A“Divide-by-OddNumber”Injection-Locked...

Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

A “Divide-by-Odd Number” Injection-LockedFrequency Divider.

Examensarbete utfört i Elektroniska Komponentervid Tekniska högskolan vid Linköpings universitet

av

Malik Summair Asghar

LiTH-ISY-EX--13/4653--SE

Linköping 2012

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

A “Divide-by-Odd Number” Injection-LockedFrequency Divider.

Examensarbete utfört i Elektroniska Komponentervid Tekniska högskolan i Linköping

av


LiTH-ISY-EX--13/4653--SE

Handledare: Prof. Michael Peter Kennedy, FIEEEElectrical and Electronic Engineering, University College Cork

Examinator: Prof. Atila Alvandpourisy, Linköpings universitet

Linköping, 15 December, 2012

Avdelning, InstitutionDivision, Department

Division of Electronic DevicesDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

DatumDate

2012-12-15

SpråkLanguage

Svenska/Swedish Engelska/English

RapporttypReport category

Licentiatavhandling Examensarbete C-uppsats D-uppsats Övrig rapport

URL för elektronisk versionhttp://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-88014

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-88014

ISBN—

ISRNLiTH-ISY-EX--13/4653--SE

Serietitel och serienummerTitle of series, numbering

ISSN—

TitelTitle A “Divide-by-Odd Number” Injection-Locked Frequency Divider.

FörfattareAuthor


SammanfattningAbstract

The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is well-known for its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.

In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.

Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divide-by-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

NyckelordKeywords Injection-Locked Frequency divider (ILFD), Phase Locked Loop(PLL), Frequency

divider (FD)

Abstract

The use of resonant CMOS frequency dividers with direct injection in fre-quency synthesizers has increased in recent years due to their lower power con-sumption compared to conventional digital prescalers. The theoretical and experi-mental aspects of these dividers have received great attention. This masters thesiswork is a continuation of earlier work, based on the fundamentals of Injection-Locked Frequency Dividers (ILFD’s). The LC CMOS ILFD with direct injectionis well-known for its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.

In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.

Over the years, numerous ILFD circuit topologies have been proposed, mostof which have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divide-by-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

v

Acknowledgments

First of all I would like to thank Almighty Allah,who gave me strength andknowledge to carry out my masters degree and thesis work. I would like to thankmy parents and family who were always there to provide me with moral supportand gave me the confidence to accomplish my study tasks.

Secondly, I would like to pay my deepest gratitude to my respected supervi-sor Prof. Michael Peter Kennedy for providing me with the opportunity to workon this project. I feel very blessed to work under his dynamic and encouragingsupervision. He is a man of responsibility, divergent knowledge, sharp thinkingability, producing multiple solutions and having excellent leading skills. His guide-lines and knowledge not only helped me with this project but will also remain asa useful asset for my future life, educational and professional career.

Further more, I would like to thank my examiner Prof.Atila Alvandpour andmy University, Linköping University, for providing me with the opportunity todo my master thesis as an ERASMUS exchange student and also for helping meout in all administrative issues. I would also like to thank University CollegeCork Ireland and Tyndall National Institute for providing me with this valuableopportunity to study in Ireland.

Lastly, I would like to thank my classmate M.A.Awan and two UCC studentsHuiyuan Xing and Xi Wu for their initial guidelines and support for this project.Here, I would like to mention my gratitude for the cooperation and support pro-vided by the MCCI team in Tyndall for the cadence support. This work wassupported in part by Science Foundation Ireland under grant 08/IN.1/I854 andby the European Commission under the ERASMUS program.

I hope this work will be a stepping stone for all researchers and future workin the field of Injection-Locked Frequency Dividers.

vii

Contents

1 Introduction 71.1 PLL Synthesizer and ILFD . . . . . . . . . . . . . . . . . . . . . . 71.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Background and Previous Work 132.1 LC CMOS Injection Locked Frequency Dividers . . . . . . . . . . . 13

2.1.1 LC CMOS ILFD With Tail Injection . . . . . . . . . . . . . 142.1.2 LC CMOS ILFD with Direct injection . . . . . . . . . . . . 15

2.2 Arnold Tongue Scenario . . . . . . . . . . . . . . . . . . . . . . . . 162.3 Devil’s staircase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.4 Brute Force Method . . . . . . . . . . . . . . . . . . . . . . . . . . 192.5 Previous work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.5.1 Divide by even number . . . . . . . . . . . . . . . . . . . . 212.5.1.1 Experimental Characterization . . . . . . . . . . . 212.5.1.2 Measurement Setup . . . . . . . . . . . . . . . . . 22

2.5.2 LabVIEW Algorithms . . . . . . . . . . . . . . . . . . . . . 232.5.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . 24

2.5.3.1 Frequency Sweeping Results . . . . . . . . . . . . 242.5.3.2 Boundry Following Results . . . . . . . . . . . . . 252.5.3.3 Boundry Finding Results . . . . . . . . . . . . . . 25

2.5.4 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3 Divide-by-Odd Number 293.1 Developed Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.2 Experimental Characterization . . . . . . . . . . . . . . . . . . . . 31

3.2.1 ILFD on Bread-Board . . . . . . . . . . . . . . . . . . . . . 313.2.2 Components and Parameters . . . . . . . . . . . . . . . . . 323.2.3 Differential Signal . . . . . . . . . . . . . . . . . . . . . . . 343.2.4 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . 353.2.5 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.2.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . 36

3.3 Symmetric Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.3.1 Components and Parameters . . . . . . . . . . . . . . . . . 37

ix

x Contents

3.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . 383.4 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4 Modeling and Simulations 414.1 Modeling and Spice Simulations . . . . . . . . . . . . . . . . . . . . 41

4.1.1 Spice Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 424.1.2 MOSFET Models . . . . . . . . . . . . . . . . . . . . . . . . 434.1.3 SPICE Runtime Algorithm . . . . . . . . . . . . . . . . . . 434.1.4 MATLAB Post-processing Algorithm . . . . . . . . . . . . . 434.1.5 SPICE and MATLAB Simulations Results . . . . . . . . . . 45

4.2 Symmetric Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.2.1 Spice Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.2.2 SPICE and MATLAB Simulations Results . . . . . . . . . . 47

4.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5 Conclusion and Future Work 495.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495.2 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.3.1 Analytical Model . . . . . . . . . . . . . . . . . . . . . . . . 515.3.2 Monolithic Implementation . . . . . . . . . . . . . . . . . . 51

Bibliography 53

A LabVIEW Algorithms 57A.1 Frequency Sweeping . . . . . . . . . . . . . . . . . . . . . . . . . . 57A.2 Boundary Following . . . . . . . . . . . . . . . . . . . . . . . . . . 60A.3 Boundary Finding . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

B Matlab Post-Processing Code 70B.1 Frequency Sweeping . . . . . . . . . . . . . . . . . . . . . . . . . . 70B.2 Boundary Following . . . . . . . . . . . . . . . . . . . . . . . . . . 72B.3 Boundary Finding . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

C Spice Netlist and Matlab Code 75C.1 Spice Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75C.2 Spice Netlist for Symmetric Circuit . . . . . . . . . . . . . . . . . . 76C.3 Matlab Post-Processing Code . . . . . . . . . . . . . . . . . . . . . 78

List of Figures1.1 A simple frequency synthesizer comprised of a PLL. . . . . . . . . 81.2 Jang et al. [26] use a CMOS LC oscillator circuit with multiple

inductors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 LC CMOS ILFD With Tail Injection. . . . . . . . . . . . . . . . . 142.2 LC CMOS ILFD With Direct Injection. . . . . . . . . . . . . . . . 152.3 The bifurcation diagram explaining the locking behavior and the

Arnold tongues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.4 LC CMOS ILFD With Direct Injection. . . . . . . . . . . . . . . . 172.5 Devil’s staircase diagram showing wide steps for ρ=2,4,6,8 and nar-

row steps for ρ=3,5,7. . . . . . . . . . . . . . . . . . . . . . . . . . 182.6 Tiebout’s classical direct injection-locked oscillator topology [19]. . 192.7 Measured locking regions in the LC CMOS ILFD with direct injec-

tion for ρ=2, 4 and 6 [30]. . . . . . . . . . . . . . . . . . . . . . . . 202.8 LC CMOS ILFD With Direct Injection on Breadboard. . . . . . . 222.9 Measurement Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . 232.10 Experimental results forthe Frequency Sweeping algorithm applied

to the LC CMOS ILFD with direct injection in Fig. 2.2 . . . . . . . 242.11 Experimental results for the Boundary following algorithm showing

locking regions corresponding to ρ=2, 3, 4, 5, 6 and 7. . . . . . . . 252.12 Experimental results for the boundary finding algorithm showing

locking regions coressponding to ρ=2, 3, 4, 5, 6 and 7. . . . . . . . 26

3.1 Modified LC CMOS ILFD with direct injection for Divide-by-Oddnumber. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 ILFD implementation On bread-board. . . . . . . . . . . . . . . . . 313.3 Pin assignment of CD4007UBE. . . . . . . . . . . . . . . . . . . . . 323.4 RC network for combining Vac and Vdc. . . . . . . . . . . . . . . . 333.5 Instrumentation Amplifier for getting differential output. . . . . . . 343.6 Pin assignment of LT1229 Instrumentation Amplifier. . . . . . . . 353.7 Measurement Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . 353.8 Experimentally measured Arnold tongues corresponding to ρ=2,3,4,5,6

and 7 in the modified circuit of Fig. 3.1 . . . . . . . . . . . . . . . . 373.9 Symmetric Circuit of the ILFD with direct injection. . . . . . . . . 383.10 Experimental Results for the Symmetric Circuit of the ILFD with

direct injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.1 H-Spice Circuit schematic of the developed Divide-by-Odd ILFD. . 424.2 Spice model for MOS transistors in Figure. 4.1 with zero threshold

modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434.3 Spice Output ASCII data file presented to Matlab. . . . . . . . . . 444.4 Spice simulation results for divide-by-2 and divide-by-3 locking re-

gions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.5 Spice simulation results for divide-by-2 and divide-by-3 locking re-

gions without parasitic impedance networks. . . . . . . . . . . . . . 46

2 Contents

4.6 H-Spice Circuit schematic of the Symmetric Circuit. . . . . . . . . 474.7 Spice simulation results for divide-by-2 and divide-by-3 locking re-

gions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

A.1 Block diagram of the frequency sweeping algorithm. . . . . . . . . 58A.2 Control panel of the Frequency Sweeping algorithm. . . . . . . . . 58A.3 Measurement of tongues in Boundary following algorithm. . . . . . 60A.4 Concept behind finding a boundary point in Boundary following

algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62A.5 Control panel of boundary finding algorithm. . . . . . . . . . . . . 64A.6 The half interval search method concept for the boundary finding

algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65A.7 Measurement of tongues using the boundary finding algorithm. . . 66A.8 Flow chart for the Main Process of the Boundary-Finding Algorithm

Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67A.9 Flow chart for the left boundary of the Boundary-Finding Algorithm. 68A.10 Flow chart for the right boundary of the Boundary-Finding Algorithm. 69

Contents 3

List of Tables2.1 Component values of the LC Tank . . . . . . . . . . . . . . . . . . 22

3.1 Component values of the LC Tank . . . . . . . . . . . . . . . . . . 323.2 Component values of the RC Network . . . . . . . . . . . . . . . . 34

4 Contents

List of Abbreviations

ILFD Injection-Locked frequency divider

VCO Voltage Controlled Oscillator

PLL Phase Locked Loop

FD Frequency Divider

FS Frequency Synthesizer

PD Phase Detector

LPF Low Pass Filter

CML Common Mode Logic

LR Locking Range

IA Instrumentation Amplifier

VISA Virtual Instrument Software Architecture

GPIB General Purpose Interface Bus

PC Personal Computer

TSMC Taiwan Semiconductor Manufacturing Company

KHz kilohertz

GHz Gigahertz

RF Radio Frequency

MHz Megahertz

nf nanofarad

pf picofarad

Contents 5

OpAmp Operational Amplifier

IC Integrated Circuit

CMOS Complementary Metal Oxide Semiconductor

mW milliwatts

Chapter 1

Introduction

This chapter provides a brief introduction to the project and the context. Sec-tion 1.1 provides a brief introduction to applications of PLL based frequency syn-thesizers while Section 1.2 talks about the objectives of this project, highlightingsome of the previous and current work in the field of ILFD’s.

1.1 PLL Synthesizer and ILFD

A frequency synthesizer is an electronic system for generating a range of frequen-cies. Frequency dividers (FD) are widely used as building blocks in the imple-mentation of Phase Locked Loops (PLL) based frequency synthesizers for bothwireless and wire line communications [1]. The power consumption of the divideris an important consideration when it is integrated into a complete system, partic-ularly in the case of portable communication devices. Nowadays, these have a lotof applications such as GPS systems, radio receivers, radio telephones, mobile tele-phones satellite receivers, etc. Frequency synthesizers are capable of generating arequired output signal by combining frequency division, frequency multiplication,and frequency mixing operations. Phase-locked loop based synthesizers are widelyused in current wireless applications.

A phase locked loop (PLL) is a feedback control system. A phase detector(PD) compares the phases of its two input signals and, depending on the differ-ence between them, it generates a proportional error signal.The error signal thengoes through a low pass filter and afterwards is used as a control voltage for avoltage-controlled oscillator (VCO) which generates an output signal frequency.

7

8 Introduction

The output signal frequency is then fed back to the phase detector through afrequency divider, producing a negative feedback loop [2].

Figure 1.1: A simple frequency synthesizer comprised of a PLL.

A simple frequency synthesizer comprised of a PLL is shown in Fig. 1.1.It contains a phase detector (PD), a low-pass filter (LPF), a voltage-controlledoscillator (VCO), and a frequency divider (FD) [3]. The output signal frequencyfout is divided to a lower frequency fdiv which is then locked to the phase of a fixedreference signal with frequency fref . As can be seen from Fig. 1.1, the frequencydivider comprises two sub blocks. One is called a prescaler; it divides by a fixednumber Np. The second one is a programmable divider which divides by a rationalnumber Nv/M , where Nv and M are positive integers. When the loop is in thelockes condition, then

Fout = N

MFref . (1.1)

where N=NpNv. If M=1, the synthesizer is called an integer-N synthesizer.Otherwise, if M 6= 1, the synthesizer is called a fractional-N synthesizer. The roleof the prescaler is to divide the output frequency by a positive integer and to passthis signal to a programmable divider [4]. The prescaler is the focus of the masterthesis work carried out in this project.

An Injection-Locked Frequency Divider (ILFD) is capable of dividing an inputinjection signal with a high frequency to produce an output signal with a lowerfrequency with a fixed frequency ratio between the injected input signal frequencyand the output signal frequency.

1.2 Objectives 9

The key parameters of an ILFD are:

1. The rotation number ρ: This is the ratio of the input signal frequency to theoutput signal frequency.

2. The locking range (LR): For a given rotation number ρ, the range of theinput signal frequency over which the output signal frequency is rationallylocked to the input signal frequency is called the locking range.

3. Phase Noise: The circuit noise can disturb the oscillator’s output phase.Generally, all oscillators possess an amplitude-limiting phenomenon so, atthe output of the oscillator, phase noise dominates [5].

1.2 Objectives

The use of digital frequency dividers is constrained at high frequencies by theirhigh power consumption which increases rapidly with frequency [6]. As an alter-native, analog frequency dividers have lower power consumption and high speedand frequency capabilities [7]. FDs can be realized using Common Mode Logic(CML) [8], [9], dynamic logic [10], Miller dividers [11] and Injection Locked Fre-quency Dividers (ILFD) [12]. Compared to CML and Miller dividers, the powerconsumption of an ILFD does not increase significantly with frequency.

An ILFD is an electronic oscillator which produces an output signal whoseperiod (equivalently, zero-crossing rate) is rationally related to that of the inputsignal [13]. When there is no injected input signal, the oscillator oscillates with afree-running frequency f0. When an injection signal Vi is applied with a frequencyfs, then the output signal Vo oscillates with a frequency fd. The ratio of fs/fd

is called the rotation number, denoted by ρ [14]. This locking behavior is due tothe nonlinear phenomenon of synchronization, also known as entrainment or 1 : morder injection locking [15]–[17].

The advantage of the ILFD is that it has the potential for low power operationbecause the relatively small perturbation by the input signal does not significantlyaffect the power consumption of the underlying oscillator [18]. However, ILFDshave two major drawbacks. Firstly, they are poorly understood from a theoreticalpoint of view, despite a long history of research and significant progress sincethe advent of computational nonlinear dynamics [16, 17]. Secondly, the ILFD isbandpass in nature, meaning that it divides correctly only over a small range offrequencies. This is related to the entrainment phenomenon; the oscillator locksto the perturbing input signal with the correct frequency division ratio ρ only overa limited range of frequencies, the so-called Locking Range (LR).

10 Introduction

Circuit topologies which realize frequency division by even numbers, e.g.divide-by-2 prescalers, have been studied extensively in the literature [19]–[25]. In orderto avoid pulling in transceivers, there is a demand from frequency planners fordivision by numbers other than two, and in particular, division by odd numbers.In recent years, frequency division by odd numbers, particularly divide-by-3, hasreceived increasing attention.

Jang et al. [26] and Lee et al. [27] use CMOS LC oscillator circuits withmultiple inductors. In the circuit schematic shown in Fig. 1.2, the drain current Id

of the MOSM5 at which the injection voltage Vi is applied contains odd harmonicfrequency components at ωo and 3ωo [26]. The third harmonic component of thecurrent at 3ω0 sees a higher impedance load composed of two inductors than thefundamental drain current harmonic component at ω0. The third harmonic ofthe MOS M5 drain voltage is fed back to the gate of the MOS M5 through aparasitic gate-drain capacitor, so that the gate voltage of MOS M5 has a third-order harmonic component. This, in turn, allows the circuit to realize a divide-by-3locked signal. Most of the chip area and power are consumed by the inductors.Consequently, this circuits occupies a large chip area due to multiple inductorsand also has a large power consumption.

Figure 1.2: Jang et al. [26] use a CMOS LC oscillator circuit with multiple induc-tors.

The main objective of this master thesis is to study an existing topology ofLC CMOS ILFD, and specifically to modify it so that it has wide locking regions

1.2 Objectives 11

with odd rotation numbers. In this thesis, we propose a simpler circuit, alsobased on a CMOS LC oscillator, but with a single inductor. We describe theconventional divide-by-2 oscillator on which this work is based and the methodwhich we have used to characterize its locking behavior. Furthermore, we introduceour modification to the CMOS LC oscillator with direct injection which makes itsuitable for division-by-odd numbers.

Chapter 2

Background and PreviousWork

This chapter presents background information about ILFDs by explaining theexisting topologies and exploring previous work done in this field.

Section 2.1.1 describes the classical topology of an ILFD with tail injectionwhile Section 2.1.2 talks about the improved technique of an ILFD with direct in-jection. Section 2.2 discusses bifurcation theory and the Arnold’s tongues scenarioof locking regions. Section 2.3 describes the method of the devil’s staircase forcharacterizing rotation numbers. Section 2.4 explains the brute force method forfinding the boundaries of Arnold tongues. Section 2.5 gives an overview of variousresearch results in the field of ILFDs prior to this work.

2.1 LC CMOS Injection Locked Frequency Di-viders

An injection-locked frequency divider (ILFD) is an oscillator to which a periodicinput is applied.This input signal is regarded as the injection signal. ILFDs aregenerally categorized into two basic topologies: One is indirect injection throughthe tail and the other is direct injection.

13

14 Background and Previous Work

2.1.1 LC CMOS ILFD With Tail Injection

These days, a widely used LC CMOS differential injection-locked oscillator topol-ogy is the LC CMOS ILFD with tail injection [19]. The circuit diagram of an LCCMOS ILFD with tail injection is shown in Fig. 2.1.

V i

Vin

M5

Figure 2.1: LC CMOS ILFD With Tail Injection.

The main disadvantages of this classical topology is its large input capacitanceand its small input locking range.Furthermore, the single-ended input is consideredto have less advantages when a VCO and divider are integrated on chip.The smalllocking range of the LC CMOS with tail injection is due to the inefficient injectionpath through the tail transistor M5. The injected current of M5 vanishes into thecapacitance of the tail node when we operate at higher frequencies. Similarly, another disadvantage of this classical topology is that M5 should have a large widthin order to provide the input transconductance and tail DC current. Replacingthe tail transistor (M5) with an NPN transistor could give the benefit of highertransconductance. In order to avoid these problems, an LC CMOS ILFD withdirect injection has been developed [19].

2.1 LC CMOS Injection Locked Frequency Dividers 15

2.1.2 LC CMOS ILFD with Direct injection

We consider a direct injection locked frequency divider (ILFD) in this thesis. Thecircuit diagram of the LC CMOS ILFD under consideration is shown in Fig. 2.2.

Vi

Figure 2.2: LC CMOS ILFD With Direct Injection.

This LC CMOS ILFD comprises an oscillator and an additional transistor.The oscillator comprises an LC tank and four transistors (M1-M4). The LC tankhas a capacitor in parallel with a series combination of an inductor and a resistor.The four transistors M1 to M4 include two PMOS transistors and two NMOStransistors.The four transistors M1 to M4 work as a negative resistance network.The additional transistor M5 is an NMOS transistor and is used to couple theinjected signal to the LC tank. When no injection signal is applied to M5, thecircuit oscillates with an unforced frequency fo which is also known as the naturalfrequency. When we drive our circuit with an injected input signal Vi at frequencyfs then the output signal Vo acquires the frequency fd. The ratio of the inputsignal frequency fs to the output signal frequency fd, namely fs/fd is called therotation number, denoted by ρ. Under appropriate conditions, the output signal


locks to the injected signal in such a way that the frequency of the input signal isan integer multiple of the frequency of the output signal.

This improved topology with direct injection overcomes the drawbacks of theclassical tail injection topology.The injected signal is provided directly throughM5, which can be designed much smaller than the tail transistor due to the moreefficient injection scheme. The transistorM5 acts as a switch which can be realizedby an NMOS transistor or a PMOS transistor [19].

2.2 Arnold Tongue Scenario

Nonlinear dynamics provides a paradigm for frequency entrainment (injection lock-ing), namely the so-called standard circle map or sine map [28]. Consider a first(dependent) oscillator with an unforced frequency f0 that is driven by a second(independent) oscillator with frequency fs. If the phase θ of the first oscillator issampled at the frequency of the second oscillator, then samples are described bya discrete time dynamical system of the form

θ[n+ 1] = θ[n] + Ω− k

2π sin(2πθ[n]), (2.1)

where Ω= f0/fs is the ratio of the unforced and injected signals and k isthe strength of the coupling.The behavior of this system is summarized in a twodimensional bifurcation diagram, as shown in Fig. 2.3. The bifurcation diagramis organized into regions called Arnold tongues; inside each tongue, the rotationnumber is constant.

The abscissa (horizontal axis) in Fig. 2.3 shows the relative frequency of theinjected signal and the ordinate (vertical axis) k is the strength of the couplingbetween the input signal and the oscillator. θ is the phase of the first oscillator.The bifurcation diagram is organized into regions called Arnold tongues; the rota-tion number ρ is constant inside each tongue.The bifurcation diagram in Fig. 2.3shows Arnold tongues corresponding to rotation number 5/1, 4/1, 3/1, etc. [28].

In this work, we use a similar way to present the locking range for differentconstant rotation numbers, as shown in Fig. 2.4.

The main idea behind the synchronization of an oscillator and the appliedinput injected signal can be analyzed in terms of the locking regions which havea typical V-shape called Arnold tongues.The locking behavior is due to the non-linear phenomenon of synchronization. Fig. 2.4 shows locking regions in a typical

2.2 Arnold Tongue Scenario 17

Figure 2.3: The bifurcation diagram explaining the locking behavior and theArnold tongues .

Figure 2.4: LC CMOS ILFD With Direct Injection.

LC CMOS oscillator. The abscissa is the ratio fs/fd, the normalized injectionfrequency. The ordinate is A, the amplitude if the injected signal. The triangularregions in Fig. 2.4 are called Arnold tongues.These correspond to the ranges ofthe input frequency over which the division ratio ρ is constant.The width of atongue at a given input amplitude A is known as Locking range (LR). For a givenrotation number ρ, there is a unique tongue which has a left boundary and a right


boundary.The input frequency where these two boundaries meet is known as thecenter frequency. For every given rotation number ρ, the center frequency is givenby ρ/

√LC. For example, for ρ=2 the center frequency would be 2/

√LC. These

locking regions can be determined accurately by a variety of algorithms which wewill discuss in Sec. 2.5.2.

2.3 Devil’s staircase

There is another simple and useful method to characterize the bifurcation diagram.It is known as the Devil’s staircase. The devil’s staircase is a monotonically in-creasing function of fs with horizontal levels of finite width at each rational valueof ρ. We can plot the Devil’s staircase by keeping the value of A fixed and takinga cross section through the bifurcation diagram. As can be seen in Fig. 2.5, thehorizontal steps correspond to the different tongues. In each horizontal step of thedevil’s staircase plot, the ratio ρ is constant [28].

Figure 2.5: Devil’s staircase diagram showing wide steps for ρ=2,4,6,8 and narrowsteps for ρ=3,5,7.

For large values of A, there is overlap between the different tongues. In thisregion, the devil’s staircase can be useful to determine whether the tongues overlapor not. The overlapping of tongues corresponding to different rotation numbers

2.4 Brute Force Method 19

leads to hysteresis effects and chaos [29].

2.4 Brute Force Method

The brute force method is another useful method, and it is the basis of the numeri-cal method described in Sec. 2.5.2, for determining the ranges of the different lock-ing regions of the ILFD. The brute force method calculates the rotation numberon a grid of points which correspond to fixed values of frequency and amplitude.The distance between two consecutive measurement points is predefined and isknown as the step size. The locking regions of the ILFD can be determined bycalculating the ratio ρ at each point.The interval from the start boundary pointto the end boundary point is known as the locking range for a specific rotationnumber. One of the major drawback of this method is the time required to findthe locking regions for different rotation numbers. Also, it does not provide anyinformation regarding the shapes of the Arnold tongues [29].

2.5 Previous work

Marc Tiebout [19] was the first to describe the CMOS Direct Injection-Locked fre-quency divider. In his paper [19], the author presented a novel circuit topology forILFD’s to achieve a wider locking range, and experimentally verified the features.The classical Injection-locked frequency divider with direct injection topology byTiebout is shown in Fig. 2.6.

Figure 2.6: Tiebout’s classical direct injection-locked oscillator topology [19].


Daneshgar, et al. [3], [20], used bifurcation theory and presented a nonlinearapproach to predict the widths of locking regions. They presented a nonlinearapproach based on the applications of bifurcation theory to predict where thelocking range is wider. Daneshgar supported his approach by simulations andexperimental verification of the circuit ILFD.

Daneshgar, et al. [3], [20], focused their research experiments and simulationon the injection locked frequency diver with tail injection. They did not publishmuch on the injection locked frequency divider with direct injection.

Kennedy, et al. [30] carried on the next phase of this research. They reporteda phenomenological study of the LC CMOS Injection Locked frequency dividerwith direct injection. In their work, they considered the effects of various factorson the locking behavior. These factors include the amplitude of the injected signal,the harmonic components of the injected signal, the size of the switching transis-tor, and the DC component of the switching transistor. They also presented a newalgorithm for determining the boundary points of the locking regions for charac-terizing the ILFD behavior [4]. In their work, they analyzed the locking regions(Arnold’s tongues). The measured Arnold’s tongues produced in this paper [30]are shown in Fig. 2.7.

Figure 2.7: Measured locking regions in the LC CMOS ILFD with direct injectionfor ρ=2, 4 and 6 [30].

The measured Arnold Tongues can be separated into 3 regions. Region 1 cor-responds to the low amplitude forcing regime, which is modeled well by the classi-cal Arnold tongue paradigm. Region 2 shows some evidence of overlap. Here, thewidth of the divide-by-2 tongue grows rapidly with increasing amplitude, and thedivide-by-4 tongue bends away to make room for it. In Region 3, the tongues are

2.5 Previous work 21

again distinct. Their widths remain almost constant with the increasing amplitudeof the perturbation signal. This region has been called a saturation region [30].

2.5.1 Divide by even number

In this section, we will discuss the divide-by-even number ILFD, which has beenunder consideration in previous work. We will describe the experimental charac-terization of the ILFD under test. Furthermore, we explain the circuit implemen-tation and the measurement setup used for the experiments. We will briefly givea description about the algorithms used for the experimental characterization ofthe locking regions for the ILFD under test. In the end, we will reproduce the pre-vious experimentally measured results for the circuit under test by using variousalgorithms and analyze these results.

2.5.1.1 Experimental Characterization

Beyond the theory of the Injection locked frequency divider, an experimental char-acterization of different topologies of ILFD’s is necessary. In this section, we willexplain and physically realize the circuit topology of the ILFD which has beenunder consideration in previous research work.

The circuit under test is the LC CMOS ILFD with direct injection, as shownin Fig. 2.2.

To get started with the experimental characterization of the ILFD undertest we built a physical prototype of the circuit with discrete components on abreadboard. The breadboard implementation of the LC CMOS ILFD with directinjection is shown in Fig. 2.8.

In our design, we use Texas Instruments CD4007UBE CMOS DUAL COM-PLEMENTARY PAIR PLUS INVERTER for the implementation of the five tran-sistors (M1-M5). The CD4007UBE comprises three PMOS transistors and threeNMOS transistors.

In the circuit implementation on the breadboard, two CD4007UBE chips areused. On the first chip, two PMOS transistors (M1 and M2) and two NMOStransistors (M3 and M4) form the core of the ILFD.These two cross-coupled pairsof CMOS inverters act as a negative resistance. On the second CD4007UBEchip the fifth NMOS transistor M5 is implemented which acts as an input switchthrough which the injected signal is coupled. M5 is implemented on another chipbecause when it is required to increase the size of the NMOS transistor, it can be


Figure 2.8: LC CMOS ILFD With Direct Injection on Breadboard.

done by using NMOS transistors available on the second chip. It is implementedby connecting three NMOS transistors in parallel.The input transistorM5 couplesthe injection signal Vi through an RC bias network. The values of the componentsof the LC tank are shown in the Table 2.1. These values were used in previousresearch [30] and are used in this work also.

Component Value UnitsResistor R 235 ΩCapacitor C 57 pFInductor L 1246 µH

Table 2.1: Component values of the LC Tank

The circuit is powered by two DC power supplies. One power supply provides9V DC as V DD while the other power supply provides the DC bias componentfor the injected input signal. The latter can produce an offset ranging from 0V to9V DC.

2.5.1.2 Measurement Setup

The experimental set-up in the laboratory is shown in Fig. 2.9


Figure 2.9: Measurement Setup.

In the measurement setup, we are using an Agilent 33250A function genera-tor to provide the sinusoidal component of the injected signal. The generator iscontrolled by the computer, which is used to set the frequency fs and amplitude Aof the input sinusoidal signal. The ILFD under test is labeled Nonlinear Oscillatorin Figure 3.7. We are using an Agilent 53132A universal counter to calculate theratio between the frequencies of the input signal and the output signal and alsodetermining the boundary points of the locking regions. We observe the inputand output signals using a Tektronix TDS3034B oscilloscope. We connect a PCto the instruments with GPIB cables. The instrument control, data acquisition,and processing algorithms are programmed using LabView. The acquired data isthen post-processed using Matlab to calculate the Arnold tongues correspondingto different locking regions

2.5.2 LabVIEW Algorithms

LabVIEW is the abbreviation for Laboratory Virtual Instrumentation EngineeringWorkbench. LabView is a system design platform which makes use of a visual pro-gramming language. LabVIEW can perform a variety of tasks such as instrumentcontrol, data acquisition, and industrial automation. Over the years, a numberof different methods and tools have been used by researchers to characterize thelocking behavior of ILFD’s. Some of these were explained briefly in the previ-ous sections. To analyze and measure the characteristics and locking behavior ofILFD’s over large amplitude and frequency ranges, an efficient LabVIEW algo-rithm should be used. There are three LabVIEW algorithms which the authorstudied and analyzed for finding the boundary points and the characteristics ofthe locking behavior of the ILFD under test. These are;

1. Frequency Sweeping

2. Boundary Following


3. Boundary Finding.

In the Appendix A, a brief description of all the three LabView algorithmsis given for the understanding of the reader.

2.5.3 Experimental Results

In the previous section three LabVIEW algorithms were mentioned. In this section,we present results for these algorithms when applied to the LC CMOS ILFD withdirect injection shown in Fig. 2.2. The results are produced for the different divideratios by post processing using Matlab.

2.5.3.1 Frequency Sweeping Results

Experimentally measured results plotted using the frequency sweeping algorithmare shown in the Fig. 2.10. The frequency interval is 5 kHz and amplitude intervalis 0.1V . The injection input signal has a DC bias of 6.03V and is applied tothe input transistor M5 with single length and single width. From the plot, itis clear that the divide-by-even regions are wider and the divide-by-odd regionsare narrower. The divide-by-3 region disappears when the amplitude is above 3V .Therefore, the LC CMOS ILFD with direct injection under test can divide by evendivision ratios but is not good at dividing by odd numbers. The Matlab code usedfor post processing the acquired data is shown in Appendix B.

Figure 2.10: Experimental results forthe Frequency Sweeping algorithm appliedto the LC CMOS ILFD with direct injection in Fig. 2.2 .


2.5.3.2 Boundry Following Results

The experimentally measured results using the Boundary following algorithm areshown in Fig. 2.11. The plot exhibits similar tongues to the frequency sweepingalgorithm as expected. The divide-by-even locking regions are wide and the divide-by-odd locking regions are very narrow. The Matlab code used for post processingis shown in Appendix B.

Figure 2.11: Experimental results for the Boundary following algorithm showinglocking regions corresponding to ρ=2, 3, 4, 5, 6 and 7.

2.5.3.3 Boundry Finding Results

The experimentally measured results using the boundary finding algorithm areshown in Fig. 2.12. From the plot it can be seen that the divide-by-even num-ber locking regions are much wider than the divide-by-odd locking regions. Thetongues becomes almost vertical when the injected input signal amplitude is largerthan 3.5 V . The Matlab code used for post processing is shown in Appendix B.


Figure 2.12: Experimental results for the boundary finding algorithm showinglocking regions coressponding to ρ=2, 3, 4, 5, 6 and 7.

2.5.4 Analysis

In previous section, we presented experimental measured results from the threelabVIEW algorithms showing the locking behavior of the LC CMOS ILFD withdirect Injection. From the three sets of results, it can be seen that the divisionratios ρ=2,4,6,8 (divide-by-even) have wide locking ranges. The division ratiosρ=3,5,7 (divide-by-odd) are very narrow and disappear with increasing input signalamplitude. Moreover the Divide-by-2 and divide-by-4 locking regions for the LCCMOS ILFD with direct injection are wider then the LC CMOS ILFD with tailinjection [4]. Furthermore, the slopes of the boundaries of the divide regionsincrease and become almost verticall when the injected input amplitude goes above3.5 V . This phenomenon was first observed experimentally and reported in [4] andhas been reproduced by the author.

From the experimentally measured results, it can be concluded that the deviceunder test, the LC CMOS ILFD with direct injection shown in Fig. 2.2, can divide


by ρ=2,4,6,8 very well. But it is not as effective at dividing by ρ=3,5,7. Thismotivates the design of a variant of this circuit which will advance the state of theart by being able to divide as effectively by odd numbers as by even ones.

Chapter 3

Divide-by-Odd Number

The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. Numerous circuit topologies havebeen proposed, most of which have been optimized for division by even numbers,especially divide-by-2. It has been more difficult to realize division by odd num-bers, such as divide-by-3. This chapter describes a simple modification to a CMOSinjection locked frequency divider (ILFD) with direct injection, which gives it awide locking range both in the “divide-by-odd number” mode and in the con-ventional “divide-by-even number” regime, thereby opening up applications whichrequire frequency division by an odd number.

This chapter presents the circuit architecture and experimental validation ofits operations. Section 3.1 proposes a modified ILFD with direct injection. Sec-tion 3.2 explains the circuit architecture, the measurement setup, the algorithmsused for experimentally characterizing the ILFD under test and the experimentallymeasured results. Section 3.3 shows the symmetric circuit architecture and theexperimental results for it and in the last Section 3.4 these results are analyzed.

3.1 Developed Model

We consider a direct injection locked frequency divider (ILFD) in this work. Thecircuit diagram of the modified LC CMOS ILFD under consideration is shown inFig. 3.1.

29

30 Divide-by-Odd Number

C5Vi

Figure 3.1: Modified LC CMOS ILFD with direct injection for Divide-by-Oddnumber.

The modified LC CMOS ILFD comprise an oscillator with an additionaltransistor and capacitor. The oscillator comprises an LC tank and four transistors.The LC tank has a capacitor in parallel with a series combination of an inductorand a resistor. The four transistors M1 to M4 include two PMOS transistorand two NMOS transistors.The four transistors M1 to M4 work as a negativeresistance network. The additional transistorM5 is an NMOS transistor and isused to couple the injected signal to the LC tank(so-called direct injection). Weintroduce an additional capacitor between the gate and drain of M5. When noinjection signal is applied to M5, the circuit oscillates with an unforced frequencyf0. When we drive our circuit with an injected input signal Vi at frequency fs,the output signal V0 has a frequency fd. The ratio of the input signal frequencyfs to the output signal frequency fd, namely fs/fd, is called the rotation number,denoted by ρ. Under appropriate conditions, the output signal locks to the injectedsignal in such a way that the frequency of the input signal is an integer multiple offrequency of the signal. With this circuit, we can get both even (divide-by-2) andodd (divide-by-3) rotation numbers over ranges of the input frequency of similarwidth.

3.2 Experimental Characterization 31

3.2 Experimental Characterization

Beyond the theory of Injection locked frequency divider, an experimental char-acterization of the developed ILFD is necessary. In this section, we explain andphysical realization of the ILFD under consideration. Furthermore, the experi-mental setup which is used in the laboratory for observing the locking behavior ofthe ILFD under test will be explained.

3.2.1 ILFD on Bread-Board

To get started with the experimental characterization of the ILFD under test, webuilt a physical prototype of the circuit with discrete components on a breadboard.Fig. 3.2 shows the modified LC CMOS ILFD with direct injection on a breadboard.

Figure 3.2: ILFD implementation On bread-board.

In our design, we use Texas Instruments CD4007UBE CMOS DUAL COM-PLEMENTARY PAIR PLUS INVERTER for the implementation of the five tran-sistors (M1-M5). The CD4007UBE comprises three PMOS transistors and threeNMOS transistors.The pin assignment of the CD4007UBE, as provided on thedata sheet, is shown in the Fig. 3.3.

In the circuit implementation on the breadboard, two CD4007UBE chips areused. On the first chip, two PMOS transistors (M1 and M2) and two NMOStransistors (M3 and M4) are used to form the core of the ILFD.These two crosscoupled pairs of CMOS inverters act as a negative resistance. On the secondCD4007UBE chip, the fifth NMOS transistor M5 is implemented; this acts as an


Figure 3.3: Pin assignment of CD4007UBE.

input switch through which the injected signal is coupled. M5 is implemented onanother chip. When it is required to increase the size of the NMOS transistorM5,this is achieved by connecting three NMOS transistors in parallel. An additionalcapacitor C5 connects the gate to the drain of the input transistor M5.

3.2.2 Components and Parameters

We are using CD4007UBE transistors manufactured by Texas Instruments. Theadditional capacitance C5 is 560 pF . The values of the components in the RLCtank are shown in the Table 3.1

Component Value UnitsResistor R 235 ΩCapacitor C 57 pFInductor L 1246 µH

Table 3.1: Component values of the LC Tank

The injection input signal voltage Vi is applied through an RC bias network,which is shown in the Fig. 3.4.

The injected input signal is generated by combining a sinusoidal AC signalwave with a DC component, using a resistor and a capacitor. This resistor and


Figure 3.4: RC network for combining Vac and Vdc.

capacitor network is used because we cannot directly combine two different voltagesources. In the circuit diagram, the input injected signal Vin is a sinusoidal voltagewith 6.03V DC offset, whose amplitude and frequency can be controlled separately.While performing the experiment, the injection input signal was separated into twoparts. The first part consists of an AC sinusoidal signal wave Vac and the secondpart adds a DC component Vdc of 6.03 V . These two parts were combined usinga resistor and a capacitor network. Equation (3.1) shows how the resistor andcapacitor network combines the two signals:

Vin = Vdc + R

R+ 1jωC

× Vac, (3.1)

If the values of R and C are sufficiently large, we can ignore the term 1jωC ,

and, at frequencies of interest, i.e. 100kHz<fs<2MHz, the RC network has noeffect on the ac component Vac, i.e:

R

R+ 1jωC

≈ 1 (3.2)

The input sinusoidal voltage signal Vi is applied with a 6.03V DC offset. Theparameters of the RC bias network are as shown in the table 3.2.


Component Value UnitsResistor R 100 KΩ.Capacitor C 57 pFDC Offset Vdc 6.03 V .

Table 3.2: Component values of the RC Network

The circuit is powered by two DC power supplies. One power supply provides9V DC as V DD while the other power supply provides the DC bias componentfor the injected input signal. The latter is adjustable to produce an offset rangingfrom 0V to 9V DC.

3.2.3 Differential Signal

At first, the output signal which is required is the single-ended output of the LCtank. Afterwards, the differential signal is also analyzed to measure the differentialsignal between the two nodes of the LC tank. To achieve this, an instrumentationamplifier was built using discrete components on a breadboard. The instrumenta-tion amplifier’s circuit diagram is shown in Fig. 3.5.

Figure 3.5: Instrumentation Amplifier for getting differential output.

The instrumentation amplifier is implemented by using three LT1229 Dual100MHz Current Feedback Amplifiers maunfactured by Linear Technology. Thepin assignment of the LT1229, as provided by the data sheet, is shown in Fig. 3.6.

The instrumentation amplifier is powered by± 15V DC. This instrumentationamplifier adds the two single-ended outputs and gives a single differential output:


Figure 3.6: Pin assignment of LT1229 Instrumentation Amplifier.

Vout = Va − Vb (3.3)

3.2.4 Measurement Setup

The experimental set-up in the laboratory is shown in Fig. 3.7.

Figure 3.7: Measurement Setup.

In the measurement setup, we are using an Agilent 33250A function generatorto provide the sinusoidal component of the injected signal. The ILFD under testis the Nonlinear Oscillator in Fig. 3.7. We are using an Agilent 53132A universalcounter to calculate the ratio between the frequencies of the input signal and the


output signal and also the boundary points of the locking regions. We observe theinput and output signals using a Tektronix TDS3034B oscilloscope. We connect aPC to the instruments with GPIB cables. The instrument control, data acquisi-tion, and processing algorithms are programmed in LabVIEW. The acquired datais post processed using Matlab to observe the Arnold tongues corresponding todifferent locking regions.

3.2.5 Algorithms

In our work, we use the boundary finding algorithm implemented in LabVIEWwhich is explained in the Sec. A.3, in order to characterize the ILFD over largeranges of frequencies and amplitudes of the injected signal. For different values ofrotation number (i.e. 2,3,4,5,6,7), the LabVIEW program generates an output filewhich consists of the boundary points of the locking regions corresponding to theselected rotation numbers.

Afterwards, we use Matlab to plot the boundary points for these rotationnumbers.


The experimentally measured Arnold tongues corresponding to ρ =2,3,4,5,6,7 werepost processed using Matlab and are shown in Fig. 3.8.

The frequency fs of the input signal is plotted on the abscissa of the two-dimensional bifurcation diagram and the amplitude A on the ordinate. The ap-proximately triangular regions, called Arnold tongues, correspond to ranges of theinput over which the rotation number ρ (equivalently, the division ratio) is con-stant. The width of a tongue at a given input amplitude is the Locking Range(LR). By contrast with the standard circuit, tongues corresponding to even andodd division ratios have similar widths in the modified circuit. This means qual-itatively that the circuit can divide by odd numbers as well as by even ones.In particular, the locking range for divide-by-3 is comparable in size to that fordivide-by-2.

3.3 Symmetric Circuit 37

Figure 3.8: Experimentally measured Arnold tongues corresponding to ρ=2,3,4,5,6 and 7 in the modified circuit of Fig. 3.1 .

3.3 Symmetric Circuit

In order to simplify the analytical analysis of the circuit, the circuit is madesymmetric by adding an injection through a PMOS and a capacitor C6.The newdeveloped symmetric circuit for direct injection locking Frequency divider is shownin Fig. 3.9. The proposed changes to previous Asymmetric ILFD with directinjection are highlighted with red lines.M6 is complementary to M5, and C6 isequal to C5. Essentially, the ILFD is driven now symmetrically.

3.3.1 Components and Parameters

I am using CD4007UBE transistors manufactured by Texas Instruments. Theadditional capacitance C5 and C6 are 560 pf. The parameters of Components ofLC tank are similar to the Asymmetric ILFD.


Figure 3.9: Symmetric Circuit of the ILFD with direct injection.

I am applying the input signal Vin as differential inputs through two RCnetworks. I am applying the -Vin input signal as a sinusoidal voltage with a 6.03 vDC offset at the gate ofM5. Similarly I apply the +Vin input signal as a sinusoidalvoltage with a 2.97 V DC offset at the gate ofM6. The parameters of componentsof RC networks are similar to the Asymmetric ILFD.

The -Vin input signal is generated by using a simple inverting amplifier(LT1229) to get the 180 degree phase shifted signal.


The experimentally measured Arnold tongues corresponding to ρ =2,3,4,5,6,7 werepost processed using Matlab and are shown in Fig. 3.10.

3.4 Analysis 39

Figure 3.10: Experimental Results for the Symmetric Circuit of the ILFD withdirect injection.

3.4 Analysis

From Fig. 3.10, it can been seen that the tongues for the divide regions corre-sponding to ρ = 2 and 3 are of similar width. The divide region for 3 is signif-icantly wider in this work than in previous works which did not include C5 andC6. Therefore, the proposed model can divide both by even and odd numbers.This phenomena was first observed experimentally and then reproduced in simula-tions.The phenomenon has been reported in a conference paper [32] and a patentapplication [34].

Chapter 4

Modeling and Simulations

In this chapter, we will discuss the simulations of the divide-by-odd number LCCMOS ILFD with direct injection. Section 4.1 describes the Spice model andthe MOSFET model used. It talks about the Spice algorithm used for capturingthe locking behavior of the ILFD and describes the corresponding Matlab postprocessing algorithm. Finally, it shows the Spice simulation results. Section 4.2describes the implementation of the Symmetric circuit of the LC CMOS ILFDwith direct injection by explaining the schematic and simulation results. Finally,section 4.3 gives an overall analysis of the simulation results.

4.1 Modeling and Spice Simulations

In the simulation part of this project, we built a model circuit using Spice, whichis intended to replicate the experiments. Spice can predict the circuit behaviorand works in the same way as the Frequency Sweeping method which we describedearlier. Spice produces its output in the form of an ASCII listing. The listing con-sists of columns of numbers corresponding to calculated outputs V oltages and/orCurrents. Therefore, a MATLAB program is needed to post process the outputof Spice in order to plot the bifurcation diagrams.

41

42 Modeling and Simulations

4.1.1 Spice Model

SPICE is a general purpose open source analogue electronic circuit simulator. Itis a powerful program that is used in integrated circuit and board-level design tocheck the integrity of circuit designs and to predict circuit behavior.

The Spice model under consideration is shown in Fig. 4.1. The schematic isthe same as in Fig. 3.1 except for the parasitic output network. In our experiments,we use Texas Instruments CD4007UBE CMOS DUAL COMPLEMENTARY PAIRPLUS INVERTER, which have 3 complementary logic inverters. Each inverter hasan input capacitance and an output load capacitance and resistance. Therefore, formatching the experimental results to simulations we add parasitic networks at bothoutputs in our Spice model. While performing simulations, the most importantfactor is the MOSFET model. In this project, the basic aim was to match thesimulations to experiments for divide-by-odd numbers. Therefore, many types ofMOSFET models were tried to get the best results.

C3180pF

R3160K C4

180pF

R4160K

R298.7

C5560pF

Figure 4.1: H-Spice Circuit schematic of the developed Divide-by-Odd ILFD.

The complete Spice code/Spice net-list for the circuit schematic shown inFig. 4.1 is given in Appendix C.

4.1 Modeling and Spice Simulations 43

4.1.2 MOSFET Models

In the simulation, the most important component is the MOSFET model. Atransistor model is classified according to the level of sophistication, e.g. level 1,2 or 3. The higher the level, the more precise and detailed the MOSFET modelis. The sizes of the transistors in the CD4007UBE used for experiments have beenmeasured by Tyndall National Institute. In this project, in order to match thesimulations to experimental result, many types of MOSFET models were tried toget the best results. The transistor model we chose for our simulations is a Level-1MOSFET model with the factor GAMMA=0, as shown in Fig. 4.2.

Figure 4.2: Spice model for MOS transistors in Figure. 4.1 with zero thresholdmodulation.

4.1.3 SPICE Runtime Algorithm

In the SPICE algorithm, two variables are used. These are the injection frequencyfinj and the amplitude of Vinj . In order to capture the ILFD’s locking behavior, wesweep the input voltage Vinj from 0.1V to 5V and the frequency finj from 300kHzto 2000kHz. We then carry out transient simulations and store the results inASCII format in an output file. The ASCII format output file is shown in Fig 4.3.

4.1.4 MATLAB Post-processing Algorithm

The output file from H-Spice gives us the details (e.g. voltage and time) of eachpoint of the selected output waveforms.

The main idea of post-processing using MATLAB is to calculate the frequen-


Figure 4.3: Spice Output ASCII data file presented to Matlab.

cies and frequency ratios as follows :

1. It collects data from the Spice output file in the form of the output voltagedata corresponding to one value of the input frequency.

2. Perform the Fast Fourier Transform and map the voltage data from the timedomain to the frequency domain.

3. Find the peak in the frequency domain and record this frequency as theoutput frequency fd.

4. The frequency ratio is equal to the input frequency fs divided by the outputfrequencyfd.

Important Digital Signal Processing knowledge is also used in MATLAB:

1. The Fast Fourier Transform is used to determine the frequency content of adigital signal or the frequency response of a digital system.

2. The input to the Fourier Transform is a uniformly-sampled discrete-timesignal and the result of the transform is a discrete function of ω.

3. The output of the Fast Fourier Transform is periodic with period 2π. Thereal frequencies in the range 0 tofs (sampling frequency) are mapped to ωin the range 0 to 2π.

4.1 Modeling and Spice Simulations 45

4. The output of the Fast Fourier Transform is a vector of complex numbersthat is symmetrical about ω = π.

The key MATLAB functions used are as follows:

1. dlmread reads the numerical data from the Spice output data file whichcontains the ASCII data, as shown in Fig 4.3. At the top of the SpiceOutput data file, there is some simulation information which is not requiredfor our analysis. The first column (time) is also unnecessary for the analysis.Therefore, MATLAB reads the data from the first line of the numerical datadirectly. In this case, the read range in the dlmread function is [166 1001561 1]. [166 100156] is the number of lines containing relevent numeric data,and [1 1] denotes the second column..

2. fft(x): Fast Fourier Transform of the array x.

3. To find the maximum element in array A, we use [C, I] = max(A). It willfind the maximum value element in array A, then return the maximum valueto C and assign the index of the maximum value to I.

Complete MATLAB code is listed in Appendix C.

4.1.5 SPICE and MATLAB Simulations Results

Brute force transient simulations were run over a grid of points in the A-fs plane ofthe two-dimensional bifurcation diagram and the rotation number ρ was calculatedby post-processing the resulting time series using Matlab, as described above. Theresults are summarized in Fig. 4.4.

Spice simulation results using Level-1 MOSFET models without consideringthe parasitic input and output impedance networks are shown in Fig. 4.5. Fromthis Figure, it can be seen that, without considering the parasitic input and out-put impedance networks, the center frequency for the tongues shift towards theright. This causes a noticeable mismatch between the experimental and simulationresults. By adding parasitic input and output impedance networks to our Spicemodel, we can reduce this mismatch to a large extent.

Qualitatively, the widths of the divide-by-2 and divide-by-3 regions in thesimulations are similar to those found in the physical experimental implementa-tion, confirming our experimental observations that the circuit can divide by oddnumbers as well as by even numbers.


3 4 5 6 7 8 9 1 0 1 1

x 1 05

0

0 . 5

1

1 . 5

2

2 . 5C a p a c i t o r c o n n e c t e d S i n g l e M 5 , i n c l u d i n g R L C L , 7 V D C b i a s ,

F r e q u e n c y

Am

plitu

de

Figure 4.4: Spice simulation results for divide-by-2 and divide-by-3 locking regions.

Figure 4.5: Spice simulation results for divide-by-2 and divide-by-3 locking regionswithout parasitic impedance networks.

4.2 Symmetric Circuit

In the simulation part of this project, we built a model circuit using Spice ofthe symmetric circuit, which is intended to replicate the experiments. Spice canpredict the circuit behavior and works in the same way as the Frequency Sweepingwhich we introduced earlier. Spice produces its output in the form of an ASCIIlisting. The listing consists of columns of numbers corresponding to calculatedoutputs V oltages and/or Currents. Therefore, MATLAB program is needed toanalyze the output of Spice.

4.2 Symmetric Circuit 47

4.2.1 Spice Model

The Spice circuit model under consideration of the symmetric circuit is shownin Fig. 4.6. The schematic is the same as in Fig. 3.9 except the output para-sitic network. In our experiments, we use Texas Instruments CD4007UBE CMOSDUAL COMPLEMENTARY PAIR PLUS INVERTER, which have 3 complemen-tary logic inverters. Each inverter has an input capacitance at input and an outputload capacitance and resistance. Therefore, for matching the experimental resultsto simulations we add parasitic network at both outputs in our Spice model. Whileperforming simulations, the most important factor is the MOSFET model. In thisproject, the basic aim was to match the simulations to experiments for divide-by-odd numbers. Therefor many types of MOSFET models were tried to get the bestresults.

Vs 2.97V

C6 R5

MN6

Figure 4.6: H-Spice Circuit schematic of the Symmetric Circuit.

The complete Spice code/Spice net-list for the circuit schematic shown inFig. 4.6 is given in Appendix C.

4.2.2 SPICE and MATLAB Simulations Results

Brute force transient simulations were run over a grid of points in the A-fs planeof the two-dimensional bifurcation diagram and the rotation number ρ was cal-culated by post-processing the resulting time series using Matlab, as describedearlier. The model includes the input and output parasitic network. The resultsare summarized in Fig. 4.7.


Figure 4.7: Spice simulation results for divide-by-2 and divide-by-3 locking regions.

4.3 Analysis

Qualitatively, the modified ILFD exhibits both divide-by-2 and divide-by-3 be-havior, which has been observed experimentally and via Spice simulations. Fromthe Symmetric circuit simulations, the divide-by-2 and divide-by-3 regions lie inalmost the same input frequency range as was observed in the Spice simulationsfor the Asymmetric circuit. The implementation of the design in Spice and thesimulated results shows that the developed LC CMOS ILFD with direct injectioncan perform both divide-by-even and divide-by-odd numbers.

Chapter 5

Conclusion and Future Work

This chapter presents conclusions of the project work and also suggests potentiallyfruitful directions for future work in the field of ILFD’s.

Section 5.1 concludes the project work with a description of the most impor-tant achievements. Section 5.2 talks about the limitations and drawbacks foundduring the work on this project. Section 5.3 discusses the post project ideas whichcan lead to some interesting future research based on this project in the field ofILFD’s.

5.1 Conclusion

Injection-Locked frequency dividers is a well-studied topic and has been underresearch for many years. In recent years, a lot of research work has taken place.M.P Kennedy’s group in Tyndall National Institute has been working on Injection-Locked frequency dividers for many years. This masters thesis work is a con-tinuation of the previous research in order to study deeply and to analyze theperformance of Injection-Locked frequency dividers with direct injection.

This masters thesis work was carried out over a period of twenty-four weeks.In the first phase of the project, the author learned the background about ILFDs,the existing circuit behavior, the experimental setup, and SPICE. In the secondphase, the author studied the LabVIEW algorithms and used these algorithms toreproduce various earlier experimental observations and SPICE simulations. Inthe final phase of the project, the author developed a modified LC CMOS ILFD

49

50 Conclusion and Future Work

with direct injection which is capable of both divide-by-even and divide-by-oddnumbers. This phenomenon was first observed experimentally and then validatedby simulations.

Three LabVIEW algorithms were tested on the ILFD under test for charac-terizing its locking behavior. Compared to other algorithms, the boundary findingalgorithm is more efficient and accurate for measuring the boundary points of thelocking regions. This algorithm is very easy to use. For future work in the field ofILFD’s, this algorithm can be used as a certified tool. Using the boundary findingalgorithm, many earlier experimental observations and phenomena were repro-duced; for example, the dependence of the locking range on the forward body biasand the amplitude of the input injected signal, as well as the switch size. Duringthe experimental work in this project, the equipment, circuit board, transistorsand instruments were different from previous works. Therefore, after getting,the same results as previously observed, we verified the robustness of the circuitsbehavior and the efficiency of the boundary finding algorithm. Similarly, the sim-ulations also matched the experimentally observed results very closely. Therefore,the Spice model provides a strong base for future work in the field of Injection-locked frequency divider, especially for developing a mathematical model for theILFD.

For reasons associated with frequency planning and power consumption, thereis interest in developing ILFDs that are capable of dividing by numbers other thantwo. Several divide-by-3 ILFDs have been developed in recent years, but these aresignificantly more complex from an implementation point of view than comparabledivide-by-2 ILFDs.

We have developed a simple modification of a standard “divide-by-even num-ber” Direct Injection CMOS LC ILFD which enables it also to divide by oddnumbers. The design concept has been validated experimentally and by SPICEsimulations. This masters thesis work has been reported at the ICECS 2012 Con-ference [32]. We have also applied for a patent for the idea [34].

5.2 Limitations

A few limitations of this project should also be mentioned here.

In the experiment, to get precise results, and to see the waveforms on the oscil-loscope it is necessary to add an instrumentation amplifier before the final output,as discussed in the experimental characterization section of chapter three. Thisaspect of the differential signal operation was not implemented in the experiments.

5.3 Future Work 51

Consequently, some unexpected results occurred, especially in the overlap re-gions. These imprecise operations would lead to algorithm errors and then makeincorrect estimates of the locking regions.

Moreover, the boundary finding algorithm was used in a relatively low fre-quency range (less than 5MHz). Hence, the performance in the high frequencyrange should be tested and validated in the future.

5.3 Future Work

5.3.1 Analytical Model

The long-term goal of this research work is to build an accurate mathematicalmodel of the divide-by-odd circuit in order to optimize its locking behavior. Todevelop this mathematical model, future work should take both experiments andsimulation into consideration, and produce a simple mathematical model withfew nonlinear equations. Therefore, it requires a precise measuring method andhardware in the experiment and a more accurate SPICE model to replicate thelocking mechanism.

We are in the process of developing a theoretical explanation of the lockingmechanism underlying this ILFD with direct injection. For this purpose, we areworking with another modified version of the ILFD with direct injection. This newILFD model and the analytical explanation of the underlying locking phenomenonhave been submitted for publication [33].

5.3.2 Monolithic Implementation

In the future, we are prototyping an integrated circuit implementation of thedivide-by-odd ILFD with direct injection in the multi-GHz frequency range. Weare going to implement this circuit using the TSMC 65nm Cadence design envi-ronment. The target for our Cadence design is the 24 GHz ISM band that goesfrom 24.0 to 24.25 GHz. The center frequency is 24.125 GHz. The results of thisfollow-on project, when complete, will be reported elsewhere.

Bibliography

[1] J. Craninckx and M. Steyaert, “Wireless CMOS Frequency Synthesizer Design”London, U.K.: Kluwer, 1998.

[2] Wikimedia Foundation, “Frequency synthesizer”http://en.wikipedia.org/wiki/Frequency-synthesize, 2012.

[3] Daneshgar, De Feo and Kennedy, “Observations concerning the locking rangein a complementary differential LC injection-locked frequency divider-Part I:Qualitative analysis” IEEE Trans. Circuit and Systems-Part I, vol. 57, no. 1,pp. 179–188, Jan. 2012.

[4] M.P. Kennedy, H. Mo and X. Dong. “Experimental Characterization of ArnoldTongues in Injection- Locked CMOS LC Frequency Dividers with Tail andDirect Injection.” In Proc. ECCTD 2011, pp. 484–487.

[5] H. Lee and Hajimiri. “Oscillator Phase Noise: A Tutorial” IEEE JOURNALOF SOLID-STATE CIRCUITS, VOL. 35, NO. 3, MARCH 2000.

[6] B. Razavi, “Challenges in portable RF transceiver design” IEEE CircuitsDevices Mag., vol. 12, no. 9, pp. 12–25, Sep. 1996.

[7] M. M. Ghahramani, S. Daneshgar, M. P. Kennedy, and O. De Feo, “Optimizingthe design of an injection-locked frequency divider by means of a nonlinearanalysis” in Proc. Eur. Conf. Circuit Theory Des., Seville, Spain, Aug. 2007,pp. 571–574.

[8] J. Craninckx and M. Steyaert, “A 1.75 GHz/3 V dual-modulus divide-by-128/129 prescaler in 0.7µ m CMOS” in Proc. ESSCIRC, Sept.1995, pp. 254–257.

[9] D. Pfaff and Q. Huang, “A quarter-micron CMOS 1 GHz VCO/prescaler-set

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54 Bibliography

for very low power applications” in IEEE Custom Integrated Circuits Conf.Dig. Tech. Papers, May 1999, pp.649–652.

[10] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOScircuits for gigahertz single-phase clocks” IEEE J. Solid-State Circuits, vol.31, pp. 456–463, Mar. 1996.

[11] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18 µm CMOStechnology” in Symp. VLSI Circuits Dig. Tech. Papers, June 2003, pp. 259–262.

[12] S. Verma, H.R. Rategh, and T.H. Lee. “A unified model for injection-lockedfrequency dividers” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1015–1027,Jun. 2003.

[13] B. Razavi, “A study of injection locking and pulling in oscillators” IEEE J.Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004.

[14] M.P. Kennedy, K.R. Krieg, and L.O. Chua. “The devil’s staircase: the elec-trical engineer’s fractal” IEEE Trans. Circuits and Systems, vol. 36, no. 8, pp.1133–1139, Aug. 1989.

[15] R. Adler, “ A study of locking phenomena in oscillators” Proc. IRE WavesElectrons, vol. 34, no. 6, pp. 351–357, Jun. 1946.

[16] A. Pikovsky, “ Rosenblum, and J. Kurths, Synchronization. Cambridge” U.K.:Cambridge Univ. Press, 2001.

[17] M. V. Bartuccelli, J. H. B. Deane, and G. Gentile, “Frequency locking in aninjection-locked frequency divider equation” Proc. R. Soc. London A, Math.Phys. Eng. Sci., vol. 465, no. 2101, pp. 283–306, Jan. 2009.

[18] H.R. Rategh and T.H. Lee. “Superharmonic injection locked oscillators aslow power dividers” In Prof. Symp. VLSI Circuits Dig., pp. 132–135. Jun 1998

[19] M. Tiebout. “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider” IEEE J. Solid-State Circuits, vol. 39,no. 7, pp. 1170–1174, Jul. 2004.

[20] S. Daneshgar, O. De Feo and M.P. Kennedy. “Observations Concerningthe Locking Range in the Complementary Differential LC Injection-LockedFrequency Divider-Part II: Design Methodology” IEEE Trans. Circuits andSystems—Part I, vol. 58, no. 4, pp. 765–776, Apr. 2011.

Bibliography 55

[21] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee, and M.-H. Juang,“A wide locking range and low voltage CMOS direct injection locked frequencydivider” IEEE Microw. Wireless Compon. Lett, vol. 16, no. 5, pp. 299–301,May 2006.

[22] S.-L. Jang and C.-F. Lee, “A wide locking range LC-tank injection lockedfrequency divider” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 8, pp.613–615, Aug. 2007.

[23] S. Daneshgar, “Analytical Method to Predict Locking Range in Injection-Locked Frequency Dividers” PhD thesis, University College Cork, April 2010.

[24] A. Buonomo and A. Lo Schiavo. “An analytical approach to the study ofinjection-locked frequency dividers” IEEE Trans. on Circuits and Sys.-I (inpress).

[25] A. Buonomo and A. Lo Schiavo. “Nonlinear dynamics of divide-by-2 injection-locked frequency dividers” Int. J. Circuit Theory Appl. (submitted).

[26] Sheng-Lyang Jang, Chien-Feng Lee, Wei-Hsung Yeh. “A Divide-by-3 InjectionLocked Frequency Divider With Single-Ended Input” IEEE MICROWAVEAND WIRELESS COMPONENTS LETTERS, VOL. 18, NO. 2, FEBRUARY2008.

[27] I.-T. Lee, C.-H. Wang and S.-I. Liu. “Current-reused divide-by-3 injection-locked frequency divider in 65 nm CMOS” ELECTRONICS LETTERS 1stSeptember 2011, Vol. 47, No. 18.

[28] J.A. Glazier and A. Libchaber. “Quasi-Periodicity and Dynamical Systems:An Experimentalist’s View” IEEE Trans. Circuits and Systems, vol. 35, no. 7,pp. 790–809, Jul. 1988.

[29] Final Report of Xi Wu . “Injection-Locked Frequency Divider” Departmentof Electrical and Electronic Engineering,UCC, March 2012.

[30] M.P. Kennedy, X. Dong and H. Mo. “Phenomenological Study of an Injection-Locked CMOS LC Frequency Divider with Direct Injection” In Proc. ECCTD2011, pp. 480–483.

[31] Final Report of Huiyuan Xing . “Injection-Locked Frequency Divider” De-partment of Electrical and Electronic Engineering,UCC, March 2012.

[32] M.S. Asghar, M.A. Awan and M.P Kennedy. “A “Divide-by-Odd Number” Di-rect Injection CMOS LC Injection-Locked Frequency Divider” In Proc.ICECS

56 Bibliography

2012, pp. 488-491, Seville, Spain, 09-12 Dec. 2012.

[33] A. Buonomo, A. Lo Schiavo, M. A. Awan, M.S. Asghar and M.P Kennedy.“A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Twoand Divide-by-Three Operation” IEEE Trans. Circuits and Systems-Part II,**(*):***, ***. 2013 (submitted, ** December 2012).

[34] “Divide-By-Three Injection-Locked Frequency Divider”, M.P Kennedy, M.S.Asghar, M.A. Awan, A. Buonomo and A. Lo Schiavio, US patent application,filed December 2012.

Appendix A

LabVIEW Algorithms

A.1 Frequency Sweeping

The frequency sweeping algorithm is the first LabVIEW algorithm which we willanalyze and use to characterize the ILFD under test. Frequency sweeping is atype of brute force method to measure the locking behavior and to determine theboundary points of the locking regions. The LabVIEW block diagram and thecontrol panel of the frequency sweeping algorithm are shown in Figures A.1 andA.2 respectively [31].

In the frequency sweeping algorithm, the values of the parameters can be setin the control panel. Before running the algorithm, the following parameters needto be set;

1. Provide the device information such as VISA (Virtual Instrument SoftwareArchitecture) or GPIB address (General Purpose Interface Bus) which arethe interface addresses of the devices that are connected to the PC.

2. Choose, if required, the DC offset, units, and shape of the waveform of theinjected input signal.

3. Select the Start, stop and step frequencies of the desired frequency sweep.

4. Set the stop and start Vpp values for the injected input signal.

5. Set an appropriate instruction and function which will set the counter’s mea-

57

58 LabVIEW Algorithms

Figure A.1: Block diagram of the frequency sweeping algorithm.

Figure A.2: Control panel of the Frequency Sweeping algorithm.

surement mode. For example, if we want the counter to measure the bound-ary points for the output frequency then we set the instruction to measureand the function to frequency 2.

A.1 Frequency Sweeping 59

6. An output file name is to be provided which will contain the measurementresults from the counter. This file will be stored at the completion of thealgorithm in the same directory as the frequency sweeping algorithm.

7. To ensure that the instruments have sufficient time for calculations and mea-surements, a millisecond delay is to be set.This is the delay time betweenwriting the injected signal and reading back the output ratio.

The algorithm and working of the frequency sweeping program are explainedas follows:

1. First the sweep frequency range and interval are chosen which should beequal to the grid points on the X-axis. Similarly, choose the sweep amplituderange and interval which should be equal to the grid points on the Y-axis.The step size for the Vpp values is set by default to 0.1 V . The user can alterit according to their own requirements.

2. The algorithm will run from the start frequency to the stop frequency withthe first provided value of Vpp. After it reaches the stop frequency, it willadd a step (which is 0.1V in our case ) to the previous Vpp value and thensweep again from the start to the stop frequency.This will continue until thevalue of Vpp becomes greater then the predefined stop value of Vpp.

3. The algorithm will stop when the final value of Vpp is greater than the pre-scribes stop value or the frequency ratio is greater then 6.

4. At the end, the program will generate an output file containing the measuredfrequency points and the frequency ratios, respectively, and save it in thepath of the frequency sweeping algorithm.

The frequency sweeping program runs over the whole range of frequenciesand amplitudes. This takes a huge amount of time for a single experiment. Thisis a drawback of this algorithm. We used the frequency sweeping algorithm tocharacterize the locking regions for ρ=2,3,4,5,6. We set the start frequency to 300kHz and the stop frequency is 2000 kHz with a step size of 5 kHz. The Vpp was setto step from 0.1V to 5V with a default step size of 0.1 V . Now we can estimatethe time required for the frequency sweep algorithm to run over the whole rangeof frequencies and amplitudes:

Number of frequency points= 2000kHz−300kHz5kHz +1=341 points

Number of amplitude points= 5V −0.1V0.1V +1=50 points

Total sweeping points=341 × 50=17050 points


Total time= 170501sec/point=17050sec=4.74hours

As the chosen frequency interval step size is 5 kHz, many points inside theinterval will be missed by the algorithm. If we reduce the step size, then therunning time of the program will increase enormously. This will miss lots of pointsinside an interval. If the frequency step is reduced further, the running time willbe significantly larger again. Frequency sweeping is suitable for measuring theoverlap between consecutive tongues over a small range of input frequencies witha small injected amplitude [31].

A.2 Boundary Following

Boundary following is a more efficient approach to measuring the boundaries ofthe Arnold Tongue locking regions [30]. The boundary following algorithm hasbeen designed specifically to characterize the locking regions and the tongues of anILFD. Previous students [30] have designed an effective way to find the boundariesof Arnold Tongues. The fact that each boundary point is close enough to the otherboundary point gives rise to the idea of a local search for boundary points. Bytaking very small steps, boundary points for tongues can be measured as shownin Fig. A.3

Figure A.3: Measurement of tongues in Boundary following algorithm.

The rotation number is constant inside the each tongue, which makes bound-ary following a bit difficult. For example, it is very difficult to decide whichspecific frequency point is the first point of the respective rotation number for theleft boundary. Similarly for the right boundary, which specific frequency point isthe last incidence for the target rotation number. Therefore, an assumed bound-ary concept is used. In this algorithm, the assumed boundary consists of pointswith a rotation number that are a fixed difference of 0.001 from the actual rotation

A.2 Boundary Following 61

number. For example, for the divide-by-2 boundary, the left boundary points areequal to 1.999 and the right boundary frequency points are equal to 2.001.

Before running the algorithm, the following parameters need to be set;

1. Provide the device information such as VISA (Virtual Instrument SoftwareArchitecture) or GPIB address (General Purpose Interface Bus) which arethe interface addresses of the devices connected to the PC.

2. Choose the Start and free-running frequencies.

3. Set the stop and start Vpp values for the input injected signal and a startdivision value.

4. Set an appropriate instruction and function which will set the counter’s mea-surement mode.

5. An output file name is to be provided (which by default is in the date andtime format) which will contain the measurement results from the counter.This file will be stored at the completion of the algorithm in the same direc-tory as the boundary following algorithm.

The algorithm and working of the boundary following program are explainedas follows:

1. When the algorithm is started, it searches for the first left boundary pointfrom the point with the start frequency and the max Vpp (user specified),which should be on the left side of the left boundary.

2. The algorithm finds the point within a fixed difference of 0.08 from the as-sumed boundary by jumping the frequency up and down. It uses three differ-ent step sizes, fo/25, fo/50, fo/100, where fo is the free-running frequencyof the ILFD measured in advance by the user. This is shown schematicallyin Fig. A.4.

3. A half-interval search strategy is used by stepping the input frequency upand down until the boundary point is found. The half search interval is fo

25× 1

2n , where we increment n at every step.

4. If the measured point is within 0.005 of the boundary point or the intervalis less then 30 Hz, then the stop condition is reached.

5. When the algorithm reaches its stop condition, it records the input frequency


point of the boundary point and continues finding the next boundary pointby taking the last input frequency as the start frequency.

6. Once the left boundary has been found, the algorithm starts finding the rightboundary using a half interval search.

7. The algorithm finds the boundary points for the rotation numbers from firsttill the seventh.

Figure A.4: Concept behind finding a boundary point in Boundary following al-gorithm.

The main advantage of the boundary following algorithm is its speed andaccuracy for finding boundary points. For every tongue, it takes only 10 minutes.We ran the boundary following algorithm to characterize the locking regions forρ=2,3,4,5,6,7. We set the start frequency to 250 kHz and the free-running fre-quency is 100 kHz. The amplitude is set to be from 0.1V to 5 V with a defaultstep size of 0.1 V . When the interval is less then 30 Hz, the boundary searchstops. The instruments take half a second to complete each jump. For the ILFDwith direct injection, the first boundary point for divide-by-2 is approximately300kHz. We can estimate the time taken by the boundary following algorithm forone complete experiment to run over whole range of frequencies and amplitudesas follows:

First interval( f025 )=4 kHz)× 1

2n <30Hz→n=8

Number of boundary points on each tongue=100

Number of jumps for first boundary point≈ 300−2504 +8=21

Number of jumps for rest of points≈4(estimated)+8=12

Total number of jumps for one tongue=21+12×99=1209

A.3 Boundary Finding 63

Total time for one tongue=1209× 0.5secjump =604.5sec=10 min

The advantages of the boundary following algorithm are its speed and accu-racy. If the user wants to measure the boundary points of tongues for two verydifferent rotation numbers (e-g,2 or 8), then the speed and accuracy decrease. Theuse of small steps taken by algorithm is not necessary. The boundary following al-gorithm finds the point within range a 0.08 form the assumed boundary, but thenafter the first step of the half interval search, the algorithm will use a larger step(fo/50 = 4kHz). Due to the above mentioned drawbacks in the boundary followingalgorithm, the improved Boundary finding algorithm was developed [31].

A.3 Boundary Finding

In order to overcome the drawbacks of the boundary following algorithm a newLabVIEW algorithm was designed, known as the boundary finding algorithm.Before running the algorithm, the following parameters need to be set:

1. Provide the device information such as VISA (Virtual Instrument SoftwareArchitecture) or GPIB address (General Purpose Interface Bus) which arethe interface addresses of the devices connected to the PC.

2. Choose the DC Offset if required, the Units and the shape of the waveformof the input injected signal.

3. Set the stop, start and the step values for the amplitude Vpp of the inputinjected signal.

4. enter the target rotation numbers in a list, for example, if user wants tocalculate the division ratio for 2,3,4 then these should be typed respectively.

5. Set an appropriate instruction and function which will set the counter’s mea-surement mode.

6. An output file name is to be provided (which by default is in date and timeformat) which will contain the measurement results from the counter. Thisfile will be stored at the completion of the algorithm in the same directoryas the boundary finding algorithm.

The control panel of the boundary finding algorithm is shown in Fig. A.5figure.


Figure A.5: Control panel of boundary finding algorithm.

The algorithm and operation of the boundary finding program are explainedas follows:

1. In the beginning of the boundary finding algorithm, the input injected signalcoming from the signal generator’s output is turned Off by default . Thenthe algorithm calculates the free running frequency of the ILFD under test.

2. The algorithm starts searching for the left boundary points from the fre-quency point fo×D and the stop value of Vpp, where D is the first divisionnumber or ratio ρ inserted by the user in the division list. The differencebetween the searched point and the real boundary point is d×boundarydelta.The default value of boundarydelta is 0.001, but can be altered by the useraccording to the needs.

3. A half interval search method is used by the algorithm to search the boundarypoints. The interval is fo×D−1kHz

2n , where n goes from 0 to n-1. The purposeof the 1kHz offset is to make sure that the first jump is within the rangeof the signal generator. For example, if the start point were in the lockingregion then the algorithm will jump to the left side and the input frequencywould become 0 kHz after the first jump. The half interval search is shownconceptually in Fig. A.6.

4. The first interval in the half interval search method is fo×D-1kHz. Prior totaking the first interval jump, the algorithm determines whether the currentpoint is on the left side or the right side of the boundary. If the point is onthe left side then the algorithm will jump from the current point to the right;otherwise, if it is on the right side, then the algorithm will jump towards the


left side. In other words, the algorithm increments the input frequency bythe first interval. After the first jump is completed, the algorithm will reducethe second interval jump by half. In a similar way, the algorithm keeps onjumping right and left until it finds the exact boundary point.

5. When the assumed boundary point is within a difference ofD× differencedeltafrom the measured boundary point, or the interval becomes less than 1Hz,then the stop condition is reached.

6. The algorithm then goes on finding the other boundary points with the samestart frequency of fo ×D.

7. When the left boundary points are found then the algorithm starts findingthe right boundary points in a similar way.

Figure A.6: The half interval search method concept for the boundary findingalgorithm.

The Boundary Finding Algorithm for the divide regions of the divide-by-2and divide-by-4 regions are shown in Fig. A.7.

The boundary finding algorithm is a more general purpose algorithm unlikethe boundary following algorithm, which can operate on all ILFD’s. Boundaryfinding is more accurate due to the fact that the new boundary point does notdepend on the previously measured boundary points. As compared to the bound-ary following algorithm, it takes 16 min, which makes it a bit slower. We ranthe boundary finding algorithm for the divide-by-2 locking region to calculate thetime. We set the free-running frequency to 200 kHz. In the half interval searchmethod, when the interval is less the 1kHz then each boundary point stops and itis assumed that the instrument takes half second before the next jump;


Figure A.7: Measurement of tongues using the boundary finding algorithm.

First interval(≈400kHz)× 12n <1Hz→n=19

Number of boundary points per tongue=100

Number of jumps for first boundary point=19

Total number of jumps for one tongue=19 ×100=1900

Total time for one tongue=1900× 0.5secjump =950sec=16 min

The Boundary Finding Algorithm has fewer parameters to be set by the useras compared to the Boundary Following Algorithm. The user types in the Divisionratio values for which they want to find the boundary points in the Division listin any order [30]. Flow charts of boundary finding algorithm are shown in FiguresA.8- A.10.


Figure A.8: Flow chart for the Main Process of the Boundary-Finding AlgorithmFlow.


Figure A.9: Flow chart for the left boundary of the Boundary-Finding Algorithm.


Figure A.10: Flow chart for the right boundary of the Boundary-Finding Algo-rithm.

Appendix B

Matlab Post-ProcessingCode

B.1 Frequency Sweeping

%%%plotfigureaxis([0.0e3 3000e3 0 5.0]);hold on;

y=[0.1:0.1:5.00.1:0.1:5.0]’;

% Freq2 = load(’2.000 13.54.04.03.2012.txt’);%% plot(Freq2(:,1),y(:,1),’.-r’);% plot(Freq2(:,2),y(:,2),’.-r’);

Freq2 = load(’devide by 2.txt’)for i=1:50

for j=1:2plot(Freq2(i,j),y(i,j),’-rx’);

endend

70

B.1 Frequency Sweeping 71

Freq3 = load(’devide by 3.txt’);for i=1:29

for j=1:2plot(Freq3(i,j),y(i,j),’.b-’);

endend%% %legend(’red % by 2’,’Blue % by 3’);Freq4 = load(’devide by 4.txt’);for i=1:50

for j=1:2plot(Freq4(i,j),y(i,j),’.-r’);

endend% %Freq5 = load(’devide by 5.txt’);for i=1:50

for j=1:2plot(Freq5(i,j),y(i,j),’.-g’);

endend

Freq6 = load(’devide by 6.txt’);for i=1:50

for j=1:2plot(Freq6(i,j),y(i,j),’.k-’);

endend%% Freq7 = load(’7.000 15.41.25.05.2012.txt’);% for i=1:2% for j=1:20% plot(Freq7(i,j),y(i,j),’.-k’);% end% endgridtitle(’LC CMOS ILFD with direct injection locking regions’);xlabel(’Frequency/Hz’);ylabel(’Amplitude’);%end code

72 Matlab Post-Processing Code

B.2 Boundary Following


y=[2.0:-0.1:0.10.1:0.1:2.0];


Freq2 = load(’16.41_25.05.2012 2.000.txt’);for i=1:2

for j=1:20plot(Freq2(i,j),y(i,j),’.-b’);

endendlegend (’blue % by 2’, ’Black % by 3’,’Red % by 5’,’Blue % by 6’ )


for j=1:20plot(Freq3(i,j),y(i,j),’.-k’);

endend



endendFreq5 = load(’16.41_25.05.2012 5.000.txt’);for i=1:2


endendFreq6 = load(’16.41_25.05.2012 6.000.txt’);

B.3 Boundary Finding 73

for i=1:2for j=1:20

plot(Freq6(i,j),y(i,j),’.-k’);end

endgridtitle(’LC CMOS ILFD with direct injection locking regions’);xlabel(’Frequency/Hz’);ylabel(’Amplitude’);

B.3 Boundary Finding


y=[2.0:-0.1:0.12.0:-0.1:0.1];


Freq2 = load(’02.000 12.34.25.05.2012.txt’);for i=1:2

for j=1:20plot(Freq2(i,j),y(i,j),’-rx’);

endend


for j=1:20plot(Freq3(i,j),y(i,j),’.b’);

74 Matlab Post-Processing Code

endend

%legend(’red % by 2’,’Blue % by 3’);Freq4 = load(’4.000 15.03.25.05.2012.txt’);for i=1:2


endend



endendFreq6 = load(’6.000 15.29.25.05.2012.txt’);for i=1:2


endend



endendgridtitle(’LC CMOS ILFD with direct injection locking regions’);xlabel(’Frequency/Hz’);ylabel(’Amplitude’);

Appendix C

Spice Netlist and MatlabCode

C.1 Spice Netlist

**RLCLsingM5_Capacitor_Gamma0

.GLOBAL 0

.OPTION POST=1 ingold=2 numdgt=10 DVDT=4 LVLTIM=3 RMAX=5e-3

.OPTIONS NOWARN warnlimit=0

.param Freq =300k

.param v1=2.3

.TRAN 10ns 200us START=100us SWEEP Freq 300k 1100k 5k

.print vc=PAR(’(V(1)-V(2))’)

**main circuit*vdd vdd 0 9Vdgpw1 Vdd 0 PWL (0 0 1e-5 9 1meg)Vs vs 0 SIN (0 v1 Freq)Vdc vdc 0 7

R2 vi vdc 9.87e4C2 vs vi 1e-6

75

76 Spice Netlist and Matlab Code

R1 1 3 234L1 3 2 1.2468e-3C1 1 2 7.5e-11

C3 1 0 180E-12R3 1 0 200000

C4 2 0 180E-12R4 2 0 200000

mp1 1 2 vdd vdd PMOSt L=10e-6 W=60e-6mp2 2 1 vdd vdd PMOSt L=10e-6 W=60e-6mn3 1 2 0 0 NMOSt L=10e-6 W=30e-6mn4 2 1 0 0 NMOSt L=10e-6 W=30e-6mn5 1 vi 2 0 NMOSt L=10e-6 W=30e-6C5 vi 1 560e-12

* ----------------------------------------------------------------------*

C.2 Spice Netlist for Symmetric Circuit

*****Symmetric ILFD*******

.GLOBAL 0

.OPTION POST=1 ingold=2 numdgt=10 DVDT=4 LVLTIM=3 RMAX=5e-3

.OPTIONS NOWARN warnlimit=0

.param Freq =350k

.param Vac=0.0

.TRAN 10ns 200us START=100us SWEEP Freq 350k 1500k 10k

.print vc=PAR(’(V(1)-V(2))’)

**main circuit*vdd vdd 0 9Vdgpw1 Vdd 0 PWL (0 0 1e-5 9 1meg)

C.2 Spice Netlist for Symmetric Circuit 77

Vs vs 0 SIN (0 Vac Freq)Vdc vdc 0 7

R2 vi vdc 9.87e4C2 vs vi 1e-6

E6 vs1 0 value=(’(V(Vdd)-V(vi)) ’)

R3 vim 0 9.87e4C3 vs1 vim 1e-6

R1 1 3 234L1 3 2 1.2468e-3C1 1 2 7.5e-11

C4 1 0 110E-12R3 1 0 200000

C5 2 0 110E-12R4 2 0 200000

mp1 1 2 vdd vdd PMOSt L=10e-6 W=60e-6mp2 2 1 vdd vdd PMOSt L=10e-6 W=60e-6mn3 1 2 0 0 NMOSt L=10e-6 W=30e-6mn4 2 1 0 0 NMOSt L=10e-6 W=30e-6mn5 1 vi 2 0 NMOSt L=10e-6 W=30e-6C6 vi 1 560e-12

mn6 1 vim 2 vdd PMOSt L=10e-6 W=60e-6C7 vim 2 560e-12

* ----------------------------------------------------------------------.MODEL NMOSt NMOS LEVEL=1 GAMMA=0 XJ=0

+TOX=1200E-9 PHI=0.6 RS=0 KP=111E-6 VTO=2.0 LAMBDA=0.01

+RD=0 CBD=2.0E-12 CBS=2.0E-12 PB=0.8 CGSO=0.1E-12

+CGDO=0.1E-12 IS=16.64E-12 N=1 NSUB=5E+15

.MODEL PMOSt PMOS LEVEL=1 GAMMA=0 XJ=0

+TOX=1200E-9 PHI=0.6 RS=0 KP=55E-6 VTO=-1.5 LAMBDA=0.04


+RD=0 CBD=4.0E-12 CBS=4.0E-12 PB=0.8 CGSO=0.2E-12

+CGDO=0.2E-12 IS=16.64E-12 N=1 NSUB=5E+15* ----------------------------------------------------------------------

.PROBE

.END

C.3 Matlab Post-Processing Code

%%%%%%%%%%%%%%load spiceclcclear allrange1 = [150 1 10150 1 ];%range1 = [402 1 10402 1 ];for j=1; %Vpp 0.1 0.3 0.5 0.7

for i = 1:115; %FreqInj% Mj,i = dlmread(’foranalysis.lis’,’\t’,range1);

Mj,i= dlmread(’00.lis’,’’,range1)%

range1 = range1+[10015 0 10015 0 ] ; %3015=3157-157+15end

range1 = range1 + [170 0 170 0];endsave(’00.mat’, ’M’);

FreqInj = 350e3:10e3:1500e3; %input frequency############Ts =10e-9;Fs = 1/Ts;for j=1;

for i = 1:115; %#########TInj = 1/FreqInj(i);

a = Mj,i;

spectrumRaw = fft(a(:,1));

C.3 Matlab Post-Processing Code 79

freqArray = 0: (Fs/2)/(ceil(length(spectrumRaw)/2)-1) : Fs/2;

[y1, y2] = max(abs(spectrumRaw(1:1:ceil(length(spectrumRaw)/2))));

f(j,i)=freqArray(y2);Ratio(j,i)=FreqInj(i)/f(j,i)

endend

save(’00.mat’, ’Ratio’);

%%%%%%%%COmbining Ratios%%%%%%%%%

clcclear all

fid=fopen(’ratio.txt’,’wt’)

load 00.matfor i=1:1:115

fprintf(fid,’%d \’,Ratio(i))endfprintf(fid, ’\n’)






fprintf(fid,’%d \’,Ratio(i))end

%%%%%%%Ratio Plot%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%


%%%% PLOT RATIO %%%%%%%%%%%%%%%%%%%%%%%%%%%%Ratio=load(’ratio.txt’)FreqInj1 = 350e3:10e3:1500e3;%input frequencyy1= 0.0:0.5:2.5;refineratio1=zeros(06,115);for j=1:6;

for i=1:115;if abs(Ratio(j,i)-2)<= 0.00001;

refineratio1(j,i)=2;else

if abs(Ratio(j,i)-3)<= 0.000001;refineratio1(j,i)=3;

end

endend

endfiguregridaxis([350e3 1100e3 0 2.5])title(’Capacitor connected Single M5,including RLCL, 7V DC bias, ’,’FontSize’,11)xlabel(’Frequency’,’FontSize’,13)ylabel(’Amplitude’,’FontSize’,13)hold on

for j =1:6;for i = 1:115;

if refineratio1(j,i)==2;plot(FreqInj1(i),y1(j),’-ko’)

elseif refineratio1(j,i)==3;

plot(FreqInj1(i),y1(j),’-ro’)

end

endend

end

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