Analog Design 1

8/7/2019 Analog Design 1

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Design of CMOS low dropoutDesign of CMOS low dropout

voltage regulatorvoltage regulator

Project guide :

Mrs Varsha Prasad

NMIT

By :

Savitha M M

1NT09LVS13

NMIT1

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ContentsContents

y Introduction

y Literature survey

y

Selection of tools for the projecty Project work execution stages

y Design of LDO voltage regulator

y

Questions

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IntroductionIntroduction

y

Design of a 3-5V 50mA CMOS low Drop-out (LDO) linearregulator with a single compensation capacitor.

yThe circuit realization to be developed with respect to the

loop-gain response, the transient response, the output

noise, the output accuracy, as well as the standby power

consumption.

yThe proposed LDO regulator to be implemented in the

0.6um CMOS process. Maximum output load current upto

50mA and the regulated output voltage should be 2.8V

should be supported.yThe regulator should provide a full load transient response

less than 5mV overshoots and undershoots.

yPower supply reject rate better than -65dB

yOutput noise of 0.02 uV/sqrt Hz at 100 kHz 3NMIT


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Literature surveyLiterature survey

y Cmos low dropout voltage regulator-Vincent lixiang bu

y Design of analog CMOS integrated

circuits-B.Razaviy CMOS analog circuit design-Phillip.E.Allen

and Douglas R.Holberg

y

Handbook of operational amplifierapplications-Ken Martin

y Understanding terms and definitions of

LDO voltage regulators-Bang S Lee of TI4NMIT


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Selection of tools for the projectSelection of tools for the project

Evaluated H-Spice and T-Spice.

Selected T-Spice v 13.0 because of its more

user friendly waveform viewer

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Project work execution stagesProject work execution stages

y Design of a 2 stage opamp

y Simulation of unity gain buffer : input

common mode range

y Simulation of open loop gain

y Simulation of transfer function

y Simulation of phase margin

y Simulation of amplifier compensation

y Simulation of power dissipation

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execution stages contdexecution stages contd

y Simulation of CMRR

y Simulation of slew rate

y

Simulation of o/p resistance

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Design of 2 stage opampDesign of 2 stage opamp

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Design of 2 stage opamp contd..Design of 2 stage opamp contd..

Ibias 30A

S1=S2 3

S3=S4 10

S5=S8 7.5

S6 61

S7 23

Rl 1mega ohm

Vin 2.5V

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Simulation of unity gain buffer : inputSimulation of unity gain buffer : input

common mode rangecommon mode range

The input common-mode range of this op amp extends from

-2.20V to 2.00V

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Unity gain buffer AC waveformUnity gain buffer AC waveform

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Time (ms)

-1.0

-0.5

0.0

0.5

1.0

Voltage(V)

v(vout)

v(q6)

y1= y2= dy=999.52m -1.00 -2.00

unity ainac

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Simulation of open loop gainSimulation of open loop gain

The input offset voltage for this op amp = 0.26mV

The open-loop gain of this op amp = 2179The open-loop gain of this op amp in db= 67db

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Open loop gain waveformOpen loop gain waveform

-1.0 -0.5 0.0 0.5 1.0

in (mV)

-0.5

0.0

0.5

Voltage(V)

(

out)

205.12m

(q6)

382.04u

1 2 d382.04u 211.31u -170.74u y1 y2 dy199.67m -172.37m -372.05m

open_loop

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Transfer function waveformTransfer function waveform

10 100 1k 10k 100k 1M 10M 100M

Freque cy (Hz)

-

0

-10

0

10

20

30

40

50

60

70

oltageMag

itude(dB)

db(

out )

y1= y2= dy=67.31 8.04 - 9.27

trans er

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Simulation of phase marginSimulation of phase margin

10 100 1k 10k 100k 1

10

100

eque cy(Hz)

-200

-150

-100

-50

0

50

100

150

200

olagePhase(d

eg)

p(

ou

)

-177 29

x1= x = dx=1 92k 36 90 36 89 y1= y2= dy=74 69 -175 44 -250 13

phase

Phase margin =180-175 = 5deg

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Simulation of amplifierSimulation of amplifier

compensationcompensation

20 deg phase = Cc is 0.3pfarad

60 deg phase = Cc is 2.8pfarad

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compensationcompensation

10 100 1k 10k 100k 1M 10M 100M

Frequency (Hz)

-200

-150

-100

-50

0

50

100

150

200

Voltage

Phase

(deg)

vp(vout)

-120.62

x1= x2= dx=1.92k 5.25M 5.25M y1= y2= dy=74.60 -119.04 -193.64

amp6a

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compensation contdcompensation contd

m ( s)

-

!

"

t

(m

)

#

(# $ %

t)#

(&

'

)

amp6b

Amplifier compensation improves phase margin and to

achieve stable closed loopperformance 20NMIT


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Simulation of power dissipationSimulation of power dissipation

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1 .5 2.0 2.5

( )

-250

-200

-150

-100

-50

0

50

100

150

200

250

Cu

e

t(uA)

(

()

ss)(

()

dd)

y1 y2 dy187.39u -187.49u -374.87u

power8

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Simulation of CMRRSimulation of CMRR

Common mode gain

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Common mode gain waveformCommon mode gain waveform

10 100 1k 10k 100k

F ( z)

-0

0

-1

2

-1

0

-3

2

-3

0

-15

-10

-5

0

V

l

M

i

(

)

4

5 6

( 4 7 8 9 )

y1= y2= dy=- 19 - 9.68 - 2.49

cmrr1

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Differential mode gain waveformDifferential mode gain waveform

10 100 1k 10k 100k

Fr y( z)

0

10

@

0

A

0

40

50

60

B

0

t

tde(dB)

C

db(C

D

E

t)

y1= y2= dy=67.61 35.01 -32.60

cmrr1a

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CMRR contdCMRR contd

CMRR

=

Differential mode gain common mode gain

At 10hz = 74.8db

At 100khz = 74.69db

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Simulation of slew rateSimulation of slew rate

Positive slew rate = 11.18v/sNegative slew rate = 9.76v/s

With no load

Positive slew rate = 11.12v/s

Positive slew rate = 10.53v/s

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Slew rate waveformSlew rate waveform

0.0 0.5 1.0 1.5 2.0

Time (us)

-1.0

-0.5

0.0

0.5

1.0

Voltage

(V)

v(vout)

slewrate3

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Simulation of o/p resistanceSimulation of o/p resistance

0.0 0.5 1.0 1.5 2.0

Time ( s)

- F .1

- F .0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

V

e(mV)

v(vG

H I )

v(P 7)

y1 y2 dy909.87u 295.06u -614.81u

opres4

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Design of LDO voltage regulatorDesign of LDO voltage regulator

This work is in progress

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LDO voltage regulator contd..LDO voltage regulator contd..

This work is in progress

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LDO voltage regulator contdLDO voltage regulator contd

Performance parameters:

y Dropout voltage

y Transient response

y Power supply rejection

y Line regulation

y Load regulation

y Output noise voltage

y AccuracyThis work is in progress

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Analog Design 1

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