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  • Diplomarbeit

    Design of Monolithic IntegratedLumped Transformers

    in Silicon-based Technologiesup to 20 GHz

    Ausgefuhrt zum Zwecke der Erlangung des akademischen Grades eines

    Diplom-Ingenieurs unter Leitung von

    Werner Simburger und Arpad L. Scholtz

    E389

    Institut fur Nachrichtentechnik und Hochfrequenztechnik

    eingereicht an der Technischen Universitat Wien

    Fakultat fur Elektrotechnik

    von

    Daniel Kehrer

    9526730Hacklweg 9, 4081 Hartkirchen

    Wien, im Dezember 2000

  • Contents

    1 Introduction 1

    2 Design of Integrated Transformers 52.1 Silicon-based Technology and Metallization . . . . . . . . . . . . . 52.2 Transformer Construction . . . . . . . . . . . . . . . . . . . . . . 7

    2.2.1 Basic Electrical Characteristics . . . . . . . . . . . . . . . 72.2.2 Planar Winding Scheme . . . . . . . . . . . . . . . . . . . 92.2.3 Metallization Structure . . . . . . . . . . . . . . . . . . . . 16

    2.3 Transformer Model . . . . . . . . . . . . . . . . . . . . . . . . . . 19

    3 Parameter Extraction 253.1 Inductance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 253.2 Skineect and Current Crowding . . . . . . . . . . . . . . . . . . 31

    3.2.1 Equivalent Series Resistance . . . . . . . . . . . . . . . . . 323.3 Substrate Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

    3.3.1 Conductor on Substrat . . . . . . . . . . . . . . . . . . . . 343.3.2 Conductor Suspended in Dielectric . . . . . . . . . . . . . 37

    3.4 Capacity Extraction . . . . . . . . . . . . . . . . . . . . . . . . . 413.5 Test-Structures for Measurement and Characterization . . . . . . 43

    4 Design Examples 464.1 Monolithic Transformer BL62S005 . . . . . . . . . . . . . . . . . 46

    4.1.1 Measurement and Simulation Results up to 5GHZ . . . . . 484.2 Monolithic Transformer N3M2 . . . . . . . . . . . . . . . . . . . . 55

    4.2.1 Measurement and Simulation Results up to 20GHZ . . . . 56

    Conclusion 62

    Appendix 63

    FastTrafo Manual 63

    Bibliography 80

    i

  • Abstract

    Monolithic integrated lumped planar transformers have several advantageswhen using them in power ampliers, mixers, oscillators and other radio frequencycircuits. But, up to now there was no way to get an accurate prediction and modelof the electrical characteristic of on-chip transformers.

    For the rst time this work presents the modeling and model verication of in-tegrated lumped planar transformers in silicon which have excellent performancecharacteristics in the 1-20 GHz frequency range. A new method for characteriza-tion of monolithic lumped planar transformers is proposed in this work.

    The metallization of a semiconductor process denes the possibilities for trans-former design. Planar and layer construction of common monolithic lumped trans-formers and its optimization techniques are considered in detail. A lumped low-order equivalent circuit is presented which results from the transformer geome-tries.

    The aim of precise and fast transient analysis of RF circuits using monolithictransformers was reached with the compact lumped low order model which con-sists of 24 elements. The model gives accurate prediction of the electrical behaviorand ensures fast transient analysis. An excellent prediction accuracy is achieved.

    Background details about extraction of all elements used in the equivalent cir-cuit are given. The inductance of transformers built up from straight conductorsis derived. Skin eect and current crowding cause losses in the conductors. Theconductive substrate causes additional losses. Some thesis about the parasiticcapacitive coupling between the windings and the substrate are presented.

    The parameter extraction for the equivalent circuit is based on a tool devel-oped by the author which uses a new expression for the substrate loss and twonite element method cores.

    The modeling and parameter extraction of monolithic transformers has beenveried by multiple transformers. In this work the measurement of two types oftransformers is presented as example. The rst type oers a high coupling perfor-mance up to 4 GHz. The second type of transformer oers a high self resonancefrequency of 20 GHz. Measurement and simulation of the two transformers showexcellent agreement.

  • List of Abbreviations

    Al AluminumCAD Computer Aided Design Depth of Current Penetration in [m]DECT Digital Enhanced Cordless TelecommunicationDC Direct CurrentDUT Device Under Test"r Relative Permittivity in [1]FEM Finite Element MethodfOp Operation Frequency in [Hz]GaAs Gallium-ArsenideGMD Geometric Mean Distance in [m]IC Integrated Circuitk Coupling Coecient in [1]L Inductance in [H]g Guided Wavelength in [m]n Turn Ratio in [1]N Number of Turns in [1]M Mutual Inductance in [H] Permeability in [Vs/Am]Q Quality Factor in [1]RF Radio Frequency Specic Resistivity in [m] Conductivity in [S/m]Si SiliconSi3N4 SiliconnitrideSiO2 SilicondioxideVLSI Very Large Scale Integration

  • Chapter 1

    Introduction

    Transformers have been used in radio frequency circuits since the early days oftelegraphy. Normally transformers are relatively large and expensive componentsin a circuit or system. But there are several outstanding advantages using trans-formers in circuit design:

    DC isolation between primary and secondary winding

    BALUN function

    Impedance transformation and matching

    No power consumption

    The requirements of nowadays telecommunication systems needs a high degreeof monolithic integration. Today it is possible to integrate lumped planar trans-formers in Si- and GaAs-based IC technologies which have excellent performancecharacteristics in the 1-20 GHz frequency range. The outer dimensions are in therange of about 500m down to 60m diameter depending on the frequency ofoperation and the IC technology.

    Monolithic integrated lumped planar transformers are introduced by [Rabjohn 89].A review of the electrical performance of passive planar transformers in IC tech-nology was presented by [Long 00]. Ampliers and mixers using monolithic trans-formers are presented in [McRory 99], [Long 99]. A monolithic 2 GHz Meissner-type voltage controlled oscilallator is realised in [Wohlmuth 99]. The transformercoupled push-pull type amplier was invented in the early days of tubes. Re-cent designs in monolithic integration of this concept shows a high performance[Simburger 99],[Simburger 00],[Heinz 00].

    Figure 1.1(a) shows the schematic diagram of a monolithic transformer coupledRF power Amplier for 2 GHZ in SI-bipolar [Simburger 00].The circuit consistsof a transformer X1 as input-balun, a driver stage T1 and T2, a transformer

    1

  • CHAPTER 1. INTRODUCTION 2

    X2 as interstage matching network and a power output stage T3 and T4. Thetransformers X1 and X2 are of the same kind.

    Figure 1.1b shows the chip micrograph of the power amplier. The key elementsof this circuit are two high performance on-chip transformers of the same kind,which work as input balun and for interstage matching.

    A detailed micrograph of the on-chip transformer is shown in Figure 1.2. A moredetailed description of this transformer is given in Sect. 4.1.

    SubstrateVEE

    RFIN+

    VCCD

    VEED E

    KPBKDP

    PBDB

    X1N=6:2

    X2N=6:2

    R1R2

    CIN CISD1

    D2

    T1

    T2

    T3

    T4

    RFIN-

    RFOUT-

    RFOUT+

    Figure 1.1: (a) Schematic diagram of a power amplier using integratedlumped planar transformers (b) Micrograph of the 2 GHz RF power amplier[Simburger 00]

  • CHAPTER 1. INTRODUCTION 3

    Figure 1.2: Micrograph of an on-chip transformer. Size: 205m diameter

    The operation of a lumped transformer is based upon the mutual inductancebetween two or more conductors or windings.

    In contrast to an ideal transformer, monolithic integrated transformers have par-asitic eects and imperfect coupling between the windings which results in acoupling coecient less than one. However, monolithic integrated lumped trans-formers have not the characteristics of an ideal component. To create a successfuldesign including a integrated transformer it is not enough to know the trans-formers turn ratio. A sucient specication includes at least the main electricalparameters, which are inductance and coupling coecients of multiple coupledinductors of the windings, ohmic loss in the conductor material of the windingsdue to skin eect and current crowding, parasitic capacitive coupling between thewindings and parasitic capacitive coupling into the substrate and nally substrateloss.

    The limitations of monolithic integrated transformers on silicon must be clearlyunderstood by the circuit designer in order to get an overall successful circuitdesign. Up to now there was no way to get an accurate prediction and models of

  • CHAPTER 1. INTRODUCTION 4

    the electrical characteristic of the on-chip transformers.

    For the rst time this work presents the modeling and model verication of inte-grated lumped planar transformers in silicon. A lumped low order model whichconsists of 24 elements is presented. The model gives accurate prediction of theelectrical behavior and ensures fast transient analysis, because of the low com-plexity. This work presents a method of parameter extraction for the equivalentcircuit. The method is based on a tool developed by the author. The tool, calledFastTrafo, uses a new expression for the substrate loss and two nite elementmethod (FEM) cores available from Massachusetts Institute of Technology calledFastHenry [MIT 96] and FastCap [MIT 92].

    FastTrafo consists of three program modules. The rst module computes theself inductances and mutual inductances of the primary and secondary windingand the ohmic loss due to the resistivity of the conductor material, skin eectand current crowding. The substrate loss is calculated by a formula which followsfrom characteristic impedances [Hilberg 81] and simulations using the FEM-solverMaxwell-Field by [Ansoft 93]. The second module computes the parasitic capaci-tance between primary winding, secondary winding and the substrate. The thirdprogram module creates a SPICE netlist of the equivalent model which is thencompared to measurement data of the transformer (if available).

    Chapter 2 presents the design and construction of monolithic planar transformers.The metallization of a semiconductor process denes the possibilities for trans-former design. Design rules and optimization techniques are presented. A lumpedlow-order equivalent circuit results from the transformer geometries. Chapter 3derives basic relations of an ideal transformer. Background details about extrac-tion of all elements used in the equivalent-circuit are given. Chapter 4 shows sev-eral design examples. Simulation results are compared to measurement results.An excellent prediction accuracy is achieved.

  • Chapter 2

    Design of IntegratedTransformers

    The design of monolithic lumped planar transformers is a demanding task. Firstthe metallization of a semiconductor process, which denes the possibilities fortransformer design, is considered. Planar and layer construction of common mono-lithic lumped transformers and its optimization techniques are presented in Sect. 2.2.A lumped low-order equivalent circuit, resulting from the transformer geometries,is derived in Sect. 2.3.

    2.1 Silicon-based Technology and Metallization

    The Metallization of a wafer is known as the wiring-layers, which are placed on thesurface of the wafer. They are used to get a connection between the componentsof the circuit. The connection should have less resistance. In the case of a mono-lithic transformer, the winding construction consists of the metallization-layers.The metallization denes restrictions and possibilities. It is the working-area formonolithic transformer design.

    The most common material for metal-layers is Aluminum (Al). It is a cheap mate-rial, inexpensive in production and has excellent characteristics against diusionin silicon.

    Nowadays some semiconductor-manufacturer are using copper as material for themetallization. Nearly the half resistance of aluminum stands in the opposite ofa complex and costly semiconductor-process. INFINEON decided to use a Al-metallization for the standard process B6HFC.

    The metallization forms the design environment for monolithic transformers. Thelayer construction xes the design rules for transformer design. It sets the restric-tions and aects the transformers characteristics. In order to get a good trans-former design it is necessary to take advantage of all available possibilities of themetallization.

    5

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 6

    A simplied cross-section of the B6HFC-metallization is shown in Fig. 2.1. TheB6HFC-Process consists of three metal layers, Alu1, Alu2 and Alu3. The conduc-tor material is aluminum and has a conductivity of = 33 S/m. Every metallayer has a dierent height and a dierent minimal spacing between two con-ductors. The minimal spacing increases with each metal-layer and is a physicalresult of the semiconductor process. The metal layers are embedded in Silicon-dioxide SiO2, which has a relative permittivity of "r = 3:9. The passivation isa airproof protection coat against dust, dirt and oxidation. It consists of Sili-connitride Si3N4 and has an "r = 7:5 . The substrate is a p

    -doted Silicon andis a mixture of conductor and dielectric. The thickness of the substrate-layer isabout 200m. The high conductivity of = 12:5 S/m is signicant for the sub-strate loss, discussed in Section 3.3. The relative permittivity of the substrate is"r = 11:9.

    >2.80.55

    6.45

    ~20

    0

    1.6

    3.1

    5.05

    10.

    551.

    4>0.9

    >0.6

    Passivation Si Nr=7.5

    r=3.9

    r=11.9=12.5 S/m (8 cm)

    Dielectric SiO

    Substrate Si-p

    =33mS

    Alu3

    Alu2

    Alu1

    All dimensions in [m]

    2

    3 4

    Figure 2.1: Schematic cross section of the B6HFC-metallization.

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 7

    2.2 Transformer Construction

    The goal of a design procedure for monolithic integrated transformers is to attainthe desired frequency range with the lowest possible losses. Because of the com-plexities in modeling and analysis of these components, any change of the designshould involve a simulation of the structure.

    2.2.1 Basic Electrical Characteristics

    Now some basic relations about transformers are explained. This relations will beneeded to understand the design of monolithic integrated lumped planar trans-formers. Fig. 2.2 shows the schematic symbol of an ideal transformer with twocoupled windings. In this work all variables shown in Fig. 2.2 are related to thisgure if not noted dierently.

    LP

    IP IS

    LS

    N1 N2

    M

    UP US

    Figure 2.2: Schematic symbol of an ideal transformer with two windings.

    A monolithic integrated planar transformer comprises two windings. Each wind-ing consists of an integer number of turns N1 1; N2 1 where N1 is thenumber of primary turns and N2 is the number of secondary turns. The twowindings are arranged in a single plane with conductors crossing one another.

    The turn ratio n of a transformer is one of the main electrical parameters ofinterest and is dened as

    n =N1

    N2(2.1)

    In the case of an ideal transformer, the turn ratio n is also equivalent to

    n =UP

    US=IS

    IP(2.2)

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 8

    where UP is the voltage between the primary ports, US is the voltage betweenthe secondary ports. IP and IS is the current-flow into the related ports.

    Each winding, the primary and the secondary, has a self-inductance LP and LSand they are inductively coupled denoted by the mutual-inductance M .

    The strength of the magnetic coupling between the primary and secondary wind-ing is indicated by the coupling coecient k (k-factor) as

    k =M

    pLP LS

    (2.3)

    A typical range for the k-factor achieved in monolithic transformer designs is0:6 k 0:95.

    A lumped transformer means that the maximum outer dimensions are smallerthan the guided wavelengthg at the operation frequency fop. This is expressedin the following unequation:

    dO g(fop) (2.4)

    where dO is the maximum outer dimension of the transformer.

    Transformer Tuning

    In many applications (i.e Input matching and interstage matching of a powerampliers) a high current transfer ratio of the on-chip transformer is desired. Incontrast to an ideal transformer the current transfer ratio of a lossy transformeris not equal to the value of the turn ratio. In this subsection a basic relation ofthe current transfer ratio of a lossy tuned transformer is derived.

    Fig. 2.3 shows a secondary short-circuit transformer. It consists of a primary wind-ing LP and a secondary winding LS. LP and LS are mutually coupled, denotedby the k-factor. In most cases the input impedance of the driver stage and theoutput stage is very low. Therefore, the secondary winding of the transformer inFig. 2.3 is short-circuit, but without loss of generality. The ohmic loss of the pri-mary winding LP , ohmic loss the secondary winding LS and the input impedanceof the transistors (assumed real valued) are considered by the admittance G. Thetransformer is connected as a parallel resonant device using the capacitor C.

    Then the resonant frequency !res of the tuned transformer can be derived as

    !res =1q

    (1 k2) C LP(2.5)

    The quality factor Q of the resonant circuit is

    Q =!res C

    G=

    1

    G

    sC

    (1 k2) LP(2.6)

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 9

    G

    LP

    IP IP IS

    LS

    k

    Transformer

    Inpu

    t

    Out

    put

    C

    Figure 2.3: Tuned ideal transformer equivalent circuit [Simburger 99].

    The inner current transfer ratio of the ideal transformer is

    ISI 0P

    = k

    sLPLS

    (2.7)

    Now the total current transfer ratio IS=IP of the parallel resonant transformercan be expressed by ISIP

    = k Q sLPLS

    (2.8)

    This relation shows that in contrast to the untuned transformer, the total currenttransfer ratio can be increased by a quality factor of Q > 1.

    2.2.2 Planar Winding Scheme

    Monolithic transformers have been presented in various geometric designs andmany dierent kinds have been realized. Some planar winding schemes for mono-lithic transformers are discussed in this section. The schemes are presented insimple example transformers.

    Fig. 2.4(a) shows the winding scheme of a monolithic transformer with a turnratio n = 2 : 2. Fig. 2.4(b) illustrates the physical layout of the circular-shapedplanar transformer. The primary ports are located on the left side, the secondaryports are located on the right side. The two windings are separated from eachother. The secondary winding starts at the radius rIS, which is equal to the innerradius rI of the transformer, and ends at the radius rOS. The primary windingstarts at the radius rIP and ends at the radius rOP which is equal to the outerradius rO of the transformer. The winding scheme includes two cross-overs, onein the primary winding between the turns P1 and P2 and another one in thesecondary winding between the turns S1 and S2. The transformer is completelysymmetrical about a line. This design can be improved by several ways.

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 10

    P+

    P-

    S+S-

    P+P-

    S+S-

    (a) (b)

    P1

    S1P2

    S2

    2r,2r I

    IS

    2rIP

    2r,2r

    OO

    P

    2rO

    S

    Figure 2.4: Circular-shaped monolithic lumped planar transformer with a turnratio n = 2 : 2, (a)Winding Scheme (b) Physical layout

    Adjacent Conductors

    To maximize magnetic coupling between windings, adjacent conductors shouldbelong to dierent windings. The mutual magnetic coupling between adjacentconductors that belong to the same winding increases self-inductance but notmutual inductance. It is clear from (2.3) that the k-factor is signicantly lowered.

    The circular-shaped transformer in Fig. 2.4 has not been optimized. Two primaryturns are followed by two secondary turns which lowers the k-factor as mentionedbefore. In this case a interleaved winding scheme would help to increase magneticcoupling.

    (a) (b)

    S+S-

    P+P-

    P1

    P2S1

    S2 S+S-

    P+

    P-

    W

    S

    2a,2a I

    IS

    2aO

    S2a

    ,2a

    OO

    P

    2aIP

    Figure 2.5: Square-shaped monolithic transformer with a turn ratio n = 2 : 2 andan interleaved scheme: (a)Winding Scheme (b) Physical layout

    The square-shaped transformer in Fig. 2.5 has the same number of windings onprimary and secondary side (n = 2 : 2) as the transformer shown in Fig. 2.4.The major dierence between these two designs is the winding scheme. The

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 11

    transformer is constructed with a interleaved winding scheme, which means pri-mary turns are followed by secondary turns. This increases magnetic couplingbetween the windings and the coupling coecient k. The winding scheme shownin Fig. 2.5(a) consists of two turns on each side and without loss of generality thescheme can be expanded with a number of more than two turns.

    Interlaced Winding Scheme

    To realize other values of the turn ratio than 1 dierent numbers of primaryand secondary turns are used. This implements that some adjacent conductorsbelong to the same winding which results in a lower k-factor. A solution for thisproblem is to use a interlaced winding-scheme. One winding (e.g. the secondary)is sectioned into a number of individual turns rather than one continuous winding.

    P+

    P-PCT

    S1S1S1

    S2S2

    S2S+SCTS-

    P1P6P2P5P3P4

    Figure 2.6: Interlaced winding scheme of a planar transformer with a turn ratioof n = 6 : 2.

    Fig. 2.6 illustrates a interlaced winding scheme with a turn ratio of n = 6 : 2.The six primary turns (P1-P6) are connected in series. On the secondary side thethree outer and the three inner turns are connected in parallel to form two groups(S1 and S2). The groups are connected in series to form two secondary turns.Six primary turns and two secondary turns result in a turn ratio of n = 6 : 2.Centertaps on the primary side PCT and on the secondary side SCT are available.

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 12

    Ports Position

    In many applications of monolithic integrated transformers it is desired to connectthe primary ports at the left side and the secondary ports on the right side.The winding schemes presented before (Fig. 2.4, Fig. 2.5, Fig. 2.6) enable thisdemands. The groups of conductors are interconnected in a way which brings allterminals to the outside edge of the transformer layout.

    In applications it is commonly required to use such transformers in balancedcircuits, for which at least at one of the transformer winding a center tap exists.The midpoint (center tap) between the ports on each winding, can be locatedprecisely at the inside edge. Because of the symmetric design, the center tapis optimally positioned, and the two halves of the winding are inductively andcapacitively balanced for frequencies in a very broad range. All winding schemespresented before provides this symmetric design.

    Square- and Circular-Shaped Transformers

    Planar transformers can be constructed in square-shape or in circular shape.These two shapes of the planar transformer geometry are illustrated in Fig. 2.4(b)and Fig. 2.5(b). The main dierence between these two shapes is the needed chiparea.

    Now a single circular-loop and square-loop shown in Fig. 2.7 is used as exampleto derive the relation between these two shapes. We want to assume the sameperimeter, lRect and lCircle, for each shape which is expressed in the followingequation.

    r2a

    I I

    (b)(a)Figure 2.7: Single current-loop: (a) circular-shaped loop (b) square-shaped loop.

    lRect = 8a = 2r = lCircle

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 13

    a =

    4r (2.9)

    where a is the half side length of the square-shaped loop and r is the radius ofthe circular-shaped loop. In the case of a transformer all length are scaled withthe factor =4. The needed chip area of a square shaped transformer follows from(2.9) to

    ARect = 4 a2O = 4

    r2O2

    16= r2O

    4= ACircle

    4(2.10)

    where aO is the half side length of a square-shaped transformer (Fig. 2.5) and rOis the outer radius of a circular-shaped transformer (Fig. 2.4). (2.10) shows thatthe needed chip area for a square shape is only =4 of the area of a circular shapewith the assumption that lRect = lCircle.

    W

    T

    (a) (b)Figure 2.8: Conductor-Cross-Section: (a) Rectangular cross-section (b) Circularcross-section.

    Now a basic relation of the self-inductance for a plane circular- and a square-loopis derived. The inductance-formulas [Grover 46] of any plane closed gure withperimeter l and radius of the conductors cross section have the general form

    L =o

    2l

    "ln

    2l

    ! +

    l

    #(2.11)

    The constant is characteristic for the gure and its shape. The value of forsquare- and circular-shape was noted by [Grover 46] and is valid for a innitethin wire. For a nite conductor cross section have to be corrected with thegeometric mean distance GMD of the conductors cross section (Sect. 3.1). In thecase of a rectangular conductor cross section the constant for a circular- andsquare-shaped loop can be noted as

    Rect = 2:854 + ln 0:2235 = 1:356;

    Circle = 2:452 + ln 0:2235 = 0:954 (2.12)

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 14

    Equation (2.11) is valid for conductors with negligible conductor height T whichis not the case at monolithic transformers. So instead of the general inductance-formula for plane shapes a approximation based on (2.11) is used for the induc-tance calculation. The approximation was noted by [Wohlmuth 00].

    LRect =o2

    8aln

    2

    W + T

    + ln (8a) 1:356 +

    W + T

    8a

    (2.13)

    LCircle =o2

    2rln

    2

    W + T

    + ln (2r) 0:954 +

    W + T

    2r

    (2.14)

    where T is the conductor height and W the conductor width, a is the half sidelength of the square-shaped loop and r is the radius of circular-shaped loop. In thecase that W +T r and W +T a the last term in brackets is negligible. Withthis simplication and the assumption lRect = lCircle the ratio of the inductancescan be written as

    LRect=LCircle =ln

    2lW+T

    1:356

    ln

    2lW+T

    0:954

    (2.15)

    For a square and a circular shaped loop with the same length (2.15) shows a lowerinductance for the square shape in a range of 5-15% for typical geometries. Toget the same inductance of both shapes the rectangular loop must have a greaterlength.

    In Fig. 2.9 a comparison of the needed chip area between circular-shaped andsquare-shaped loop is illustrated. The data plotted in Fig. 2.9 is valid for a singlecurrent loop in the two mentioned shapes and is a result of the numerical solutionof (2.13) and (2.14) under the condition LRect = LCircle. A circular loop withradius r, track width W and conductor height T needs a chip area of ACircleto reach a certain inductance. A square loop with the same track width andconductor height needs a chip area of ARect to achieve the same inductance asthe circular loop.

    In the case of a transformer with a number of turns it is not possible to makea simple comparison. The simulation of the transformer design in both shapesis the best way to nd the optimum. In fact the chip-area consumption of thesquare-shaped transformer in opposite to the circular shaped transformer is notthat small as mentioned in (2.10). The ratio of the needed chip-area is alwayssmaller than =4 for reaching the same inductance. In some cases the requiredchip area of a circular-shaped transformer can be lower than a square shapedtransformer.

    Another disadvantage of the square shaped transformer are unsteady places inthe geometries. The corners of the square represent a narrow place for the current.Additional losses are the consequences. In some cases a rectangular shape can beplaced better on the chip than a circular shape.

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 15

    1 2 3 4 5 60.94

    0.96

    0.98

    1

    1.02

    1.04

    1.06

    1.08

    A rect

    /Aci

    rcle

    r/(W+T)

    Single loop, LRect=LCircle

    Figure 2.9: Comparison of needed chip area between circular- and square-loopwith the same inductance.

    Spacing between Conductors

    The following steps are explained with the help of the simple example transformershown in Fig. 2.5. To keep it simple, no center taps and only two turns for eachwinding are used. The top view shows the geometry parameters W which is theconductor-width of each turn, lateral spacing S between the turns, the inner andouter side length 2 aI and 2 aO. The primary ports are located on the left side,the secondary ports on the right side.

    Narrowly spaced conductors improve the magnetic and electric coupling betweenwindings. The plot in Fig. 2.10 illustrates the k-factor of the example transformeras a function of the conductor-width W and dierent lateral spacings S. It showsthat the transformers k-factor improves when the spacing between the windingdecreases, and therefore the smallest practical spacing should be used in thedesign. However, the high parasitic capacity between the windings must also beconsidered. The k-factor tends to a limiting value for a given spacing S. The datashown in Fig. 2.10 indicates that a design with a ratio of W=S 2 is optimum.

    The simulation was done with the transformer CAD-tool FastTrafo. FastTrafo wasdeveloped by the author and is partly based on two FEM-cores available fromMassachusetts Institute of Technology called FastHenry [MIT 96] and FastCap[MIT 92].

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 16

    3 4 5 6 7 8 9 100.45

    0.5

    0.55

    0.6

    0.65

    0.7

    Coup

    ling

    Coef

    ficie

    nt k

    PS

    Trackwidth W in m

    2:2 Transformer, 4 turns, r i=25m, Alu3, B6HFC (Fig. 2.1)

    S=3m S=5m S=8m S=10m

    Figure 2.10: k-factor versus trackwidth of a n = 2 : 2 transformer (Fig. 2.5).

    2.2.3 Metallization Structure

    A closer look insight the transformers geometric design is illustrated in Fig. 2.11.It shows the detailed layer construction of monolithic transformers, with primary-and secondary winding, dierent metal layers, cross-overs and VIAs. The trans-formers characteristic depends also on the layer construction and process tech-nology. Now a view possibilities to optimize the usage of the metallization for amonolithic transformer are discussed.

    Multiple Layers

    To reduce the ohmic loss it is possible to use multiple layers of metal to constructeach winding. The dierent layers are connected in parallel with a number ofsmall pins called "VIA". The cross section in Fig. 2.11 shows metal layer 3 inparallel with metal layer 2 for the primary winding and metal layer 1-3 in parallelfor the secondary winding. Every half turn of the turns they are connected inparallel with VIAs. This results in reduced ohmic losses in the conductors and alower insertion loss of the transformer. These losses modify the impedances seenat each port when the transformer is impedance matched to the source and load,and also contribute noise in the nal circuit [Long 00]. The disadvantage of thispossibility are the increasing parasitic capacities between the windings and thesubstrate.

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 17

    p-Substrate

    Metal Layer 3Metal Layer 2Metal Layer 1

    Primary WindingSecondary Winding

    VIA

    Oxide

    Figure 2.11: Cross section of an integrated transformer.

    It was shown previously (Fig. 2.10) that the transformers k-factor can be im-proved with varying the trackwidthW and spacingS. Another possibility to in-crease the k-factor is the usage of multiple layers. In Fig. 2.12 the k-factor of theexample transformer shown in Fig. 2.5 is illustrated. The conductor-width W andthe used metal layers are choosen to get the same cross-section-area and hencethe series-resistance and the overall current-density for each case is nearly thesame. The data from Fig. 2.12 shows that the k-factor can be improved signi-cant by using multiple layers and lower conductor-width. The parasitic capacityto ground shown in Fig. 2.13 has also increased by using metal layer Alu1. So op-timum in this case is to use Alu2 and Alu3. It shows the lowest parasitic capacityto ground and an improved k-factor. The data from Fig. 2.12 and Fig. 2.13 wasgenerated with FastTrafo.

    Overlay Coupled Transformers

    A monolithic planar transformer is constructed using conductors interwound inthe same plane. Another possibility to construct a transformer is to use conduc-tors overlaid as stacked metal. The planar transformer which have the conductorsin the same plane is a edge or horizontally coupled transformer. The second kindwhich have stacked conductors is a overlay or broadside coupled transformer. The

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 18

    3 4 5 6 7 8 9 100.5

    0.55

    0.6

    0.65

    0.7

    0.75

    Coup

    ling

    Coef

    ficie

    nt k

    PS

    Spacing S in m

    2:2 Transformer, 4 turns, r i=25m, S=3m , B6HFC (Fig. 2.1)

    W= 4m, Alu3, Alu2, Alu1 W= 6m, Alu3, Alu2 W=10m, Alu3

    Figure 2.12: k-factor of transformer with dierent numbers of metal layer.

    3 4 5 6 7 8 9 1070

    80

    90

    100

    110

    120

    130

    140

    150

    160

    170

    Para

    sitic

    Cap

    acity

    CO

    XP in

    fF

    Spacing S in m

    2:2 Transformer, 4 turns, r i=25m, S=3m , B6HFC (Fig. 2.1)

    W= 4.7m, Alu3, Alu2, Alu1 W= 5.8m, Alu3, Alu2 W=10m, Alu3

    Figure 2.13: Parasitic capacity from primary winding to ground.

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 19

    advantage of overlaying the windings compared to the planar transformer is thatapproximately one-half of the chip area is required. The main disadvantage ofbroadside coupled transformers is a large parallel-plate component to the capac-itance between windings due to the overlapping of metal layers, which limits thefrequency response. Multiple layers must be shared between the secondary andprimary winding to construct the windings , follows a higher ohmic loss. Also,a symmetric design can not be performed, which involves all disadvantages ofnon-symmetric designs.

    The better performance of planar transformers is the reason why only this kindis explained in this work.

    Summary of Design Rules

    Many aspects of design possibilities have been presented in this chapter. Thediscussed design rules are valid for the general design of monolithic transformers.The nal circuit design depends on the desired electrical characteristics and candier from the presented design techniques. The designer is able to optimize a lotof parameters in order to make an intelligent design compromise.

    A highly optimized circular-shaped monolithic transformer which is used in thepower amplier mentioned in Chapter 1 (Fig. 1.1) is presented in Sect. 4.1. Athree dimensional top view of the transformer is shown in Fig. 4.2.

    Now lets make a short summery about optimization techniques for monolithicintegrated lumped transformers:

    Use narrowly spaced conductors to improve the magnetic coupling be-tween windings.

    If possible use a trackwidth to spacing ratio of W=S 2 for your design.

    Adjacent conductors should belong to dierent windings.

    Use a interlaced winding-scheme for reaching the desired turn ratio.

    Use multiple layers of metal to reduce the ohmic loss.

    Check the performance of circular and square shape design.

    2.3 Transformer Model

    The complete electrical behavior of a monolithic integrated lumped transformercannot be accurately predicted from closed-form equations. A alternative for de-sign and optimization is a lumped-element equivalent circuit. The aim of pre-cise and fast transient analysis of RF circuits using monolithic transformers was

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 20

    reached with a compact lumped low order model. The complexity of this model islow enough and the precision is high enough to perform fast and accurate analysisof the integrated circuits.

    p-Substra

    te

    Oxide

    Figure 2.14: Three dimensional cross section of a transformer with basic modelelements.

    An electrical model of a transformer can be derived from the physical layoutand process technology. Fig. 2.14 shows a cross-section of a monolithic integratedlumped transformer. The circuit devices illustrated in the gure are the basicelements of the equivalent circuit and can be identied as:

    Multiple coupled inductors of the windings.

    Ohmic loss in the conductor material due to skin eect, current crowdingand nite conductivity.

    Parasitic capacitive coupling between the windings.

    Parasitic capacitive coupling into the substrate.

    Losses in the conductive substrate.

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 21

    Lumped 16-element Model

    With this basic elements a lumped low-order equivalent model was constructed.The model shown in Fig. 2.15 can be used directly in a time-domain circuitsimulation (i.e. SPICE).

    PRIMARY WINDING

    SECONDARY WINDING

    P-

    S-

    P+

    S+

    LRC

    CC CC

    R

    R C

    R L

    C R

    C R

    Coupling Coefficient:

    k (L ,L )

    SubP2

    SubS2

    SubP1

    SubS1

    OXP1

    OXS1

    OXP2

    OXS2

    K4 K3 K2

    P

    S

    P

    S

    K1

    P SPS

    Figure 2.15: Basic equivalent circuit of the transformer without center taps.

    Self inductance of the conductors are modeled by components LP for the primarywinding and LS for the secondary winding. The inductances are coupled mutuallydenoted by the coupling coecient kPS.

    Ohmic loss in the conductor material due to skin eect, current crowding andnite conductivity is modeled by components RP for the primary winding andRS for the secondary winding.

    The parasitic capacitive coupling between primary and secondary winding is mod-eled by components CK1, CK2, CK3 and CK4. The sum of all four capacities isequivalent to the static capacity between primary and secondary winding and canbe measured between primary and secondary port. The capacities CK2 and CK3placed across the windings model the capacity between the individual turns ofeach winding.

    The parasitic capacitive coupling into the substrate is modeled by componentsCOXP1, COXP2 for the primary winding and COXS1, COXS2 for the secondarywinding. The sum of the capacities for each winding is the static capacity to thesubstrate.

    The losses in the conductive substrate are modeled by components RSubP1, RSubP2for the primary winding and RSubS1, RSubS2 for the secondary winding.

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 22

    Expanded Lumped 24-element Model

    In applications it is commonly required to use such transformers in balancedcircuits, for which at least at one of the transformer windings a center tap exists.The equivalent circuit in Fig. 2.15 shows the case without center taps. This modelcan be expanded to include center taps. Fig. 2.16 shows the expanded model withprimary and secondary center taps.

    PRIMARY WINDING

    SECONDARY WINDING

    P-

    S-

    P+

    S+

    PrimaryCenter Tap

    SecondaryCenter Tap

    L

    R C

    LRC

    CC CC

    R

    R C L

    R C

    L C R

    R R

    R C R

    Coupling Coefficients:

    Sub5 Sub4

    Sub5

    Sub1

    Sub2

    Sub3 OX3

    OX5

    OX5

    OX2

    OX1

    OX4

    S2

    S4 S3

    S1

    4 3

    12

    K4 K3 K2 K1

    k (L ,L )1 212k (L ,L )3 434k (L ,L )1 313k (L ,L )2 424k (L ,L )1 414k (L ,L )2 323

    Figure 2.16: The Lumped-Equivalent-Circuit of the transformer [Simburger 99].

    Self inductance of the conductors are splitted into components L1, L2 for theprimary winding and L3, L4 for the secondary winding. Each inductance is cou-pled mutually with every other inductance, denoted by the coupling coecientsk12; k34; k13; k24; k14 and k23. Note that the problem increases to a multiple coupledinductors problem.

    Ohmic losses in the conductor material due to skin eect, current crowding andnite conductivity are splitted into RS1, RS2 for the primary winding and RS3,RS4 for the secondary winding.

    The parasitic capacitive coupling between primary and secondary winding is mod-eled by components CK1, CK2, CK3 and CK4. The capacities CK2 and CK3 placedacross the windings model the capacity between the individual turns of eachwinding. CK2 and CK3 also describe the dierent cases of operation (i.e. primarycenter tap or primary port P- grounded).

    The parasitic capacitive coupling into the substrate is modeled by componentsCOX1, COX2 and COX3 for the primary winding and COX4, COX5, and COX6 for

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 23

    the secondary winding. The sum of the capacities for each winding is the staticcapacity to the substrate. The division into three capacities on each side is againthe modeling for dierent operation cases.

    The losses in the conductive substrate are modeled by components RSub1, RSub2and RSub3 for the primary winding and RSub4, RSub5, and RSub6 for the secondarywinding. The substrate-resistance is distributed into three resistors for each wind-ing.

    Conversion from the 24-element to the 16-element Model

    The equivalent circuit shown in Fig. 2.16 can be reduced to the model shown inFig. 2.15. The relation between these two models and its parameters is derivedin the following equations.

    The inductance values LP and LS can be calculated with the following equations.

    LP = L1 + L2 + 2M12 = L1 + L2 + 2 k12qL1 L2 (2.16)

    LP = L3 + L4 + 2M34 = L3 + L4 + 2 k34qL3 L4 (2.17)

    The coupling coecient kPS can be calculated to

    kPS =k13pL1 L3 + k14

    pL1 L4 + k23

    pL2 L3 + k24

    pL2 L4p

    LP LS(2.18)

    The series resistance of the windings follow as

    RP = 2RS1 = 2RS2 (2.19)

    RS = 2RS3 = 2RS4

    The substrate resistances RSub are converted to

    RSubP1 = RSubP2 = RSub1=2 (2.20)

    RSubS1 = RSubS2 = RSub4=2

    The parasitic oxid capacities COX follow as

    COXP1 = COXP2 = 2COX1 (2.21)

    COXS1 = COXS2 = 2COX4

    The parasitic capacitive coupling between the windings, denoted by CK , is thesame in both models.

  • CHAPTER 2. DESIGN OF INTEGRATED TRANSFORMERS 24

    Validity of the Transformer Model

    The transformer models presented in Sect. 2.3 result in fast and accurate anal-ysis of the integrated circuits. The complexity of the equivalent models are lowenough and the precision is high enough for accurate simulation of the electricalcharacteristics. In Chapter 4 the measurement is compared to the simulation re-sults of two design examples. It shows in details the accuracy of the presentedtransformer model.

    In general the transformer model is valid down to DC. Normally monolithic trans-formers have operating frequencies in the GHz-range and hence the DC-case isnot of interest. When biasing primary and secondary side on dierent levels thevalidity of the DC-case is helpful and necessary.

    The upper frequency limit of the model depends on the transformer geometry.As shown previously in Sect. 2.2 the unequation (2.4) must be fullled for validsimulation results. The maximum operating frequency of the transformer in typ-ical applications is about 2/3 times of the self resonant frequency. In most casesthe upper limit of the model is about 3/2 times the self resonant frequency of thetransformer.

  • Chapter 3

    Parameter Extraction

    The lumped low-order equivalent model considered in Sect. 2.3 describes the elec-trical behavior of a monolithic integrated lumped transformer. This chapter givesthe background details about extraction of all elements used in the equivalent-circuit. In Sect. 3.1 the inductance of transformers built up from straight con-ductors is derived. The losses in the conductors due to skin eect and currentcrowding are derived in Sect. 3.2. The conductive substrate causes additionallosses treated in Sect. 3.3. In Sect. 3.4 some thesis about the parasitic capaci-tive coupling between the windings and the substrate are presented. Finally teststructures for the measurement are presented.

    3.1 Inductance Calculation

    Inductance extraction is based on Maxwells Equations

    ~5 ~H = ~J + @t ~D (3.1)

    where ~H is the magnetic eld quantity, ~J is the current density and ~D is theelectric flux density.

    Now we apply the magnetoquasistatic assumption. The frequencies of interestwill be considered small enough such that the displacement current in (3.1) canbe neglected.

    ~5 ~H = ~J (3.2)

    This assumption is clearly justied within the conductors where the conductivityis large. From the Ampere-Maxwell-Law (3.1) in magnetoquasistatic case (3.2)is it possible to derive the known formulas of self-inductance L and mutual-inductance M for two current loops [Smythe 68].

    25

  • CHAPTER 3. PARAMETER EXTRACTION 26

    L = I I 1

    4rd~s d~s (3.3)

    M = I I 1

    4j~r1 ~r2jd~s1 d~s2 (3.4)

    The mutual-inductance formula (3.4) is known as the Neumann Formula. Theintegration is round of two current loops. In most cases it exist a closed-formequation of (3.4).

    The self-inductance formula is mathematical more expensive and only in a viewcases exist a closed-form equation. The self-inductance of a loop is the mutualinductance to itself.

    Now we start the calculation of the basic element, a straight conductor, and willend at a transformer. The derivation based on (3.4) of the following formulas isnot executed in this work. The basic formulas are already noted in [Grover 46]and [Greenhouse 74].

    Mutual Inductance of Two Parallel Filaments

    The mutual inductance of two parallel laments with equal length is the basiccase for the treatment of circuits made up of parallel elements. The inductance-calculation of circuits made up of straight elements of negligible cross section(laments) have been solved and it exists a closed-form equation of (3.4).

    l

    d

    ds1

    ds2

    s ,s1 2

    Figure 3.1: Parallel conductor elements with same length

    Assuming the lengths of the laments in Fig. 3.1 to be l and their distance apartd the exact formula for the mutual inductance is

  • CHAPTER 3. PARAMETER EXTRACTION 27

    M =o2

    l

    24ln0@ ld

    +

    s1 +

    l2

    d2

    1As

    1 +d2

    l2+d

    l

    35 (3.5)If l d a better way is to make a row expansion of (3.5)

    M =o2

    l

    "ln

    2 l

    d 1 +

    d

    l

    1

    4

    d2

    l2

    #(3.6)

    The mutual inductance is dominated by ln(2l=d) and with the assumption thatl d some terms are negligible.

    Geometric Mean Distance GMD

    In calculating the mutual inductance of two conductors whose cross sectionaldimensions are small compared to their distance, the formulas above are valid.The mutual inductance is sensibly the same as the mutual inductance of lamentsalong their axes.

    A monolithic integrated transformer consists of conductors with a rectangularcross sections with non-negligible dimensions. In typical transformer designs thespacing S between two turns is smaller than the conductor-width W of the con-ductors. The cross-section dimensions of the conductors are to large to justify thesimplication made above. To use the formulas for calculating the inductance ofmonolithic transformers they must be corrected. The basic formula (3.5) for themutual inductance must be integrated over the cross sections of the conductors.The structure of the formula (3.5) is maintained, in fact only the distance d isreplaced by the corrected distance dGMD, called geometric mean distance.

    The geometric mean distance GMD between two conductors is the distance be-tween two innitely thin laments whose mutual inductance is equal to the mutualinductance between the two original conductors. More about the GMD and manytables with the GMD for dierent cross sections can be found at [Grover 46].

    In the case of monolithic integrated transformers a rectangular conductor crosssection is used. Fig. 3.2 illustrates two parallel conductor elements with rectan-gular cross section and its dimensions.

    The corrected distance dGMD between the conductors in Fig. 3.2 for inductancecalculation follows as

    dGMD = d ek (3.7)

    where k is the correction factor listed in Table 3.1.

    With the use of the geometric mean distance dGMD the basic equation (3.6) fortwo parallel laments follows to

  • CHAPTER 3. PARAMETER EXTRACTION 28

    ddGMDdGMD

    WW ST

    Figure 3.2: Parallel conductor elements with rectangular cross section.

    W=d T=W=0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

    0 0 0 0 0 0 0 0 0 0 0 00.05 -0.0002 -0.0002 -0.0002 -0.0002 -0.0002 -0.0002 -0.0001 -0.0001 -0.0001 -0.0000 0.00000.10 -0.0008 -0.0008 -0.0008 -0.0008 -0.0007 -0.0006 -0.0005 -0.0004 -0.0003 -0.0002 0.00000.15 -0.0019 -0.0019 -0.0018 -0.0017 -0.0016 -0.0014 -0.0012 -0.0010 -0.0006 -0.0003 0.00000.20 -0.0034 -0.0033 -0.0032 -0.0030 -0.0028 -0.0025 -0.0021 -0.0017 -0.0012 -0.0006 0.00000.25 -0.0053 -0.0052 -0.0051 -0.0048 -0.0044 -0.0039 -0.0034 -0.0027 -0.0019 -0.0010 0.00000.30 -0.0076 -0.0076 -0.0073 -0.0069 -0.0064 -0.0057 -0.0048 -0.0038 -0.0027 -0.0014 0.00010.35 -0.0105 -0.0104 -0.0100 -0.0095 -0.0087 -0.0078 -0.0066 -0.0052 -0.0036 -0.0018 0.00020.40 -0.0138 -0.0136 -0.0132 -0.0125 -0.0115 -0.0102 -0.0086 -0.0068 -0.0047 -0.0024 0.00020.45 -0.0176 -0.0174 -0.0169 -0.0159 -0.0146 -0.0130 -0.0110 -0.0086 -0.0059 -0.0029 0.00030.50 -0.0220 -0.0217 -0.0210 -0.0198 -0.0182 -0.0161 -0.0136 -0.0106 -0.0073 -0.0036 0.00050.55 -0.0269 -0.0266 -0.0257 -0.0243 -0.0222 -0.0197 -0.0164 -0.0128 -0.0087 -0.0042 0.00070.60 -0.0325 -0.0321 -0.0310 -0.0292 -0.0267 -0.0235 -0.0196 -0.0152 -0.0103 -0.0048 0.00100.65 -0.0388 -0.0383 -0.0369 -0.0347 -0.0316 -0.0277 -0.0231 -0.0178 -0.0120 -0.0055 0.00140.70 -0.0458 -0.0452 -0.0435 -0.0408 -0.0370 -0.0324 -0.0269 -0.0207 -0.0137 -0.0062 0.00190.75 -0.0536 -0.0529 -0.0509 -0.0476 -0.0431 -0.0375 -0.0310 -0.0237 -0.0156 -0.0070 0.00230.80 -0.0625 -0.0616 -0.0591 -0.0551 -0.0497 -0.0431 -0.0354 -0.0269 -0.0176 -0.0075 0.00310.85 -0.0725 -0.0714 -0.0683 -0.0634 -0.0569 -0.0491 -0.0401 -0.0302 -0.0195 -0.0081 0.00370.90 -0.0839 -0.0825 -0.0786 -0.0726 -0.0648 -0.0555 -0.0451 -0.0337 -0.0216 -0.0087 0.00460.95 -0.0973 -0.0954 -0.0903 -0.0828 -0.0734 -0.0625 -0.0504 -0.0374 -0.0236 -0.0092 0.00561.00 -0.1137 -0.1106 -0.1037 -0.0942 -0.0828 -0.0700 -0.0561 -0.0413 -0.0258 -0.0098 0.0065

    Table 3.1: Correction factor k of (3.7) for rectangular cross section with W=d andT=W [Grover 46].

    M =o

    2l

    "ln

    2 l

    dGMD 1 +

    dGMD

    l

    1

    4

    d2GMDl2

    #(3.8)

  • CHAPTER 3. PARAMETER EXTRACTION 29

    Mutual Inductance of Unequal Parallel Conductors

    Two laments of lengths lj and lm are separated by a distance d. The situationis illustrated in Fig. 3.3.

    d

    l j

    lp lm lq

    jm

    Figure 3.3: Parallel conductor laments with dierent length.

    The mutual inductance between conductor j and m can be calculated as

    Mj;m =1

    2[M(lm + lp) +M(lm + lq)M(lp)M(lq)] (3.9)

    where the individual M-terms are calculated using the basic formula (3.6). Forconductors with rectangular cross section use the distance dGMD derived in (3.7).Formula (3.9) applies the laws of summation of mutual inductances and is basedon the case of equal parallel laments.

    In the case of lp = lq (3.9) simplies to

    Mj;m = M(lm + lp)M(lp) (3.10)

    for lp = 0,

    Mj;m =1

    2[M(lj) +M(lm)M(lq)] (3.11)

    Other more general expressions (i.e. laments inclined at an angle to each other)are available in [Grover 46], we will limit ourselves for purposes of this work tothe noted relationships.

    Self Inductance of a Straight Conductor

    The self inductance of a straight conductor is an included case in the mutualinductance of two parallel equal conductors. The self inductance is the mutualinductance to itself.

    Based on (3.8) the self inductance of a straight conductor with rectangular crosssection and constant current density was noted by [Greenhouse 74] and can bewritten as

    L =o2l

    "ln

    2l

    W + T

    !+ 0:50049 +

    W + T

    3l

    #(3.12)

  • CHAPTER 3. PARAMETER EXTRACTION 30

    where l is the length of the conductor, W the width and T the height of therectangular cross section.

    Inductance Calculation of Monolithic Transformers

    Transformers composed of straight conductors can be treated with the summa-tion of self- and mutual-inductances of the individual conductor elements. Thecalculation procedure will be explained with the help of the transformer presentedin Fig. 2.5. The layout of the transformer is illustrated in Fig. 3.4. The trans-former has a turn ratio of n = 2 : 2. For the inductance calculation the primarywinding is divided into nP = 11 individual conductors numbered from 1-11. Thesecondary winding is divided into nS = 11 individual conductors numbered from12-22.

    P+

    P-

    S+

    S-

    221

    7

    16

    1851310

    1114

    6

    19

    17

    412

    9

    822

    3

    15

    201

    Figure 3.4: Square-shaped monolithic transformer with a turn ratio of n = 2 : 2.

    For the self inductance calculation of the individual conductors Li equation (3.12)is used. The self inductance of the primary- LP and secondary-winding LS is thesum of all self inductances of the conductors Li plus the sum of the mutual induc-tances of every conductor to every conductor Mi;k. The complete self inductance

  • CHAPTER 3. PARAMETER EXTRACTION 31

    of the windings can be written as

    LP =nPXi=1

    Li + 2np1Xi=1

    nPXk=i+1

    Mi;k (3.13)

    LS =nP+nSXi=nP+1

    Li + 2nP+nS1Xi=nP+1

    np+nSXk=i+1

    Mi;k (3.14)

    where i; k are the numbers of the individual conductors (i.e. For the secondarywinding in Fig. 3.4 the conductor numbers are i = 12 ::: 22 ).

    The mutual inductance M between the two windings is the sum of the mutualinductances of every primary conductor to every secondary conductor. The com-plete mutual inductance between the windings can be written as

    M =nPXi=1

    nP+nSXk=nP+1

    Mi;k (3.15)

    The summation indices are again the numbers of individual conductors. Themutual inductance of the element Mi;k is calculated with (3.8) or (3.9).

    The presented method is realized in FastTrafo which uses the FEM-core Fas-tHenry [MIT 96] for inductance calculation. The whole transformer geometrybuilt up of straight conductors is the input to the FEM-core. The exact model-ing of the planar construction is an important task for an accurate inductanceextraction. The exact modeling of the layer construction is less important.

    Fig. 3.5 shows the simulation of the self inductance as a function of primaryturns. The device under test is the transformer BL62S005 which is presentedin Sect. 4.1. The data plotted in Fig. 3.5 was extracted with FastTrafo. Theinductance is proportional to N1:9, in theory it is proportional to N2. The plotin Fig. 3.5 shows both curves. The simulation shows clearly the ve cross-oversections of the primary winding.

    3.2 Skineect and Current Crowding

    At radio frequencies the penetration of current and magnetic eld into the surfaceof conductors tends only to a limited depth. If the thickness of a conductor is muchgreater than the depth of penetration, its behavior at high frequencies becomesa surface phenomenon.

    Maxwell discovered that the voltage required to force a varying current througha wire increases more than could be explained by inductive reactance. The phe-nomenon is called "skin eect". The current is concentrated in the outer surfaceof the conductor, it is crowded to the outer edge of the conductor.

  • CHAPTER 3. PARAMETER EXTRACTION 32

    0 20 40 60 80 100 1200

    0.2

    0.4

    0.6

    0.8

    1

    1.2

    1.4

    Self

    Iindu

    ctan

    ce L

    in n

    H

    Elements (20 Elements =1 Winding)

    Simulation with FastTrafoApproximation: ~N1.9 Approximation: ~N2

    Figure 3.5: Primary self inductance of the transformer BL62S005 with 6 turns onthe primary side.

    The depth of current penetration in a conductor depends on the frequency andalso on the properties of the conductive material, its conductivity or resistivity and its permeability .

    The depth of penetration is dened as the depth at which the current density (ormagnetic flux) is attenuated by 1=e (-8.7dB). The depth of penetration , by thisdenition, is

    =

    s2

    !(3.16)

    is always greater than 0:9m at frequencies smaller than 10 GHz in aluminumas conductor material.

    3.2.1 Equivalent Series Resistance

    The conductor-height T of monolithic transformers depends on the semiconductorprocess and is in a typical range of 0:5m T 2m. So in most cases theskin-eect in vertical direction is negligible. The horizontal conductor dimensions(conductor-width W ) can be greater and the resistance can rise signicantly atfrequencies smaller than 10 GHz.

  • CHAPTER 3. PARAMETER EXTRACTION 33

    The series resistance of the conductors at near direct current frequencies can bewritten as

    RAC = RDC = l

    WT(3.17)

    Equation (3.17) is valid when the conductor dimensions W and T are smaller thanthe penetration depth . If this assumption is not fullled the series resistancerises at higher frequencies. The series resistance is proportional to

    pf for high

    frequencies.

    RAC qf; f !1 (3.18)

    At low frequencies the resistance is proportional to

    RDC 1 + f2; f ! 0 (3.19)

    With (3.18) and (3.19) a equation for the resistance RAC as a function of frequencycan be found. An accurate formula for the series resistance was given by [Lofti 95].

    RAC = RDC

    241 + ffl

    !2+

    f

    fu

    !535 110 (3.20)fl =

    2WT; fu =

    2

    T 2

    24K0@s1 T 2

    W 2

    1A352 (3.21)The frequencies fl and fu are the cutting frequencies of the low frequency caseand of the high frequency case. K is the elliptic integral rst order and is availablein tables or i.e in the software MatlabTM .

    K(x) =Z

    2

    0

    1q1 x2 sin2()

    d (3.22)

    The error of equation (3.20) within the assumption that 0:3 < T= < 2 is smallerthan 1%.

    Fig. 3.6 shows the primary and secondary series resistance of the example trans-former presented in Sect. 2.2.2 (Fig. 2.5(b)) with dierent track width W . Theconductor material is aluminum and has a conductivity of = 33S=m and athickness of T = 1:4m. The simulation with the lower track width W shows thehigher DC-resistance but the skin-eect starts at higher frequencies comparedto the simulations with higher track width. The simulation was done with thetransformer CAD-tool FastTrafo.

  • CHAPTER 3. PARAMETER EXTRACTION 34

    101 100 101 1021

    2

    3

    4

    5

    6

    7

    8

    9

    10

    Serie

    s Re

    sista

    nce

    in

    Frequency in GHz

    2:2 Transformer, S=3 m, r i=25m, Alu3, B6HFC (Fig. 2.1)

    W=4m Primary W=4m Secondary W=7m Primary W=7m Secondary W=10m Primary W=10m Secondary

    Figure 3.6: Series resistance of a 2:2 Transformer (Fig. 2.5(b)) as a function offrequency.

    3.3 Substrate Loss

    The substrate-material of silicon based technologies is p-doted silicon. It is amixture of conductor and dielectric, which means that the substrate of each tech-nology has a nite conductivity and relative permittivity "r 1. In recentsemiconductor processes the conductivity can reach values from a few Siemensper Meter up to 200 S/m .

    Capacitive coupling from the conductor to substrate and nite conductivity ofthe substrate causes a current flow from the conductor through the substratedown to the ground plane. This current flow represents additional losses whichare modeled by substrate resistances RSub in the equivalent circuit of Sect. 2.3.Now a new expression for the substrate resistance is derived. The formula is basedon impedance expressions in [Hilberg 81] and simulations with the 2-D FEM eldsimulator Maxwell eld [Ansoft 93].

    3.3.1 Conductor on Substrat

    Monolithic integrated transformers are complex 3-D geometries. Step by step wewant to develop an accurate approximation for the substrate resistance.

  • CHAPTER 3. PARAMETER EXTRACTION 35

    First we simplify the situation to a 2-D-problem. Figure 3.7 shows a single con-ductor placed directly on the substrate. On the upper side the conductor is sur-rounded by a dielectric. On the bottom side the substrate with a nite conduc-tivity is situated. The ground plane is at the bottom of the substrate. The areaupside the conductor is not of interest for resistance calculation.

    r=3.9

    r=11.9

    Dielectric

    Substrate

    Conductor=

    Ground Plane=

    W

    Hsub

    T=0

    =12.5 S/m

    Figure 3.7: Conductor placed directly on the substrate.

    1.17e+007 1.05e+007 9.32e+006 8.16e+006 6.99e+006 5.83e+006 4.66e+006 3.50e+006 2.33e+006 1.17e+006 0.00e+000

    Substrate

    Dielectric

    Mag J in [A/m ] 2

    Figure 3.8: Lines of constant current density around a conductor placed on thesubstrate.

    Fig. 3.8 shows lines of constant current density representing the current-flow from

  • CHAPTER 3. PARAMETER EXTRACTION 36

    the conductor to the ground plane. The voltage amplitude is 1V. The substratematerial has a thickness of HSub = 200m and a conductivity of = 12:5S/m.The current density has a maximum at the edges of the conductor. At somedistance to the conductor the lines of constant current density get an ellipticshape. The simulation was done with the 2-D FEM simulator Maxwell eld by[Ansoft 93].

    Now we want to calculate the resistance from the conductor to the ground plane.To solve this task it makes sense to reduce the problem to a known physicallayout. The "mirror method" is a perfect tool to convert the situation to a knownproblem and also to go back to original physical layout.

    If we mirror horizontally at the line of the conductor we get the situation shownin Fig. 3.9. There is exact correspondence between the parts on either side of thecentral line.

    r,Substrate

    Conductor=

    Ground Plane=

    W

    2Hsub

    Hsub

    T

    Figure 3.9: Mirror method: The situation in Fig. 3.7 is mirrored horizontally.

    Under the condition that the conductivity of the substrate Sub = 0 we can handlethe geometry in Fig. 3.9 as a transmission line. The characteristic impedance ofa lossless transmission line can be written as

    Z =

    sL0

    C 0; Sub = 0; COND =1 (3.23)

    where L0 is the inductance and C 0 the capacity per length unit of the transmissionline.

    It exists an impedance-formula for the physical layout shown in Fig. 3.9. In thecase of a perfect insulator ( = 0) instead the substrate the formula for thecharacteristic impedance was noted by [Hilberg 81].

  • CHAPTER 3. PARAMETER EXTRACTION 37

    Z =

    2ln2 coth

    8

    W

    HSub

    ; for Z > =4 (3.24)

    Z =

    8= ln

    2 e

    4

    WHSub

    ; for Z < =4 (3.25)

    where is a constant depending on the material. In the case of the transmissionline is the phase velocity in the dielectric.

    =

    r

    (3.26)

    The current eld lines in Fig. 3.8 are similar to the electric eld lines of theequivalent transmission line. Because of this fact we want to suppose that thespecic resistance RSub is proportional to the impedance Z of the transmissionline.

    R0Sub Z (3.27)

    Some simulations for the specic substrate resistance make clear that the con-stant is the specic resistivity of the substrate.

    = (3.28)

    With (3.28) the formula for the specic substrate resistance of a single conductorplaced on the substrate can be written as

    R0Sub =

    ln2 coth

    8

    W

    HSub

    ; for W=HSub < 1 (3.29)

    R0Sub =

    4= ln

    2 e

    4

    WHSub

    ; for W=HSub > 1 (3.30)

    The approximation and simulation of the substrate resistance is illustrated inFig. 3.10. Note the two valid ranges for the approximations. In practice W=HSubis always smaller than 1 and therefore (3.29) is relevant. The error of the approx-imations in the valid range compared to the simulation is always smaller than3%. The simulations was done with FastHenry and Maxwell Field Simulator.

    3.3.2 Conductor Suspended in Dielectric

    A conductor placed directly on the substrate as considered in Sect. 3.3.1 is notthe case at monolithic integrated transformers. Mostly, semiconductor processesallow only conductor suspended in a dielectric above the substrate. We have to

  • CHAPTER 3. PARAMETER EXTRACTION 38

    0 200 400 600 800 10000

    20

    40

    60

    80

    100

    120

    140

    160

    180

    R Sub

    in

    m

    m

    Width W in m

    Cond. on Substrate: HOX=0m, T=0.1m, HSub=200m, =12.5S/m

    Maxwell FastHenry Approx. for W/HSub1

    Figure 3.10: Specic resistance from a single trace placed on the substrate to theground plane.

    Dielectric

    Substrate

    Conductor=

    Ground Plane=

    W

    H sub

    H ox

    r=3.9

    r=11.9

    =0

    =12.5 S/m

    T

    Figure 3.11: Conductor suspended in a dielectric above the substrate.

    work out a formula based on (3.29) and (3.30) to calculate the resistance fromthe conductor through the substrate to the ground plane.

    Fig. 3.11 shows a conductor (i.e a turn of a transformer) suspended in an ideal

  • CHAPTER 3. PARAMETER EXTRACTION 39

    dielectric ( = 0). The conductor has a width ofW and a distance to the substrateof HOX. The conductive substrate has a height of HSub. A ground plane is placedat the bottom.

    Mag J in [A/m ] 3.69e+001 3.32e+001 2.95e+001 2.58e+001 2.21e+001 1.84e+001 1.48e+001 1.11e+001 7.38e+000 3.69e+000 0.00e+000

    Substrate

    Dielectric 2

    Figure 3.12: Lines of constant current density around a conductor suspended ina dielectric.

    Fig. 3.12 shows the simulation done with the Maxwell Field Simulator. The volt-age amplitude is 1V. The substrate material has a thickness of HSub = 200mand a conductivity of = 12:5S/m. Capacitive coupling causes a displacementcurrent to the substrate. Fig. 3.12 shows lines of constant current density whichhave again an elliptic shape at some distance to the conductor.

    From Fig. 3.12 is clear that the current-feed-in area at the substrate edge hasa greater width than the physical width W caused by capacitive coupling. Wedene an eective feed-in width Weff depending on the distance HOX and theconductor height T .

    Weff = W + 6HOX + T (3.31)

    The physical width W is replaced in (3.29) and (3.30) by the eective width Weffand the specic substrate resistance of a single conductor suspended in a dielectricabove the substrate can be written as

    R0Sub =

    ln2 coth

    8

    W + 6HOX + T

    HSub

    ; for

    WeffHSub

    < 1 (3.32)

    R0Sub =

    4= ln

    2 e

    4

    W+6HOX+T

    HSub

    ; for

    WeffHSub

    > 1 (3.33)

  • CHAPTER 3. PARAMETER EXTRACTION 40

    The equations are valid within the range whereby in practice (3.32) is relevant.

    The approximation and simulation of the substrate resistance is illustrated inFig. 3.13. For distances HOX > 0 the substrate tends to a limited value if W isnear zero (W ! 0). The error of the approximations in the valid range comparedto the simulation is always smaller than 3%. The simulation data in Fig. 3.13 wasproduced with Maxwell Field Simulator.

    0 50 100 150 2000

    20

    40

    60

    80

    100

    120

    140

    160

    180

    200

    R Sub

    in

    m

    m

    Width W in m

    Conductor in Air: T=0.1m, Substrate: HSub=200m, =12.5S/m

    HOX=0m HOX=2.5mHOX=7.0mApproximations

    Figure 3.13: Specic resistance from a single conductor to ground plane.

    RSub of a complete transformer winding is based on (3.33) and (3.32) where Wis replaced by the width of the primary winding WP = rOP rIP or secondarywinding WS = rOS rIS as shown in Fig. 2.5. RSubP for the primary winding canbe written as

    RSubP =

    lMPln2 coth

    8

    WP + 6HOX + T

    HSub

    (3.34)

    RSubS =

    lMSln2 coth

    8

    WS + 6HOX + T

    HSub

    within the range Weff=HSub < 1 and

    RSubP =

    4 lMP= ln

    2 e

    4

    WP+6HOX+T

    HSub

    (3.35)

    RSubS =

    4 lMS= ln

    2 e

    4

    WS+6HOX+T

    HSub

  • CHAPTER 3. PARAMETER EXTRACTION 41

    within the range Weff=HSub < 1, where lMP and lMS are the mean perimetersof the transformer windings. In the case of a circular transformer as shown inFig. 2.5 lMP and lMS are calculated as

    lMP = (rOP + rOP ); lMS = (rOS + rIS) (3.36)

    In the case of a square shaped transformer as shown in Fig. 2.4 lMP and lMS arecalculated as

    lMP = 4 (aOP + aOP ); lMS = 4 (aOS + aIS) (3.37)

    The resistances RSub1 to RSub6 of the model shown in Fig. 2.16 can be determinedas

    RSub1 = RSub3 = 4RSubP ; RSub2 = 2RSubP (3.38)

    RSub4 = RSub6 = 4RSubS; RSub5 = 2RSubS

    3.4 Capacity Extraction

    Parasitic capacities are dicult to determine accurately. The conductors of mono-lithic integrated transformers represent closely coupled lines. Because of the dom-inance of the edge singularity and coupled conductor construction, capacitive ef-fects are best investigated in mesh point analysis and simulations. However, somebasics about capacity calculation are presented in this section.

    The parameters needed to characterize the capacity of coupled structures are theeven- and odd-mode capacitances of parallel coupled conductors.

    CU1 U2 =-U1

    1 2U

    Ce1 Ce2U1 U1

    (b)

    1 2U=0

    Ce1 Ce2

    (a)

    ' '

    '

    Figure 3.14: (a)Even- and (b)odd-mode capacities of two conductors.

    Fig. 3.14 shows the two possible cases for two coupled conductors embeddedin a uniform homogeneous dielectric of permittivity and permeability 0. Theeven-mode happens if in both conductors the voltage have the same amplitudeand phase. If the voltages are not in phase a gap capacity C represents theodd-mode. The operation mode of a monolithic transformer is a mixture of bothmodes.

  • CHAPTER 3. PARAMETER EXTRACTION 42

    Fringing Capacities

    The capacity calculation can be splitted into several parts of capacities. Fig. 3.15shows all considered capacities for the calculation of the total odd-mode andeven-mode capacity.

    S W

    T

    Cp'Cf' Cfe'

    Cfo'Cfo'

    Co'

    Hox

    Figure 3.15: Capacitive coupled rectangular conductors suspended in a dielectric.

    To nd total even-mode capacitance C 0e to ground (Fig. 3.14) the appropriatecomponents of fringing capacitance are added to the parallel-plate componentC 0p. For a line of more than two conductors the total even-mode capacitance canbe written as

    C 0e = C0p + 2C

    0fe (3.39)

    In calculating total capacitance for the end lines in Fig. 3.4, care must be takento add to the parallel-plate component the appropriate fringing capacitance ateach edge of the conductor. The even-mode capacitance for the end conductor is

    C 0e = C0p + C

    0fe + C

    0f (3.40)

    The dierence between odd- and even-mode fringing capacitance is denoted bythe gap capacitance C 0.

    C 0 = C 0o + C0fo C

    0fe (3.41)

    The parallel-plate capacitance between a conductor and the ground plane men-tioned in the equations before using the notation of Fig. 3.15 is

    C 0p = W

    HOX(3.42)

  • CHAPTER 3. PARAMETER EXTRACTION 43

    The calculation of the other fringing capacities in Fig. 3.15 can be found in[Gupta 69] and [Smith 71]. The even- and odd-mode capacities are considered bythe capacities CK1 to CK4 and COX1 to COX6 in the transformer model shown inFig. 2.16.

    As mentioned before the best way to extract the capacity of complex geometries isa simulation based on mesh analysis. The capacity-calculation of a complete inte-grated monolithic transformer in the tool FastTrafo is based on FastCap [MIT 92].The exact modeling of the layer construction is important to get accurate results.In order to reach short processing times only a small part of the transformerscross section is the input to the FEM-core FastCap. The static specic capacitiesfrom primary to secondary C 0PS, primary C

    0OXP to substrate and secondary C

    0OXS

    to substrate are extracted.

    The static capacities of the whole transformer are

    COXP = lMP C0OXP ; COXS = lMS C

    0OXS; CPS = lM C

    0PS (3.43)

    where lMP and lMS is calculated in (3.36) and (3.37). lM is the mean perimetersof the transformer. In the case of a circular transformer as shown in Fig. 2.5 lMis calculated as

    lM = [max(rOP ; rOS) + min(rIP ; rIS)] (3.44)

    In the case of a square shaped transformer as shown in Fig. 2.4 lM is calculatedas

    lM = 4 [max(rOP ; rOS) + min(rIP ; rIS)] (3.45)

    COX1 to COX6 in the equivalent model shown in Fig. 2.16 are determined as

    COX1 = COX3 = COXP=4; COX2 = COXP=2 (3.46)

    COX4 = COX6 = COXS=4; COX5 = COXS=2

    The sum of the capacities COX for each winding is the static capacity CP and CSto the substrate.

    The parasitic capacitive coupling between primary and secondary winding in theequivalent model are determined as

    CK1 = CK2 = CK3 = CK4 = CPS=4 (3.47)

    3.5 Test-Structures for Measurement and Char-

    acterization

    Scattering parameters (S-parameters) characterize the electrical behavior of amonolithic transformer completely. To compare the measurement with the modelwe need to measure the S-parameters of the transformer. Therfore, transformersare placed as a test-structure on silicon.

  • CHAPTER 3. PARAMETER EXTRACTION 44

    Fig. 3.16 shows the test-structure of the example transformer BL62S005 consid-ered in Sect. 4.1. The connection between measurement equipment and deviceunder test (DUT) is performed by tiny needles. To put the needles on the DUT,pads are needed which have big dimensions related to the transformer geometry.The pads represent a parallel plate capacitor and falsify the measurement of thetransformer. So additional test structures are necessary to get the S-parametersof the DUT.

    Figure 3.16: Test-structures for measurement of transformer BL62S005 withtransformer-, open- and short-structure.

    As known from network-analyzers we can calibrate with open- and short-test-structures. Fig. 3.16 shows additional test-structures for open and short. Aftermeasured S-parameters of open and short we can analyze the data. De-embeddingis the key for this task. The following steps show how to get the corrected S-parameters of the DUT. The S-parameters are converted to Y-parameters stan-dardized to Z0 = 50 . The conversion in both directions is dened as

    Y =1

    Z0

    h(E S)(E + S)1

    i(3.48)

    S =h(E Z0Y)(E + Z0Y)

    1i

    (3.49)

    where E is the identity matrix with ones on the diagonal and zeros elsewhere.

    E =

    1 00 1

    !

    The conversion from S-parameter to Z-parameter and back is dened as

    Z = Z0h(E + S)(E S)1

    i(3.50)

    S =h(Z=Z0 E)(Z=Z0 + E)

    1i

    (3.51)

    The measured S-parameters of the transformer-structure S corrected with themeasured S-parameters of the open structure SOP can be calculated as

    STrOp $ YTrOp = Y YOp (3.52)

  • CHAPTER 3. PARAMETER EXTRACTION 45

    The next step is to correct with the measured S-parameters of the short structureSSh.

    STr $ ZTr = ZTrOp ZSh (3.53)

    STr describes the electrical characteristic of the transformer and can be com-pared to the model. The data of the transformer-structure S in addition to test-structures SSh, SOp applies after de-embedding the real scattering parameters STrof the transformer.

    Fig. 3.17 shows the test structures of the example transformer N3M2 considered inSect. 4.2. Only a open structure is available which results in a bad de-embedding.

    Figure 3.17: Test-structures for measurement of transformer N3M2 withtransformer- and open-structure.

  • Chapter 4

    Design Examples

    A method for characterization of monolithic lumped planar transformers has beenproposed. The modeling and parameter extraction of such transformers has beenveried by multiple transformers. In this work the measurement of two types oftransformers is presented as example. The rst type oers a high coupling perfor-mance up to 4 GHz. The second type of transformer oers a high self resonancefrequency of 20 GHz.

    4.1 Monolithic Transformer BL62S005

    P+

    P-PCT

    S1S1S1

    S2S2

    S2S+SCTS-

    P1P6P2P5P3P4

    P-

    PCT

    3

    P+

    3

    SCTSCT

    S-S-

    1

    S+S+

    1

    N=6:2

    Figure 4.1: Transformer BL62S005: (a) Winding scheme (b) Schematic symbol[Simburger 00].

    46

  • CHAPTER 4. DESIGN EXAMPLES 47

    The monolithic integrated transformer BL62S005 was designed for the use asinput-balun and interstage matching network in power ampliers [Simburger 00].

    Fig. 4.1 shows the schematic symbol and the planar winding scheme of the trans-former. The transformer oers a high coupling performance due tue an interlacedwinding scheme. The six primary turns P1-P6 are connected in series. On the sec-ondary side the three outer and the three inner turns are connected in parallel toform two groups S1 and S2. The groups are connected in series. With six primaryturns and two secondary turns a turn ratio of n = 6 : 2 is achieved. Centertapsfor balanced applications on the primary side PCT and on the secondary sideSCT are available.

    Fig. 4.2 shows a three-dimensional topview of the transformer. The primary ports,P+, PCT and P-, are located on the left side. The secondary ports, S+, SCT andS-, are located on the right side. The transformer design is completely symmetricabout a line. The outer diameter is 2rO = 205m and the inner diameter is2rI = 50m. The lateral spacing between the turns is about 1:5m and hasdierent values for each metal layer. The conductor width on the primary sideis about W = 4m and dierent for each winding. The conductor width on thesecondary side about W = 3m and also dierent for each winding.

    The operation frequency of 1.9 GHz is in the range of mobile communications.The same design was used in a power amplier at 900 MHz [Heinz 00]. To get anoperation frequency at 900 MHz the whole transformer was scaled by a factor 2from 205m to 410m outer diameter.

    200

    m

    Figure 4.2: 3-D-view of the example transformer BL62S005 [Simburger 00].

  • CHAPTER 4. DESIGN EXAMPLES 48

    A three dimensional cross section of the transformer BL62S005 is shown inFig. 2.11. The primary winding consists of metal 3 and metal 2 connected in par-allel and is separated to the substrate by HOX=3:1m. The secondary windingconsists of metal 1-3 connected in parallel to decrease the ohmic loss. The dis-tance to the substrate is HOX=1:6m resulting in a higher capacitive couplinginto the substrate compared to the primary winding.

    4.1.1 Measurement and Simulation Results up to 5GHZ

    The equivalent circuit of the high coupling performance transformer BL62S005is shown in Fig. 4.3. All parameter values are extracted by simulation with Fast-Trafo.

    L

    3

    0.156nH

    R

    S3

    1.25

    L

    4

    0.156nH

    R

    S4

    1.25

    C

    OX4

    97fF

    R

    Sub4

    908

    C

    OX6

    97fF

    R

    Sub6

    908

    L

    1

    R

    S1

    L

    2

    R

    S2

    C

    OX1

    R

    Sub1

    C

    OX3

    R

    Sub3

    1.03nH 3.871.03nH3.8749fF 49fF 805805

    R

    Sub2

    402

    C

    OX2

    98fF

    C

    K3

    140fF

    C

    K2

    140fF

    C

    K4

    140fF

    C

    K1

    140fF

    R

    Sub5

    454

    C

    OX5

    194fF

    Primary Center Tap

    Secondary Center Tap

    S-

    S+

    P-

    P+

    1

    1

    1

    1

    1

    1

    13

    18

    12

    14

    16

    10

    15

    7

    3

    2

    6

    5

    8

    4

    k

    12

    (L

    1

    ,L

    2

    )=0.68

    k

    34

    (L

    3

    ,L

    4

    )=0.50

    k

    13

    (L

    1

    ,L

    3

    )=0.70

    k

    24

    (L

    2

    ,L

    4

    )=0.70

    k

    14

    (L

    1

    ,L

    4

    )=0.65

    k

    23

    (L

    2

    ,L

    3

    )=0.65

    11

    9

    Primary Coil:

    R

    Alu

    =7.74

    R

    SubP

    =201

    C

    OXP

    =196fF

    Secondary Coil:

    R

    Alu

    =2.50

    R

    SubS

    =227

    C

    OXS

    =387fF

    13

    12

    5

    4

    8

    18

    Summary:

    L

    P

    =3.46nH

    L

    S

    =0.47nH

    k(L

    P

    ,L

    S

    )=0.85

    M=1.08nH

    Figure 4.3: Equivalent circuit of the transformer BL62S005.

    The values of the primary and secondary self inductance are

    LP = L1 + L2 + 2 k12qL1 L2 = 3:46 nH

    LS = L3 + L4 + 2 k34qL3 L4 = 0:47 nH

    The strength of magnetic coupling between primary and secondary side denotedby the k-factor is

  • CHAPTER 4. DESIGN EXAMPLES 49

    1 0.5 0 0.5 11

    0.8

    0.6

    0.4

    0.2

    0

    0.2

    0.4

    0.6

    0.8

    1

    Measurement Model

    S11

    S22

    2GHz

    4GHz

    50MHz

    6GHz

    50MHz

    Zo=50 Ohm

    Figure 4.4: Scattering parameters S11 and S22 of the transformer BL62S005.

    1 0.5 0 0.5 11

    0.8

    0.6

    0.4

    0.2

    0

    0.2

    0.4

    0.6

    0.8

    1

    2GHz

    4GHz50MHz

    6GHz

    S21polar

    Measurement Model

    Figure 4.5: Transmission S21 in polar-diagram of the transformer BL62S005.

  • CHAPTER 4. DESIGN EXAMPLES 50

    kPS =k13pL1 L3 + k14

    pL1 L4 + k23

    pL2 L3 + k24

    pL2 L4p

    LP LS= 0:85

    The series resistance of the conductors on the primary side isRAlu = 7:74 and onthe secondary side RAlu = 2:50 . Tue due the greater distance to the substratethe parasitic capacity of the primary winding COXP = 196 fF is only the halfcapacity compared to the secondary winding (COXS = 387 fF). The substrateresistances of both windings are in the same range of about 200 .

    The transformer is placed as a test structure on silicon (Fig. 3.16) to measurethe scattering parameters of the primary and secondary coil as well as of theprimary-to-secondary transmission. The center taps are left open. De-embeddingwas done with open- and short-test-structures.

    Fig. 4.4 shows the measured and simulated reflection S11 and S22 of the high cou-pling performance transformer BL62S005. The transformers S11 shows a nearlyshort circuit at low frequencies (50 MHz). The secondary winding is matchedto a driver stage with a low input impedance. Therefore, S22 shows a very lowimpedance over the whole frequency range. Measurement and model shows ex-cellent agreement up to 6 GHz.

    Fig. 4.5 shows the real and imaginary part of S21. The insertion loss is about9 dB at 1.9 GHz. The dierence between simulation and model is negligible.

    The S-parameter describes the electrical behavior of a monolithic transformercompletely. But, not only the scattering parameters must be observed. Also theZ-parameters, Y-parameters, k-factor and Q-factor give a fundamental insight tothe transformers characteristic. This parameters can be derived directly from theS-parameters.

    Especially Y 111 , which represents the input impedance of the secondary short-circuit transformer, becomes signicant importance because of the low inputimpedance of the driver stage and output stage (Fig. 1.1(a)). Fig. 4.6 showsthe real part of the measured and simulated Y 111 and Y

    122 . Fig. 4.7 shows the

    imaginary part. The conversion from S-Parameter to Y-Parameter is done with(3.49) standardized to Z0 = 50 . Simulation and measurement agrees well up to3 GHz.

    Fig. 4.8 shows primary inductance Lp and secondary Ls as a function of frequency.The self inductances are analyzed using

    LP = L1 + L2 + 2 k12qL1 L2 = Im (Z11) =! (4.1)

    LS = L3 + L4 + 2 k34qL3 L4 = Im (Z22) =! (4.2)

    Simulated and measured self resonance is at 4 GHz.

  • CHAPTER 4. DESIGN EXAMPLES 51

    0 1000 2000 3000 4000 50000

    5

    10

    15

    20

    25

    30

    35

    40

    Re(Y

    ) in

    Frequency in MHz

    Measurement Model

    Primary

    Secondary

    Y-1

    Figure 4.6: Real-part of input-impedance with secondary short-circuitt of thetransformer BL62S005.

    0 1000 2000 3000 4000 50000

    5

    10

    15

    20

    25

    30

    35

    Im(Y

    ) in

    Frequency in MHz

    Measurement Model

    Primary

    Secondary

    Y

    -1

    Figure 4.7: Imaginary-part of input-impedance with secondary short-circuit.

  • CHAPTER 4. DESIGN EXAMPLES 52

    Analyzing the coupling coecient as a function of frequency the relation

    M = k13qL1L3 + k14

    qL1L4 + k23

    qL2L3 + k24

    qL2L4 =

    s(Y 111 Z11)

    Z22!2

    (4.3)

    is useful. Then the coupling coecient can be written as

    k(LP ; LS) =M

    pLPLS

    =

    vuut (Y 111 Z11)Z22Im(Z11)Im(Z22)

    (4.4)

    Fig. 4.9 shows the coupling coecient versus frequency. A k-factor of 0.9 at1.9 GHz is a very high value for monolithic lumped planar transformers.

    The quality factor is analyzed using the following expressions

    Q = Im (Z11) =Re (Z11) (4.5)

    Q = ImY 111

    =Re

    Y 111

    (4.6)

    Fig. 4.10 shows the characteristic Q-factor of the primary and secondary wind-ing. Therefore, the output is left open. Typical Q-factor values of monolithictransformer windings are up to 8. Fig. 4.11 shows the quality factor of the trans-former with shorted output. This is an important case because of the low inputimpedance of the output-driver stage.

  • CHAPTER 4. DESIGN EXAMPLES 53

    0 1000 2000 3000 4000 500015

    10

    5

    0

    5

    10

    15

    Indu

    cta

    nce

    in n

    H

    Frequency in MHz

    Primary

    Secondary

    Measurement Model

    Figure 4.8: Self inductance of primary and secondary winding of the transformerBL62S005.

    0 1000 2000 3000 4000 50000

    0.2

    0.4

    0.6

    0.8

    1

    Coup

    ling

    Coef

    ficie

    nt k

    Frequency in MHz

    Port1 Port2 Measurement Model

    Figure 4.9: Coupling coecient k versus frequency of the transformer BL62S005.

  • CHAPTER 4. DESIGN EXAMPLES 54

    0 1000 2000 3000 4000 50006

    4

    2

    0

    2

    4

    6

    Quali

    ty fa

    ctor Q

    Frequency in MHz

    Measurement ModelQ

    Prima

    ry

    Secondary

    Figure 4.10: Quality factor with open at the secondary-side of the transformerBL62S005.

    0 1000 2000 3000 4000 50000

    0.2

    0.4

    0.6

    0.8

    1

    1.2

    1.4

    Quali

    ty Fa

    ctor Q

    Frequency in MHz

    Measurement Model

    Q

    Primary

    Second

    ary

    Figure 4.11: Quality factor with short at the second