Modeling and experimental results of short channelannular MOS transistors

Paula Lopez, Beatriz Blanco-FilgueiraDepartment of Electronics and Computer Science

University of Santiago de CompostelaCampus Vida, 15782-Santiago de Compostela, Spain

Email: p.lopez;beatriz.blanco@usc.es

Johann HauerFraunhofer Institut fuer Integrierte SchaltungenAm Wolfsmantel 33, 91058 Erlangen, Germany

Email: johann.hauer@iis.fraunhofer.de

Abstract— The reduction of the oxide thickness in advancedCMOS processes is one of the many advantages of technologydownscaling, as it favors the reduction of the threshold voltageshifts due to radiation-induced gate oxide trapped charge. Thisinherent radiation hardness of deep submicron processes can befurther exploited using gate-enclosed layout transistors with anannular design. In this paper we present a 2-D analytical I-Vmodel for short-channel annular devices based on the solution ofthe Poisson equation in cylindrical coordinates and a simplifiedthreshold voltage roll-off geometrical model.

I. INTRODUCTION

Standard CMOS processes have demonstrated robustness toirradiation triggered latch-up (SEL) and total ionizing dose(TID) effects, [1]. Current CMOS submicron processes aretherefore particularly attractive for the design of radiation-hardASICs even if the transition to future CMOS technology nodesmight need further investigation. Despite the demonstratedbenefits of a reduced oxide thickness, using standard transistortopologies, ionizing radiation may induce an inversion layerat the bird’s beak or at the shallow trench corner, givingrise to leakage current paths from the drain to the source.This can be remedied using enclosed-layout transistors (ELT),characterized by having an inner diffusion (drain or source)surrounded by the transistor gate and outer diffusion [2].

The previous statement has been widely confirmed withexperimental measurements [2]. Despite this, there is a sig-nificant lack of a thorough theoretical study of these devices.Preliminary studies were devoted to the extraction of the ef-fective W/L aspect ratio for ELT devices [3]. The first attemptto develop an electrical model was proposed in [4], were ananalytical expression for the drain current at low drain bias inthe case of long-channel devices was developed. Later, an ap-proximate numerical solution in the velocity saturation regionof an annular MOSFET was proposed based on a discretized1-D representation of the voltage along the channel [5]. In thiswork, we present the first 2-D analytical I-V model for short-channel annular ELT devices based on the direct solution ofthe Poisson equation in cylindrical coordinates. In addition, asimplified threshold voltage roll-off model has been developed.A test chip in a commercial 0.18µm CMOS standard processhas been fabricated and measured, showing good agreementwith the proposed analytical model.

Fig. 1. Layout of a conventional CMOS transistor (left) and an annularenclosed-layout transistor (right).

II. ANALYTICAL I-V MODEL

ELTs are characterized by having an inner diffusion (eitherdrain or source) surrounded by the gate and outer diffusion. Anexample of such a device is shown in Fig. 1 (right), depictingan annular ELT. In order to obtain an analytical I-V model,we will divide the channel in two regions: the linear region,extending from the source terminal to the saturation point, andthe saturation region that extends from the saturation pointto the drain terminal. The situation is summarized in Fig. 2,where the origin of coordinates is placed at the center of theinner diffusion, taken as the source in this case. In Fig. 2, r0 isthe radius of the inner diffusion and L represents the transistorchannel length extending from r0 to rL. The saturation point,rsat, divides the channel in the two regions. The situation inthe linear region of operation was considered in a previouspaper [6], while in Section II-A we will address the solutionof the 2D Poisson equation in the channel in saturation.

A. Saturation region

Due to the symmetry of the annular ELT we will usecylindrical coordinates as illustrated in Fig. 2 noting that thephysical parameters depend only on r and z and not on θ. Thelength of the saturation region is rld = rL− rsat. In Fig. 2, Ais the saturation point whereas C corresponds to an arbitrarypoint r along the channel surface between the saturation pointand the drain terminal, and B and D represent the depletionwidths at points A and C, respectively. In this analysis we willassume that the depletion region width is constant and equalto zj . Under high drain field conditions, the carrier velocitiesare assumed to increase linearly with the electric field at lowlevels and to saturate at velocity vsat when the electric field

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Fig. 2. Cross section of a MOS annular ELT.

exceeds Esat. Applying Gauss’ Law to the polygonal shapedefined by ABCD and assuming that the electric field at thebottom of the trapezoidal defined by BD is zero, we can write,

εSi

∫ zj

0

(Esat + E(r, z)) dz + εox

∫ r

rsat

Eoxdr =

− q∫ r

rsat

∫ zj

0

(NA +Nm) dz dr

(1)

where εSi and εox are the silicon and insulator permitivi-ties, NA the silicon doping concentration, Nm the mobilecharge term, E(r, z) the electric field perpendicular to the CDboundary and Eox the oxide electric field. In order to obtaina meaningful solution of (1) we use the saturation regimecondition to write, q

∫ zj0Nmdz = IDSAT

W vsat, where IDSAT is the

saturation drain current and W represents the transistor widthwhich, in the case of annular ELT transistors varies along thechannel as, W (r) = 2π r. However, if the saturation point isclose to the drain terminal and, particularly, for short channeldevices we can write W ≈ 2π rsat. We will also assume thatthe oxide electric field variation along the z axis is negligible.Under these assumptions and applying the ∇ operator to (1)we obtain,

∇E(r, z) +εoxεSi zj

Eox = −qNAεSi− IDSATw vsatεSi zj

. (2)

Taking into account that E = −∇V and expressing the oxidefield Eox as, Eox =

V ′GS−Vtox

, with V ′GS = VGS − VTH0,we obtain an alternative expression for (2) in cylindricalcoordinates as,

∂2V

∂r2+

1

r

∂V

∂r+∂2V

∂z2− a− bV = 0 (3)

where a = (1/l2)(V ′GS + l2qNA

εsi+ l2IDSAT

W vsatεSizj

), b = −1/l2

and l2 = εSitoxzj/εox. Using the transformation y = a/b+Vin (3) results in,

r2 ∂2y(r, z)

∂r2+r

∂y(r, z)

∂r+r2 ∂

2y(r, z)

∂z2−r2by(r, z) = 0. (4)

To solve this problem we will use of the variable separationmethod. We are looking for solutions of the form

y(r, z) = f(r)h(z). (5)

Substituting into (4) and dividing by h(z) we obtain,

r2 d2f(r)

dr2+r

df(r)

dr+r2f(r)

1

h(z)

d2h(z)

dz2−f(r)r2b = 0. (6)

The z dependence can be separated as

1

h

d2h

dz2= λ′ (7)

resulting in

r2 d2f(r)

dr2+ r

df(r)

dr+ r2f(r)λ′ − r2f(r)b = 0. (8)

If we define λ = λ′ − b we can rewrite (8) as,

r2 d2f(r)

dr2+ r

df(r)

dr+ λr2f(r) = 0. (9)

Comparing (9) with the general form of the Bessel equationit is then clear that (9) is the Bessel equation of order zero(m = 0) and its solution can be expressed as a linearcombination of order zero Bessel functions with argument√λr,

f(r) = c1J0

(√λr)

+ c2Y0

(√λr)

(10)

where J0

(√λr)

and Y0

(√λr)

are the Bessel functions oforder zero of the first and second kind respectively. Since|f(0) < ∞|, this condition of singularity on the originforces to c2 = 0 because Yr

(√λr)

, the Bessel functionof the second kind, has a logarithmic singularity at r=0. Thecondition f(r0) = 0 determines the eigenvalues,

J0

(√λr0

)= 0. (11)

From (11) it follows that√λr0 must be a zero of the Bessel

function J0(z). As the J0(z) function has an infinite numberof zeros, we denote the n-th zero as z0n. Then,

√λr0 = z0n, that is λ0n =

(z0n

r0

)2

(12)

Now we will consider the solution of the equation with thez dependence in (7). It has been shown that the solution canbe written as,

h(z) = c3e√λ′z + c4e

−√λ′z. (13)

Undoing the transformation, V = y − a/b, the solution ofthe 2-D problem can be expressed as,

V (r, z) =

∞∑n=1

(C1ne√λ′0nz + C2ne

−√λ′0nz)J0(

√λ0nr)−

a

b

(14)To determine C1n and C2n we apply the following boundaryconditions,

V (rsat, 0) = VDSAT (15)

V (rsat, zj) = 0 (16)

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From (15) and (16) we can calculate C1n and C2n as thecoefficients of the above Fourier-Bessel series,

C1n + C2n =

∫ rsat

0(VDSAT + a

b )J0(√λ0nrsat)r dr∫ rsat

0J2

0 (√λ0nrsat)rdr

(17)

Analogously from (16),

C1ne√λ′0nzj + C2ne

−√λ′0nzj =

∫ rsat

0abJ0(√λ0nrsat)r dr∫ rsat

0J2

0 (√λ0nrsat)r dr

(18)To perform these integrations the following Bessel functionsproperties can be used,∫

J0(√λr)rdr = rJ1(

√λr) (19)∫

J20 (√λr)rdr =

r2

2(J2

0 (√λr) + J2

1 (√λr)) (20)

From here it is possible to calculate C1n and C2n and hencethe complete solution to the problem as,

C1n =(VDSAT +

a

b

)K2n − C2n (21)

C2n = K2n

VDSAT + ab (1− e−

√λ0n zj )

1− e−2√λ′0n zj

(22)

being,

K2n = 2J1

(√λ0n rsat

)rsat

(J2

0

(√λ0n rsat

)+ J2

1

(√λ0n rsat

)) (23)

III. ANALYSIS OF SHORT-CHANNEL EFFECTS

It is possible to obtain a quantitative first-order expressionof the threshold voltage roll-off due to SCE, ∆VT,SCE usinga simplified geometric argumentation:

4VT,SCE = − 1

Cox(QBS −QBL) =

QBLCox

(1− QBS

QBL

)(24)

where QBL and QBS are the charge densities in the depletionregion for long and short channel devices respectively, andCox is the total oxide capacitance per unit area. Under theassumption of VD small or zero we have W ∼= WT in allpoints under the central part of the gate, being WT the widthof the depletion region when the transistor is polarized at theinversion-depletion transition point. The charge density canbe calculated as Q = −qN ΩG

AG, being N the total amount of

donor/aceptor atoms per cm3, ΩG the volume of the depletionregion and AG the area of the gate.

For a long-channel device, short-channel effects can be ne-glected and the charge density, QBL, can be written as QBL =−qNWT . For short-channel annular transistors, however, SCEmust be taken into account. The situation is summarized inFig. 3. The outer and inner diffusions corresponding to thedrain and source penetrate into the volume under the gateeffectively reducing the size of the depletion region. We willassume that the penetration is uniform in all directions andequal to d. Taking this into account, the effective volume underthe gate, ΩG can be calculated as ΩG = ΩO −ΩI , where ΩO

Fig. 3. Lateral penetration under the gate.

is the volume of the truncated cone defined by the circularareas of radius rL and rL − d, shown in a lighter shade ofgrey in Fig. 3, and ΩI the one defined by r0 and r0 + d,depicted in dark grey in Fig. 3. For ΩO we have, ΩO =πWT

3

(3 r2

L − 3 rL d+ d2). ΩI can be calculated analogously

resulting in, ΩG = n tan(π/n)WT (2ap,d+Lgate)(Lgate−d).Thus, the charge density in the depletion region for the short-channel annular transistor, QBS , is given by,

QBS = −qNWT

(1− (rL + r0) d

r2L − r2

0

)(25)

and,

4VT,SCE =−qNWT

Cox

d

L(26)

Making geometrical considerations it is possible to extractan expression of d as a function of process parameters. Asseen in Fig. 3, both truncated cones have a slant height, g,of g =

√h2 + d2, where h is the height. We note that g =

rj + WS , where rj is the junction depth and WS the widthof the depletion layer under the source/drain of the transistor.Through elemental mathematical calculation we write, d =√r2j +W 2

S + 2 rjWS −W 2T . Substituting in (26) we obtain

the following expression for the threshold voltage variationdue to SCE,

4VT,SCE =−qNWT

Cox

√r2j +W 2

S + 2 rjWS −W 2T

L(27)

As can be noted, (27) is a function of only process-relatedgeometrical parameters. Another important conclusion that canbe drawn from this first-order model of the VT variation is thatas the thin-film thickness, tox = εox/Cox, is reduced, the SCEbecomes smaller since the controllability of the gate over theactive channel region is stronger and the source/drain has lessinfluence on the channel.

For the sake of comparison we show in Fig. 4 the cor-responding 4VT,SCE for annular ELT, given by (27), andstandard topologies, obtained through a similar geometricalanalysis, with WS = 0.9 ∗ WT and for typical values ofthe MOS BSIM4.0 model: Tox = 3nm, rj = 0.15µm,WT = 0.155µm and N = 2× 1016atom/cm3. As seen, bothtopologies are similarly affected by short-channel effects.

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0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.55

10

15

20

25

30

35

40

45

50

55

L(µ m)

∆ V

T,S

CE (

mV

)

Standard transistor

Annular transistor

Fig. 4. Modeled threshold voltage variation due to short-channel effects forannular and standard transistors.

Fig. 5. Comparison of the simulated and experimental I-V curves ofoctogonal ELTs with L = 0.2µm and [W/L]eff = 15.

IV. EXPERIMENTAL RESULTS

A test chip in a standard CMOS 0.18µm process wasfabricated. As technical limitations do not permit the fab-rication of annular devices, polygonal structures with eightsides (n = 8) were fabricated and used for comparison. Thechip consists of an array of 72 NMOS transistors of differenttypes and different [W/L]eff ratios. All the transistors have thebulk connected to ground, and independent pads were used toaccess each transistor’s terminals using Ground-Signal-Groundprobes. The drain and gate-to-source voltages were varied from0 to 1.8 V and 1.6 V respectively. Three different chips weremeasured and the average values were considered.

Fig. 5 shows the experimentally measured I-V curves ofoctogonal ELTs with L = 0.2µm and [W/L]eff = 15compared with simulated data using the BSIM3v31 model forstandard transistors and that given by the proposed model. Asrld cannot be directly extracted from measurement data, weestimated it for each value of VGS by comparing the surfacechannel potential as predicted from the model given by (14)with device simulation results using Sentaurus from Synopsysuntil obtaining the best fit. Once rld has been obtained, the

Fig. 6. Transfer characteristics with L = 0.2µm and [W/L]eff = 30.

current in the saturation region has been approximated by,IDS = IDSAT

1− rldLeq

, being IDSAT the drain current given by the

expression in the linear region with VDS replaced by VDSATand Leq = L(1 + VDSAT /LEsat). The value of Esat wasobtained from (14) at rsat = rL − rld. The resulting I-Vcurves are shown in Fig. 5. As can be seen, in the linear regionboth the BSIM and annular models follow rather accuratelythe experimental data. In the saturation region, however, theBSIM model drifts significantly from the measured data, whilethe correction introduced by the annular model results in abetter fit. The measured transfer characteristics of an octogonaldevice compared to a standard transistor are shown in Fig. 6.

V. CONCLUSIONS

We have presented a 2-D analytical solution in cylindri-cal coordinates for radiation-hard short-channel annular ELTdevices. Theoretical results have been validated with experi-mental data in a standard CMOS 0.18µm process.

ACKNOWLEDGMENT

This work has been funded by the Spanish Ministry of Sci-ence and Education under project TEC 2009-12686 and by theXunta de Galicia under the grant number 10PXIB206037PR.

REFERENCES

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[3] P. Grignoux and R.L. Geiger, “Modeling of MOS transistors withnonrectangular-gate geometries.,” IEEE Trans. on Electron Devices, vol.29, no. 8, pp. 1261–1268, 1982.

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