Near-Field Coupling Integration Technology

40
1 of 40 Tadahiro Kuroda 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016) ISSCC2010, pp.440-441 128-Die Stacking Tadahiro Kuroda 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016) Near-Field Coupling Integration Technology Tadahiro Kuroda Keio University, Japan IEEE Fellow August 31, 2016

Transcript of Near-Field Coupling Integration Technology

Page 1: Near-Field Coupling Integration Technology

1 of 40Tadahiro Kuroda 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)

ISSCC2010, pp.440-441

128-Die Stacking

Tadahiro Kuroda 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2016)

Near-Field Coupling Integration Technology

Tadahiro Kuroda Keio University, Japan

IEEE Fellow

August 31, 2016

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Challenge to “Tyranny of Numbers”

Invention of IC driven by “Tyranny of Numbers”: Challenges implied by large number of components & interconnects.

We face the same challenge again with end of Moore’s Law and rise of IoT/big data.

Cray-31993

Mass of wires, cables, and connectors

K2011

200 thousand cables, 1,000Km long

ENIAC 1946

17 thousand vacuum tubes,5 million hand-soldered connections

Invention of transistor (1948), IC (1958) End of Moore’s LawIEEE Spectrum

From“System on a Chip”

to“System on Chips”

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Proposal: Near-Field Coupling

Replace mechanical connections (wires, solders, connectors) by electrical ones (wireless by near-field coupling).

Near-field coupling provides with invisible wires.

Far Field (Radiative)

Near Field (Reactive)

Near Field : x< /2x: distance, : wave length

VRX 1/x3 (-60dB/dec)

WiFi, Cellular

Smart cards used in place of train ticket, door key

Top view (dotted circles: coils)Cross section

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Near-Field Coupling Integration Technology

ThruChip Interface (TCI)3D integration of chips for high performance

Transmission Line Coupler (TLC)LEGO-type packaging of modules

for high function

HH

E

SoC chipsMemory chips

Processor boards

Peripheral boards(storage and sensor)

JST ACCEL Project (2015-2019):Data Centric Computer(Ultra low power mobile computer in the era of IoT)

Proof of Concept: 100GFLOPS/W (in 2019)Milestone: 512GB/s 8GB DRAM (in 2017)

100GFLOPS/W512GB/s

Proposed solution to “connections in very large system”

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Outline

Near-Field Coupling Integration Technology

Transmission Line Coupler (TLC)

ThruChip Interface (TCI)

Challenges Highly Doped Silicon Vias (HDSV) TCI_2.9D/2.5D/2.0D

ACCEL 100GFLOPS/W Computer and 512GB/s DRAM

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Transmission Line Coupler (TLC)

PCB, FPC

PCB, FPCCoupling

Transmission Line Coupler (TLC)

ElectricField

Magnetic Field 2-2+

1+ 1-

Termination

PCB, FPC

Crosstalk

TL TL

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EH

Transmission Line Coupler (TLC)

distributed system

Electromagnetic coupling characteristic impedance is controlled signal reflection can be suppressed Transceiver: digital CMOS circuits Contactless connector Modular design

http://www.kuroda.elec.keio.ac.jp/research/video/

ISSCC2011, pp.492-493

L

W

Cou

plin

g [

dB]

0

-10

-20

-30

-40

-50

-600 20161284Frequency [GHz]

Bandwidth : 8GHz (L=6mm), 12GHz (L=4mm)

Distance (d):1mm (W=0.5mm), 2mm (W=1mm)

d

Video 1 Video 2

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Applications of TLC

SatelliteLight: 60%

Vibration immunity(contactless connection)ISSCC2015 , pp.434-435

SmartphoneHigh-speed :5x(6Gb/s)

Low-energy :1/24(6pJ/b)Modular design

(electrical connection)ISSCC2015 , pp.176-177

SD

Memory CardHigh-speed:50x(12Gb/s)

Low-power:1/500Water proof

(pad-less, sealed)ISSCC2013 , pp.214-215

DisplayHigh-speed:10x(6Gb/s)

Low-energy:1/10(16pJ/b)Thin

(no mechanical structure)ISSCC2013, pp.200-201

LCD

DIMMHigh speed:5x(12.5Gb/s)

Multi-drop bus (impedance controlled)ISSCC2012 , pp.52-53

In-vehicle LANLight: 30%

Strong EMC immunity(wide band)

ISSCC2014 , pp.496-497

ECU ECU ECU

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Display/Camera Module High speed, Low power, Low profile

ISSCC2013, pp.200-201

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Modular Design

http://www.kuroda.elec.keio.ac.jp/research/video/ISSCC2015, pp.176-177Video 3

6Gb/s received data

4mm

1.5mm TLC

Host board

Module board

Module board

LCDTLC

5mm

TLC

Module

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Radiation Tolerance (EMC)

T-TLC

EM probe

Robot arm

1) EMI: Electromagnetic InterferenceGPS is not affected at a separation of 10mm from TLC

2) EMS: Electromagnetic SusceptibilityTLC is not affected at a separation of 2mm from LTE/WiFi

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Vibration Tolerance

No single bit failure during the period of launch of small locket

TLC

Vibration [Grms]

BE

R

0

10-7

10-9

4 8 12 16 20

10-5

10-3

10-11

PRBS27-1@100Mb/s

No error bits during 60 seconds

Conventional mechanical connector

TLC1/246x

ISSCC2015 , pp.434-435

Japan Aerospace eXploration Agency

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Other Possibilities

Touch and GoHot swap

InRotate(2D)

Out Rotate(3D)

Slide (1D)In

Out

door, seat wheel, joint …

DC isolation

Module1

Module2

Video 4

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Outline

Near-Field Coupling Integration Technology

Transmission Line Coupler (TLC)

ThruChip Interface (TCI)

Challenges Highly Doped Silicon Vias (HDSV) TCI_2.9D/2.5D/2.0D

ACCEL 100GFLOPS/W Computer and 512GB/s DRAM

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ThruChip Interface (TCI)

20m x 10m

15m x 10mTx

Rx65nm CMOS

Coil: multi-layer standard wires Logic interconnections go across coil Coil can be placed anywhere (above SRAM) Digital CMOS circuit solution Eventually zero cost

Txda

ta

Time

I TV

RRxd

ataRxdata

TxdataTxdata

Rxdata

Inductive coupling data communication through chips Transceiver: digital CMOS circuits

dITdtVR=k LTLR

S=1IT

ISSCC2004, pp.142-143

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Performance of TCI

11Gb/s/ch(0.18m)

ISSCC2008

8Tb/s(1000ch in 2.5mm2)

ISSCC2010

30Gb/s/ch(65nm)

A-SSCC2010

Aggregated data rate is raisedby increasing number of channels.

High Speed

128-die stackingISSCC2010

64-die stackingISSCC2009

High Integration

0.14pJ/b(90nm)

ISSCC2007

0.01pJ/b(65nm)

JSSC2011

ESD protection device (>0.5pJ/b)can be eliminated.

Low Power

TCI TSV

Bump

Low HeightLow Thermal Resistance

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TCI Coil Design

0 25 50 75 100 125 150Communication Distance, Z [m]

0

10

20

90

30

80

Usa

ble

Coi

l ban

dwid

th [

Gb/

s]U

sabl

e ci

rcui

t ba

ndw

idth

dep

ends

on

devi

ce

40

50

60

70

Coil Diameter D = Zdistance x 3

3-die stackingD=60m

Z=20m

9 die stackingD=240m

Z=80mD=200m

D=300mD=400m

D=500m

D=100m

Usable BW of 22 Gbps

80 Gbps

Data rate goes up dramatically with smaller Z

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TCI Layout

Coils of 100um size areformed byM9 and M10 for TX,M7 and M8 for RX, with power/signal lines crossing

Accommodate circuits under the coil

Similar to typical CMOS layout

Coils are overlappedand accessed by PDMAto avoid crosstalk

at phase 1at phase 2at phase 3at phase 4

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TSV vs. TCI

OSAT*: Outsource Assembly and Test, KOZ**: Keep Out Zone

TSV TCI

Wafer TechnologyPackage Technology

MiniaturizationYield

Eco-systemAdditional Cost

Placement

Speed

ESD Protection

Power Dissipation

Additional steps neededOSAT* involved

DifficultLow, difficult to improve

New model needed> 40%

Dedicated area w/KOZ**

< 512 GB/s

Needed

High

Standard CMOSConventional

EasyHigh (~100%)

Conventional modelA few %

Unconstrained

> 512 GB/s

No need

Low

Solution Mechanical in package Electrical on wafer

micro bumptransistor Magnetic Field

transistor

KOZ**

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Speed:2xPower/Area:1x

Size:1/2xVoltage:1/2x

Data Rate/Area:8xEnergy/bit:1/8x

Thickness:1/2x

3D Scaling Scenario

evaluation value dimension scaling

Device size [x] 1/

Voltage [V] 1/

Current [I] 1/

Capacitance [C]~[xx/x] 1/

Delay time [t]~[CV/I] 1/

Chip thickness [z] 1/

Coil size [D] 1/

Coil turn number [n] 0.8

Inductance [L]~[n2D1.6]

Magnetic coupling [k]~[z/D]

Received signal [vR]~[kL(I/t)]

Data rate / channel [1/t]

Channel / area [1/D2] 2

Data rate / area [1/tD2] 2

Energy / bit [IVt] 1/3Constant Magnetic Field Scaling

Constant Electric Field Scaling

Suppose 8mm-square 4 chips are stacked. When each die is thinned from 50um to 10um, number of on-chip coils are increased from 700 to 17,500, yielding 25x speed improvement.

Cost/Performance will be improved by 3D scaling scenario. Field Effect Transistor (Moore’s Law)

Inductive Coupling Link (3D Scaling Law)

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Performance of TCI in 7nm CMOS

SPICE simulation performed with Predictive Technology Model (http://ptm.asu.edu/)

Chip thickness 50 m 25 m

Coil size 150 m 75 m

Data rate per coil 50 Gb/s/coil 64 Gb/s/coil

Area efficiency 2 Tb/s/mm2 11 Tb/s/mm2

Power efficiency 30 fJ/bit 25 fJ/bit

Aggregate data rate when using 8mm x 1mm Si area

18 Tb/s 91 Tb/s

Power dissipationwhen using 8mm x 1mm Si area

0.5 W 2.2 W

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3-D NoC by TCI

JSPS project led by Prof. Amano, Prof. Matsutani A Study on Building-Block Computing Systems using TCI Inter-chip wireless inductive coupling techniques, self-

organized network-on-chips, fault tolerant architectures, optimized power control, and a flexible operating system with virtualization facilities are investigated

http://www.am.ics.keio.ac.jp/kaken_s/

3-D NoC with TCI will be presented at IEEE A-SSCC2016 Collision detection scheme by sensing magnetic field 44-bit packet transceiver of PER < 10-9

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Outline

Near-Field Coupling Integration Technology

Transmission Line Coupler (TLC)

ThruChip Interface (TCI)

Challenges Highly Doped Silicon Vias (HDSV) TCI_2.9D/2.5D/2.0D

ACCEL 100GFLOPS/W Computer and 512GB/s DRAM

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Remaining Challenges

Proof with DRAM Influence of magnetic field to DRAM Influence of DRAM (plate, cylinder, power mesh) to magnetic field

Power Supply New way of power delivery to create synergy with TCI is expected. Highly Doped Silicon Vias (HDSV) is proposed.

Idea is received highly in IEDM but needs proof.

Heat Removal Heat keeps from die stacking. Inductive coupling for horizontal link (TCI_2.5D/2D) is developed.

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Highly Doped Silicon Vias (HDSV)

A deeper and more highly doped well is used to make a low resistance HDSV. The HDSV on one die and electrodes on the next die are connected by pressure

from a Room-Temperature Wafer Level Bonding machine to create larger stacks. TCAD indicates resistance < 3m when substrate <5um,

dose: 1x1016 cm-2, implant: 200 keV, annealing: 50h, 1050°C. 0.7 mm2 net area is required (can be divided), good only for power delivery. Low cost process by implants

IEDM2014, 18.6.

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Memory Stacking with TCI and HDSV

# stacked die Die pitch

Total height Die area Data link

Power delivery IO energy/bit

IO data rate/area

spacer~1000 m

16 50

~10001x

wire bond wire bond

1x

TCI, HDSV

~80 m

165

~80~0.9xTCI

HDSV< 1/400x

wire bondNAND Stacking

~275 mDRAM die

DRAM die

DRAM die

DRAM die

Base logic die~40 m

555

~2751x

TSV TSV 1x

~ 200 Gb/s/mm2

58

~40~0.9xTCI

HDSV< 1/10x

~ 860 Gb/s/mm2

DRAM StackingTCI, HDSVTSV

Hot Chips 2014

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128GB/s HBM Case Study

TSV6.91 mm

5.1

mm

TSV (

dedi

cate

d)0.

907

mm

SK Hynix, ISSCC20141Gb/s/TSV*1024 TSV=128 GB/s

TCI, HDSV

TCI

(ded

icat

ed)

0.25

0 m

m 6.91 mm

Suppose chip thickness of 10um, stacking of 5 chips.Communication distance is 40um, coil diameter is 100um. 8 Gb/s/coil*16 coil *8 = 128GB/s

7.5 coils x 100 = 750

2.5 coils250

CLK 1

CLK3

TCI reduced chip size by 13% than TSV.

Hot Chips 2014

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TCI Can Use Whole Chip Area

TSVneed to be placed

away from active area

micro bumptransistor

Magnetic Field

transistor

TCIcan be placed in active area

Memory Area

I/O Area128GB/s 256GB/s 512GB/s …

Area +18%

1024 TSVImpractical for further addition of dedicated area for TSV

Area +36%

2048 TSV

Area +3%

208 coil

Area +6%

416 coil

With addition of one metal layer, TCI can be placed in memory area (need proof)

5096 coil …

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TCI_2.9D, 2.5D, 2.0D for Heat Removal

(a) TCI_2.9D packaging.

(b) TCI_2.5D packaging with small Si interposer.

(c) TCI_2.0D packaging.

Conventional 2.5D packaging by Si interposer with bumps and TSVs.

Package substrateC4 bumps

ChipChip Coils Coils

Package substrateC4 bumps

ChipChip

CoilsBonding wires

Coils

TCI can release mechanical constraints such as stress

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Outline

Near-Field Coupling Integration Technology

Transmission Line Coupler (TLC)

ThruChip Interface (TCI)

Challenges Highly Doped Silicon Vias (HDSV) TCI_2.9D/2.5D/2.0D

ACCEL 100GFLOPS/W Computer and 512GB/s DRAM

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JST ACCEL Project (2015-2019)

Goal Mobile supercomputer with world's best power efficiency of

100GFLOPS/W (2019) Milestone 512GB/s 8GB 8-Stacked DRAM (2017)

Technology 3D Integration using Near-Field Coupling Integration Technology

Further Challenges AI computer equipped with both a left brain and a right brain to

explore a new paradigm of information processing Left brain employing stored program system by 3D Integration Right brain employing virtual hard-wired logic system by 4D

Integration (3D + DRP with DNN and DL; not mentioned today)

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512GB/s 8GB TCI DRAM

64

128

256

512

1k

2k

4k

8k

16k

10

20

40

80

160

320

640

1280

200 400 800 1600 3200 6400 12800

Agg

rega

ted

Ban

dwid

th

Data rate per pin

Target

HMC (Micron)HBM (JEDEC)

DDR3/DDR4 (DIMM)16~24 GB/s64 DQ, 2~3 Gbps/pin

128~256 GB/s1024 DQ, 1~2 Gbps/pin

160~240 GB/s128 DQ, 10~15 Gbps/pin

512~768 GB/s1024 DQ, 4~6 Gbps/pin

3x faster than developing TSV stacked DRAM

32x faster than conventional DRAM module

TCI DRAM

TSV

DIMM

TCI

[Mb/s/pin]

[GB/s]

Target of TCI DRAM is 3x faster than HBM and HMC.

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Bottom Si 50~100um

10 layer ~100um~200um

SoCTCI (SoC-DRAM)

Air GapHeat insulator

Stacked DRAM

Flip chip substrate

Solder bump

BGA pitch ~ 0.4mmTCI(DRAM bus)

HDSV(Vdd/GND)

Active InterposerDRAM 8Gb * 9 chips

Thickness150~200um SoC

TCI (SoC-DRAM)~1mm

Stacked DRAM

Flip chip substrate

BGA height ~ 0.2mm

> 5000 coils in DRAM memory area to form bus link

Edge of DRAM slip into SoC under its eavesto form SoC-DRAM serial link

HDSV(Vdd/GND)

50~0um

100GFLOPS/W Computer

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Summary

Near-Field Coupling Integration Technology challenges to “Tyranny of Numbers” in post-Moore.

Transmission Line Coupler (TLC) using electromagnetic coupling enables contactless connector for modular design.

ThruChip Interface (TCI) using inductive coupling enables die stacking for 3D integration.

Challenges Proof with DRAM Highly Doped Silicon Vias (HDSV) for power supply TCI_2.9D/2.5D/2.0D for heat removal

ACCEL aims for 512GB/s DRAM (in 2017) and 100GFLOPS/W computer (in 2019).

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Questions

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TCI[01] ISSCC 2004, pp.142-143.[02] Symp. VLSI Circuits 2004, pp. 246-249.[03] CICC 2004, pp.99-102.[04] ISSCC 2005, pp.264-265.[05] ISSCC 2006, pp.424-425.[06] ESSCIRC 2006, pp.3-6.[07] ISSCC 2007, pp.264-265.[08] A-SSCC 2007, pp.131-134.[09] ISSCC 2008, pp.298-299.[10] ISSCC 2009, pp.244-245.[11] ISSCC 2009, pp.480-481.[12] Symp. on VLSI Circuits 2009, pp. 256-257.[13] Symp. on VLSI Circuits 2009, pp. 94-95.[14] Symp. on VLSI Circuits 2009, pp. 92-93.[15] CICC 2009, pp. 449-452.[16] A-SSCC 2009, pp.305-308. [17] A-SSCC 2009, pp.301-304.[18] ISSCC 2010, pp.436-437.[19] ISSCC 2010, pp.440-441.[20] ISSCC 2010, ES3.[21] Symp. on VLSI Circuits 2010, pp. 201-202.[22] A-SSCC 2010, pp.81-84.[23] IEDM 2010, p.17.1.1.[24] ISSCC 2011, pp.490-491.[25] ISSCC 2013, pp. 258-259.[26] Hot Chips 2014.

Key ReferencesTLC[01] ISSCC 2007, pp.266-267.[02] CICC 2007, pp.13-2007.[03] A-SSCC 2008, pp.113-116.[04] ISSCC 2009, pp.470-472. [05] Symp. on VLSI Circuits 2009, pp. 26-27.[06] ISSCC 2010, pp.264-265.[07] ISSCC 2011, pp. 492-493.[08] A-SSCC 2011, pp. 145-148.[09] ISSCC 2012, pp. 52-53.[10] CICC 2012, pp. 7.9.1-7.9.4.[11] ISSCC 2013, pp. 214-215.[12] ISSCC 2013, pp. 200-201.[13] ISSCC 2014, pp. 496-497.[14] ISSCC 2015, pp. 176-177.[15] ISSCC 2015, pp. 434-435.[16] Symp. on VLSI Circuits 2015, pp. C128-129.