Spectral PLL Built-In Self-Test for Integrated Cellular ... · Spectral PLL Built-In Self-Test for...

Spectral PLL Built-In Self-Test forIntegrated Cellular Transmitters

Spektraler PLL-Selbsttest für integrierteMobilfunktransmitter

Der technischen Fakultätder Universität Erlangen-Nürnberg

zur Erlangung des akademischen Grades

DOKTOR-INGENIEUR

vorgelegt von

Christian Münker

Erlangen - 2010

ii

Als Dissertation genehmigt vonder Technischen Fakultät der

Universität Erlangen-Nürnberg

Tag der Einreichung: 30. Oktober 2009

Tag der Promotion: 10. März 2010

Dekan: Prof. Dr.-Ing. Reinhard German

Berichterstatter: Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel

Prof. Dr.-Ing. Heinrich Klar

Christian Münker March 10, 2010

iii

Die Geburt unseres Sohns Robin, unsere Heirat, zwei Jobwechsel,zwei Umzüge, ein Hauskauf ... ohne die Hilfe meiner geliebten FrauSylvia Englert und unserer Eltern hätte ich es nie geschafft, meineArbeit in dieser turbulenten Zeit abzuschließen.

Dafür danke ich Euch von Herzen.

Spectral PLL Built-In Self-Test for Integrated Cellular Transmitters

iv

Acknowledgments

First of all, I’d like to thank my two supervisors Prof. Dr. Dr. Robert Weigel andProf. Dr. Heinrich Klar for their kind support and motivation over all the yearsin spite of geographical distance.

My interest in PLL topics was triggered by "old PLL rabbit" Edmund Götz. Healso played a vital role in our weekly discussions with Markus Scholz, BurkhardNeurauter and Günter Märzinger at Infineon Technologies revolving aroundΣ∆PLLs and self-calibration strategies. These discussions sparked-off greatchips, several patents and, in the end, this thesis. Markus Scholz also designedthe excellent multi-modulus divider block that found its way from theΣ∆PLLinto theΣ∆FD and shared countless mugs of coffee with me. Manufacturing andevaluation of the test-chips was made possible by the kind support of InfineonTechnologies.

Frank Demmerle was especially helpful for long discussionson test and self-testissues, motivation and reading the first horrible versions.Guido Retz, LudgerSchneider-Störmann and Stefanie Marek (www.schreibkonzepte.de ) gaveme valuable ideas for the final structure of this work.

Julien Layole’s contributions on PLL modeling using SystemC gave me impor-tant insights into modeling issues and spectral estimation.

Parts of this work were funded by the MEDEA+ project A107 "4G-Radio" andthe BMBF project 01M3071 "DETAILS".

This work was typeset using the MiKTEX - implementation of LATEX with theTeXnicCenter user interface and the fantastic GhostView / Ghostscript package.Figures were created with XFig / WinFig and references were administrated withthe combination of BIBTEX and JabRef. Data was kept secure and up-to-datebetween many different computers and harddisks by Unison.

A big "THANK YOU" to all of you!!


www.schreibkonzepte.de

http://miktex.org/

http://www.texniccenter.org

http://jabref.sourceforge.net

http://www.cis.upenn.edu/~bcpierce/unison/index.html

KURZFASSUNG v

Kurzfassung

Bis vor wenigen Jahren war die Komplexität von HF-ICs so gering, dass test-unterstützende Designmaßnahmen (Design-for-Test, DfT) oder gar ein Selbst-test (Built-In Self-Test, BIST) unwirtschaftlich gewesenwären. Da man HF-Parameter zudem nur schwer mit ausreichender Genauigkeit auf dem Chipmessen konnte, wurde der Produktionstest auf speziellen automatischen HF-Testsystemen (Automated Test Equipment, ATE) durchgeführt. Der allgemeineTrend der letzten Jahre hin zu drahtlosen Anwendungen schaffte einen Mas-senmarkt für komplexe HF-Systems-On-Chip (SOC) mit rapidesinkenden Pro-duktmargen. Wie zuvor bei digitalen ICs wurde der Produktionstest auch fürHF-SOCs zum Flaschenhals; DfT und BIST wurden zur ökonomischen Notwen-digkeit.

Sigma-Delta-modulierte Fractional-N Phase-Locked Loops (Σ∆PLLs) gehörenzu den Schlüsselkomponenten in heutigen HF-SOCs; sie erzeugen und modu-lieren rauscharme HF-Trägersignale mit kurzer Einschwingzeit. Die enge Ver-zahnung von analogen und digitalen Blöcken inΣ∆PLLs und deren vollständigeKapselung im SOC erschwert jedoch deren Produktionstest und damit den Testdes gesamten HF-SOCs.

Da erprobte digitale DfT-Methoden ungeeignet sind, um die vielfältigen HF-Spezifikationen abzudecken, wird ein neuer Ansatz für den autonomen, spezifi-kationsgetriebenen Test vonΣ∆PLLs in SOCs benötigt. HF-Geräte müssen stren-ge Standards erfüllen, die ganz überwiegend in der Frequenzebene spezifiziertsind, wie z.B. die Sendebandbreite. In dieser Arbeit wurde daher ein spektralerPLL BIST (SP-BIST) entwickelt, um spektrale Eigenschaftenvon integriertenΣ∆PLLs auf dem Chip ohne externe Messgeräte zu ermitteln und digital auszu-geben. Der SP-BIST beinhaltet einen Stimulusgenerator zurModulation der PLLund einen Block, der die HF-Antwort der PLL spektral bewertet.

Es musste zunächst eine Simulationsmethodik entwickelt werden, um das Zu-sammenspiel der RF- und Digitalblöcke vonΣ∆PLL und SP-BIST im Frequenz-und Zeitbereich vorherzusagen. Unter Verwendung eines Standard-VHDL-Simulators konnten damit u.a. die PLL-Schleifenbandbreite und das Phasen-rauschen bei 4 GHz mit einem Noise Floor von -200 dBc/Hz simuliert werden.

Der digitale Stimulusgenerator erzeugt Zweitonsignale mit einer Frequenz von16 . . . 180 kHz und einem Spurious-Free Dynamic Range (SFDR) von 60 dB.Die PLL wird digital über das Fractional-Frequenzwort moduliert. Das Zwei-tonsignal steht sowohl als Sigma-Delta-modulierter Bitstrom zur Verfügung alsauch in paralleler Form und ist damit ein vielseitiges Testsignal auch für andere


vi KURZFASSUNG

analoge und mixed-signal-Blöcke auf dem Chip.

Das HF-Signal der PLL wird mit einem digitalen Sigma-Delta-Frequenz-Dis-kriminator (Σ∆FD) gleichzeitig demoduliert und digitalisiert. Der demodulier-te Bitstrom wird in einem Multiraten-Bandpassfilter vierter Ordnung mit einerBandbreite von 0,8 kHz und einem digitalen Hüllkurvendetektor spektral bewer-tet. Dabei wird ein SFDR von 45 dB erzielt, der Rauschboden liegt beiL =−80 dBc/Hz. Die Mittenfrequenz des Bandpasses wird mit einemeinzigen Para-meter in Schritten von 300 Hz im Bereich von 10 . . . 200 kHz abgestimmt. Derniedrige Ausschnittsverlust des Filters verursacht einenreproduzierbaren Ampli-tudenfehler von weniger als 0.5 dB für Einzeltöne. Dieser und andere systema-tische Fehler können leicht mit einer Kalibrationsmessungentfernt werden. Dieresultierende Standardabweichung des PLL-Frequenzgangs, gemessen mit demOn-Chip Stimulusgenerator, ist 0.05 dB.

Die Messdauer beträgt 3 ms pro Frequenzpunkt, Messwerte werden über einminimales Testinterface als statisches Wort ausgegeben und ermöglichen damitauch einen RF-Test der PLL auf Wafer Level.

Mit der Einschränkung des relativ geringen SFDR können auchdas In-Band Pha-senrauschen und die Modulationsmaske bewertet werden. Diese On-Chip Extrak-tion der spektralen Parameter stellt eine effiziente Kompression der analogen Da-ten dar und kann direkt mit den Spezifikationen im Frequenzbereich verglichenwerden. Durch Messung der PLL-Bandbreite und des Spektrumskönnen funk-tionale und parametrische Ausfälle ermittelt werden.

Stimulusgenerator und Bandpassfilter basieren auf verlustlosen Resonatoren, dieguten Rauschabstand und Stabilität auch bei kurzen Wortbreiten garantieren. Re-sonanzfrequenz bzw. Bandbreite werden mit einem Parametermit annähernd li-nearer Abhängigkeit eingestellt. Durch diese einfache Beziehung eignet sich dasVerfahren auch für einen Selbstabgleich.

Der SP-BIST wurde auf einem hochintegrierten GSM / UMTS-Transceiver-Chipmit zwei 4 GHzΣ∆PLLs in einer 130 nm CMOS-Technologie integriert, ohnedie Signalqualität zu beeinträchtigen. Die volldigitale Implementierung ist ro-bust gegen Technologieschwankungen und benötigt eine zusätzliche Fläche vonweniger als 0,06 mm2, die durch die Reduktion der Testzeit um 150 ms und dieverbesserte Testabdeckung mehr als ausgeglichen wird. DerTransceiver-Chipwurde getestet und zeigt die erwartete SP-BIST Funktionalität.


ABSTRACT vii

Abstract

Until a few years ago, RF ICs were low complexity devices thatrequired noDesign-for-Test (DfT) or Built-In Self-Test (BIST) features. Additional testblocks would have been uneconomical for these small devicesand RF parame-ters could not be measured with sufficient precision on-chip. Instead, productiontest was performed on automated test equipment. Since then,a general trendtowards wireless applications has turned RF ICs into high volume System-On-Chip (SOC) commodity products with dwindling gross margins. As before withdigital ICs, production test has become a bottle-neck for cost sensitive consumermarkets, turning DfT and BIST into an economic necessity forRF SOCs as well.

Sigma-delta modulated fractional-N Phase-Locked Loops (Σ∆PLLs) are keycomponents of today’s wireless transceivers for the generation and modulationof low-noise RF carrier signals with fast settling times. The tight interaction ofanalog and digital blocks makesΣ∆PLLs - and as a consequence the whole RFSOC - hard to test, especially as the analog ports of PLLs embedded in SOCs areinaccessible from the outside.

As digital DfT methods cannot address the rich analog and RF parameter space,a new approach for the autonomous, specification oriented test ofΣ∆PLLs in RFSOCs is needed. RF applications have to fulfill tight spectral requirements, spec-ified by parameters like frequency response or the level of spurious sidebands. Inthis work, a Spectral PLL BIST (SP-BIST) for on-chip analysis of the spectralproperties ofΣ∆PLLs is developed that requires no external RF test equipmentand does not disturb critical RF paths. The SP-BIST containsa stimulus genera-tor for PLL modulation and a block for spectral response analysis of the PLL RFsignal.

A simulation methodology had to be developed to predict transient and spectralbehavior and the interaction between RF and digital blocks of PLL and SP-BIST.Utilizing a standard VHDL simulator, the PLL bandwidth and phase noise couldbe simulated down to a noise floor of -200 dBc/Hz at 4 GHz.

A digital stimulus generator provides a two-tone sine signal in the range 16. . . 180 kHz with a spurious-free dynamic range (SFDR) of 60 dBfor efficienttesting of PLL spectral properties. The PLL is modulated digitally via the frac-tional frequency word. The two-tone signal is available as an oversampled Sigma-Delta bitstream as well as in parallel form, making it a versatile test signal forother analog and mixed-signal blocks on-chip as well.

The PLL RF signal is demodulated and digitized using a first order Sigma-Deltafrequency discriminator (Σ∆FD). Spectral estimation of the demodulated bit-


viii ABSTRACT

stream is performed using a 4th order multi-rate band-pass filter with a resolu-tion bandwidth of 0.8 kHz, achieving an SFDR of 45 dB and a noise floor ofL = −80 dBc/Hz. The band-pass center frequency is tuned with a single param-eter in steps of 300 Hz in the range 10 . . . 200 kHz. The low scalloping loss of thefilter gives a reproducible amplitude error below 0.5 dB for single tones. This andother systematic errors can be eliminated easily with a calibration run, resultingin a standard deviation of 0.05 dB for the PLL frequency response measured inconjunction with the on-chip multi-tone generator.

Using a digital envelope detector, the amplitude of the band-pass output is readout as a static word via the DUT serial data bus. This minimal test interfacealso enables an RF PLL test on wafer level. Total measurementtime is 3 ms perfrequency point.

Limited by the relatively low SFDR, in-band phase noise and the modulationmask can be measured as well. This on-chip calculation of spectral informationis an efficient way for test data compaction and allows directcomparison to spec-ifications in the frequency domain. Functional and many parametric faults canbe detected by measuring the PLL bandwidth and spectrum.

Both stimulus generator and band-pass filter utilize compact lossless resonatorswhich give good performance in spite of short coefficient andword lengths. Os-cillation and band-pass center frequencies are tuned with asingle parameter withnearly linear dependency. This simple relationship enables self-calibration aswell. Slow and computation intensive tasks like linearization, smoothing andlogarithmic scaling are performed off-chip to save chip area.

The SP-BIST has been implemented on an integrated GSM / UMTS transceiverchip with two 4 GHzΣ∆PLLs in a 130 nm CMOS technology. The fully digitalimplementation is robust against technology deviations, does not degrade the de-vice performance and requires an additional area of less than 0.06 mm2 whichis more than compensated by the improved test coverage and a reduction of testtime of 150 ms. The transceiver chip has been tested, provingthe SP-BIST capa-bilities and functionalities.


Contents

Kurzfassung v

Abstract vii

Table of Contents xii

List of Acronyms and Symbols xiii

1. Introduction 11.1. Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2. State-of-the-Art of DfT and BIST . . . . . . . . . . . . . . . . 4

1.2.1. Automated Test Equipment Based Test . . . . . . . . . 61.2.2. Structural Test . . . . . . . . . . . . . . . . . . . . . . 61.2.3. Functional Test . . . . . . . . . . . . . . . . . . . . . . 101.2.4. Alternate or Translation Test . . . . . . . . . . . . . . . 111.2.5. Loop-Back Test . . . . . . . . . . . . . . . . . . . . . . 111.2.6. Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . 131.2.7. PLL BIST . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.3. Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2. Fundamentals 212.1. Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.1.1. Symbols . . . . . . . . . . . . . . . . . . . . . . . . . 212.1.2. Definitions . . . . . . . . . . . . . . . . . . . . . . . . 22

2.2. Angle Modulation . . . . . . . . . . . . . . . . . . . . . . . . . 232.2.1. Angle Modulation in the Time Domain . . . . . . . . . 232.2.2. Sinusoidal Angle Modulation . . . . . . . . . . . . . . 252.2.3. Small-Angle Approximation . . . . . . . . . . . . . . . 272.2.4. Bandwidth of Angle Modulation . . . . . . . . . . . . . 27

2.3. Phase Noise Metrology . . . . . . . . . . . . . . . . . . . . . . 282.3.1. Double-Sideband Representation . . . . . . . . . . . . . 312.3.2. Single-Sideband Representation . . . . . . . . . . . . . 322.3.3. Frequency Modulation and Division . . . . . . . . . . . 34

2.4. Spectral Estimation of Simulation Data . . . . . . . . . . . . .36

ix

x Contents

2.5. Sampling and Quantization . . . . . . . . . . . . . . . . . . . . 392.5.1. Sampling . . . . . . . . . . . . . . . . . . . . . . . . . 402.5.2. Quantization . . . . . . . . . . . . . . . . . . . . . . . 402.5.3. Oversampling . . . . . . . . . . . . . . . . . . . . . . . 412.5.4. Subsampling and Downsampling . . . . . . . . . . . . 42

2.6. Sigma-Delta Modulation . . . . . . . . . . . . . . . . . . . . . 432.6.1. Single Bit Quantizer . . . . . . . . . . . . . . . . . . . 462.6.2. Quantization Noise inΣ∆M . . . . . . . . . . . . . . . 462.6.3. Spurious Tones of First OrderΣ∆M . . . . . . . . . . . 492.6.4. Higher OrderΣ∆M . . . . . . . . . . . . . . . . . . . . 492.6.5. Terminology . . . . . . . . . . . . . . . . . . . . . . . 52

2.7. Digital Resonators . . . . . . . . . . . . . . . . . . . . . . . . 522.7.1. Basic Properties . . . . . . . . . . . . . . . . . . . . . 522.7.2. Undamped Resonators . . . . . . . . . . . . . . . . . . 552.7.3. Resonance Gain and Peak Gain . . . . . . . . . . . . . 552.7.4. Constant Peak-Gain Digital Resonator . . . . . . . . . . 562.7.5. Bandwidth and Settling Time of High-Q Resonators . . 582.7.6. Resonator Implementations . . . . . . . . . . . . . . . 61

2.8. Fixed-Point Number Format . . . . . . . . . . . . . . . . . . . 632.9. Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.9.1. Direct Form and Related Filters . . . . . . . . . . . . . 642.9.2. Passivity and Reference Network Filters . . . . . . . . . 672.9.3. Resonator Based Filters . . . . . . . . . . . . . . . . . 692.9.4. Comparison of Filter Structures . . . . . . . . . . . . . 72

3. Introduction to the Circuit-Under-Test 733.1. Basic PLL Theory . . . . . . . . . . . . . . . . . . . . . . . . . 753.2. Circuit-Under-Test . . . . . . . . . . . . . . . . . . . . . . . . 783.3. PLL Specifications and Test Methods . . . . . . . . . . . . . . 82

4. Concept and Simulation Methodology for Spectral BIST 874.1. RF PLL Test Concept . . . . . . . . . . . . . . . . . . . . . . . 874.2. Measurement Principle . . . . . . . . . . . . . . . . . . . . . . 88

4.2.1. PLL Bandwidth . . . . . . . . . . . . . . . . . . . . . . 884.2.2. Spectral Analysis with FM Discriminator . . . . . . . . 89

4.3. From MADBIST to SP-BIST . . . . . . . . . . . . . . . . . . . 904.4. Partitioning of Test Hardware . . . . . . . . . . . . . . . . . . . 924.5. Simulation Methodology . . . . . . . . . . . . . . . . . . . . . 93

4.5.1. Special Requirements for PLLs . . . . . . . . . . . . . 944.5.2. Discrete Time Modeling of Analog Blocks . . . . . . . 954.5.3. Limitations of Event-Driven Analog Simulation . . . .. 98


Contents xi

4.5.4. Noise / Jitter Modeling . . . . . . . . . . . . . . . . . . 994.5.5. Spectral Estimation of Simulation Results . . . . . . . .1004.5.6. PLL Simulation Results . . . . . . . . . . . . . . . . . 100

5. Test Tone Generation 1035.1. Principle of Digital Sine Generator . . . . . . . . . . . . . . . .104

5.1.1. Direct Digital Synthesis . . . . . . . . . . . . . . . . . 1045.1.2. Arbitrary Waveform Generation . . . . . . . . . . . . . 1045.1.3. Lossless Digital Resonator . . . . . . . . . . . . . . . . 104

5.2. Digital Resonator with Low-PassΣ∆-Modulation . . . . . . . . 1075.2.1. Principle . . . . . . . . . . . . . . . . . . . . . . . . . 1075.2.2. Σ∆-Attenuator . . . . . . . . . . . . . . . . . . . . . . 1085.2.3. Multi-Tone Signal Generation . . . . . . . . . . . . . . 1105.2.4. Quantization Noise . . . . . . . . . . . . . . . . . . . . 112

5.3. Upconversion inΣ∆PLL . . . . . . . . . . . . . . . . . . . . . 113

6. On-Chip PLL Response Analysis 1176.1. Spectrum Analysis Overview . . . . . . . . . . . . . . . . . . . 117

6.1.1. Direct Spectrum Analysis . . . . . . . . . . . . . . . . 1176.1.2. Indirect Measurement of Angle Modulation . . . . . . . 120

6.2. FM Demodulation UsingΣ∆ Frequency Discriminator . . . . . 1216.2.1. Overview of FM Demodulation . . . . . . . . . . . . . 1216.2.2. Principle of First OrderΣ∆FD . . . . . . . . . . . . . . 1236.2.3. Signal-to-Noise Ratio ofΣ∆FD . . . . . . . . . . . . . 1266.2.4. Second OrderΣ∆FD . . . . . . . . . . . . . . . . . . . 132

6.3. Spectral Analysis of Baseband Signal . . . . . . . . . . . . . . 1336.3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 1336.3.2. Filter Topology . . . . . . . . . . . . . . . . . . . . . . 1346.3.3. Downsampling Cascaded-Integrator-Comb Filters . .. . 1366.3.4. Narrowband Filtering . . . . . . . . . . . . . . . . . . . 1436.3.5. Envelope and Display Detection . . . . . . . . . . . . . 151

7. Implementation and Measurement Results 1537.1. Baseband Test-Tone Generation . . . . . . . . . . . . . . . . . 153

7.1.1. Oscillation Frequency . . . . . . . . . . . . . . . . . . 1537.1.2. Amplitude and Amplitude Variation over Frequency . .154

7.2. Output Response Analysis . . . . . . . . . . . . . . . . . . . . 1567.2.1. Sigma-Delta Frequency Discriminator . . . . . . . . . . 1567.2.2. Spectral Analysis of Demodulated Bitstream . . . . . . 159

7.3. Area Estimation and Layout . . . . . . . . . . . . . . . . . . . 1607.4. Test Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162


xii Contents

7.5. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . 1647.5.1. Disturbances Caused by SP-BIST . . . . . . . . . . . . 1647.5.2. Spectrum of Test-Tone Generator . . . . . . . . . . . . 1657.5.3. Measurement Accuracy . . . . . . . . . . . . . . . . . 1657.5.4. Measurement of Unmodulated Spectrum . . . . . . . . 1677.5.5. Measurement of Modulated Spectrum . . . . . . . . . . 1697.5.6. Measurement of Frequency Response with Calibration. 174

7.6. Programming Examples . . . . . . . . . . . . . . . . . . . . . . 1747.6.1. Programming Registers . . . . . . . . . . . . . . . . . . 176

8. Conclusion and Future Work 1798.1. Comparison to Goals . . . . . . . . . . . . . . . . . . . . . . . 1798.2. Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

A. VHDL Behavioral Models 183A.1. Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183A.2. Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . 186A.3. Random Number Generator . . . . . . . . . . . . . . . . . . . . 187

Bibliography 189

List of Figures 203

List of Tables 207

Index 209


List of Acronyms and Symbols

AcronymsΣ∆M Sigma-Delta Modulation

Σ∆PLL Sigma-Delta PLL

CP Charge Pump

ABIST Analog Built-In Self-Test

ACF Auto-Correlation Function

ADC Analog-to-Digital Converter

ATE Automated Test Equipment

ATPG Automatic Test Pattern Generation

AWGN Added White Gaussian Noise

BE Backward Euler

BER Bit-Error Rate

BiCMOS Bipolar CMOS

BILBO Built-In Logic Block Observer

BISC Built-In Self-Calibration

BIST Built-In Self-Test

BOST Built-Off or Built-Out Self-Test

CDF Cumulative Distribution Function

CDR Clock-and-Data Recovery

CIC Cascaded Integrator-Comb (Filter)

CT Continuous-Time

CUT Circuit Under Test

xiii

xiv LIST OF ACRONYMS AND SYMBOLS

DAC Digital-to-Analog Converter

DDS Direct Digital Synthesis

DF Direct Form

DFT Discrete Fourier Transform

DfT Design-for-Test

DOT Defect Oriented Test

DSB Double Sideband

DSM Deep Submicron

DT Discrete-Time

DUT Device Under Test

EVM Error Vector Magnitude

FE Forward Euler

FFT Fast Fourier Transform

FM Frequency Modulation

FPGA Field-Programmable Gate Array

FSR Full Signal Range

GSM Global System for Mobile Communications, originally Groupe Spé-cial Mobile

HBIST Hybrid Built-In Self-Test

HDL Hardware Description Language

IC Integrated Circuit

IF Intermediate Frequency

LBIST Logic Built-In Self-Test

LDI Lossless Digital Integrator

LFSR Linear-Feedback Shift-Register

LNA Low-Noise Amplifier

LO Local Oscillator

LTI Linear Time-Invariant


List of Acronyms and Symbols xv

MADBIST Mixed Analog-Digital Built-In Self-Test

MASH MultistAge noise SHaping

MBIST Memory Built-In Self-Test

MISR Multiple-Input Signature Register

NTF Noise Transfer Function

OBIST Oscillation Built-In Self-Test

ORA Output Response Analysis

OSR Oversampling Ratio

OTA Operational Transconductance Amplifier

PA Power Amplifier

PCB Printed Circuit Board

PD Phase Detector

PDF Probability Density Function

PLL Phase-Locked Loop

PM Phase Modulation

PRBS Pseudo-Random Binary Sequence

PSD Power Spectral Density

RBW Resolution Bandwidth

RF Radio Frequency

RMS Root Mean Square

ROM Read-Only Memory

RWV Real World Value of binary number representation

RX Receiver

SC Switched-Capacitor

SDM Sigma-Delta Modulation

SFDR Spurious-Free Dynamic Range

SNR Signal-to-Noise Ratio


xvi LIST OF ACRONYMS AND SYMBOLS

SOC System-On-Chip

SOS Second-Order Section

SP-BIST Spectral PLL BIST

SPICE Simulation Program with Integrated Circuit Emphasis

SPOT Specification Oriented Test

SQNR Signal-to-Quantization-Noise Ratio

SSB Single Sideband

STF Signal Transfer Function

TLA Three-Letter Acronym

TPG Test Pattern Generation

TX Transmitter

UMTS Universal Mobile Telecommunications System

VCO Voltage Controlled Oscillator

VDSM Very Deep Submicron

VHDL VHSIC (Very High Speed Integrated Circuit) Hardware DescriptionLanguage

WDF Wave Digital Filter

WL Word Length

WLAN Wireless Local Area Network

Symbolsβ f Frequency modulation index

∆Q Quantization step size

ω Angular frequency

Ω Normalized angular frequency

ω+ Upper -3 dB frequency of band-pass

ω− Lower -3 dB frequency of band-pass


List of Acronyms and Symbols xvii

ω0 Nominal or carrier angular frequency

Ωc Center frequency

Ωr Resonance frequency

ωsT Loop gain transit frequency

φ Phase deviation from nominal phase

φi(t) Instantaneous phase

σ2e Variance of quantization error

θp Pole angle

A Amplitude

Am Modulation amplitude

B Bandwidth

B−3 -3 dB bandwidth

B−60 -60 dB bandwidth

Bm Modulation bandwidth

Bn Noise bandwidth

Brel Relative bandwidth

D Frequencies in the discrete time domain

en Quantization noise voltage

f Frequency

F Normalized frequency

f0 Nominal or carrier frequency

∆ f Frequency error or deviation

∆ f Peak frequency deviation

fc Corner or center frequency

fi(t) Instantaneous frequency

fl Lower -3 dB frequency of band-pass

fm Modulation frequency or offset frequency from the carrier


xviii LIST OF ACRONYMS AND SYMBOLS

fm Modulation frequency

fr Resonance frequency

fS Sampling frequency

fsig Signal frequency

fu Upper -3 dB frequency of band-pass

FSR Full Signal Range

g(t) (Forward) transfer function in the time domain, impulse response

G(s) (Forward) transfer function in the frequency domain

h(t) Transfer function in the time domain, impulse response

H(s) Transfer in the frequency domain

∆Hsc Scalloping loss

kBW Coefficient determining the damping in resonator loop

kf Coefficient determining the resonance frequency in lossless res-onator

∆kf Difference of coefficients determining the resonance frequency instaggered resonator sections

kFM Frequency modulation gain

kPM Phase modulation gain

L ( fm) Phase noise

m(t) Message or modulation signal

N Division ratio

N Average division ratio

Nq Quantization noise power

N′q( f ) Quantization noise power spectral density

Q Quality factor

qe Quantization error

QF Number of fractional bits (position of binary point)

QI Number of integer bits (position of binary point)


List of Acronyms and Symbols xix

rp Pole radius

RBW Resolution Bandwidth

s Complex frequency

S Normalized complex frequency; signal power

SF Shape factor or selectivity of a band-pass filter

s(t) Signal

sFM(t) Angle modulated signal

Sφ ( fm) Phase instability

Sy( fm) Frequency instability

t Time

T Period

T(s) Closed-loop transfer function

∆T Period error or deviation

Tq Quantization time step

Tsym Symbol period, reciprocal of symbol rate

WL Word length in bits

y(t) Relative frequency deviation

y Peak normalized frequency deviation


xx LIST OF ACRONYMS AND SYMBOLS


The most exciting phrase to hear in science, theone that heralds new discoveries, is not

"Eureka!" (I found it!) but "That’s funny..."

Isaac Asimov 1Introduction

The motivation for improving testability of radio frequency integrated circuits isdeveloped with the main focus on the frequency synthesizer building block. Areview of state-of-the-art Design-for-Test techniques for PLLs is given and thegoals for this work are defined.

1.1. Motivation

Since its invention in 1958, integrated circuits (ICs) havetaken an incredibledevelopment. Starting with a few electronic components on agermanium die,the change to silicon enabled the evolution of ICs into full blown Systems-On-Chip (SOC) like one-chip computers, fully integrated Ethernet transceivers orsingle-chip cellular phones. ICs have become so pervasive in everyday life thatIsaac Asimov once called their invention "the most important moment since manemerged as a life form" [Ber05].

The first device breaking the one million transistor barrierwas a 1-Mbit dynamicmemory in 1986, manufactured in a 1.0-micron complementarymetal-oxide-silicon (CMOS) process. In 1989, the Intel 80486 32-bit processor was the firstlogic device to take this hurdle. It had 1.2 million transistors and operated at

2 1. Introduction

up to 50-MHz clock frequency. Only 16 years later in 2005, thefirst micro-processor featuring more than abillion transistors was Intel’s 64 bit Itanium-2,manufactured in the 90 nm technology node with clock frequencies in the GHzrange. Moore’s famous prediction ("Moore’s law") that the number of transis-tors available for designing an integrated circuit doublesevery 18 months hasnot only been proved correct for the past 40 years, it is also expected to be validfor at least the next 10 years to come [Moo03]. And even when, finally, thelimits of physics will prevent a further reduction of feature sizes, new packagetechnologies utilizing the third dimension will enable higher and higher systemintegration densities [Tum06].

This integration of system functionality onto a chip allowed to decrease the num-ber of components of high technology products. Additionally, shrinking IC fea-ture sizes enabled by advances in manufacturing processes reduced the price ofthe chips themselves. These two trends created new markets when high tech-nology became affordable for consumers as a central part of entertainment andcommunication devices like mobile phones, MP3 players or digital cameras.

This shift toward high volumes at low prices has significantly increased the per-centage of test costs of the total production costs as production test time andcosts scale with chip complexity, not with chip area. And despite low prices, thedemand for quality became higher and higher as faulty products not only meanincreased follow-up costs for the manufacturer, they can also be very damagingto the image of a product and the value of a brand.

In the 1980s, this trend forced makers of digital chips to adopt Design-for-Test(DfT) and Built-In Self-Test (BIST) methods. These techniques have proved tobe immensely successful to keep test costs down in spite of a few percent areaoverhead. Two factors had helped this development:

(1) Digital signals can be propagated and stored without signal degradation,which eased the design of test logic that does not deteriorate system per-formance.

(2) The boolean nature of digital failures also eases the creation of models andsoftware for fault simulations.

About 10 years later, production test became a bottleneck for mixed-signalanalog-digital chips, however, the parametric nature of analog failures and thecorresponding complexity of fault simulations impeded systematic DfT ap-proaches. Many applications also could not tolerate the system performancedegradations brought by DfT enhancements.

This is even more problematic for Radio Frequency (RF) ICs which now hit the


1.1. Motivation 3

production test wall: Until a few years ago, these devices were low-complexitydevices manufactured in special technologies like BiCMOS (Bipolar CMOS) orGaAs requiring no DfT support. The general trend towards wireless deviceshas fired up fierce competition; the shrinking profit margins and the availabil-ity of mainstream CMOS technologies with transit frequencies exceeding 100GHz made IC designers attempt the seemingly impossible: theintegration ofRF frontend and digital base-band signal processors on one die. This approachhas proved successful for Bluetooth in 2004 [SML+04], WLAN (Wireless LocalArea Network) in 2005 [KDZ+05] and GSM (Global System for Mobile Com-munications) in 2006 [BHH+06]. The drawbacks of deep submicron (DSM)CMOS technologies for analog and RF circuits (high parameter spread, low-gaindevices) could only be compensated using digital built-in self-calibration (BISC)schemes [MKNM05].

As test costs account for a growing percentage of the total production costs, DfTand BIST have become an economic necessity for RF ICs as well.Increasing sig-nal frequencies aggravate the problem by pushing up the costs per tester channel.This is in contrast to low-performance devices and memorieswhere efficient DfTmeasures reduce the costs per channel.

Chip area overhead, potential degradation of RF performance and yield and in-creased package cost due to additional pins have made DfT an unpopular optionfor RF ICs so far [FWM03]. On the other hand, the high integration densityof DSM CMOS technologies allows the realization of complex digital signal pro-cessing blocks with little area penalty. This also favors the digital implementationof on-chip test circuitry for analog blocks.

Besides reducing test time, a second motivation for introducing RF BIST isaccess to embedded analog blocks. Building blocks with analog interfaces tothe outside world like Analog-to-Digital-Converters (ADCs), Digital-to-AnalogConverters (DACs) or Low-Noise-Amplifiers (LNAs) can stillbe tested using theanalog capabilities of the Automated Test Equipment (ATE).As a direct conse-quence of system integration, an increasing number of building blocks is com-pletely embedded in the system. Phase-Locked Loops (PLLs) are a prominentexample for a complex mixed-signal building block that is nolonger directlyobservable or controllable from outside. PLLs are core building blocks for RFsystems: they are used to generate a clean, stable Local Oscillator (LO) signalwith programmable frequency from a fixed reference frequency.

Increasingly,Σ∆-modulated PLLs (Σ∆PLLs) are used in RF CMOS transceiversbecause this highly digital architecture is well adapted tothe parameter varia-tions of DSM technologies [MKNM05].Σ∆PLLs achieve excellent spectral pu-rity and high frequency resolution together with fast settling times. The output


4 1. Introduction

frequency can be modulated digitally, makingΣ∆PLLs well suited for mainlydigital RF transmitters or spread spectrum applications. However, the tight in-teraction between analog and digital sub-blocks makes production test a difficultand time-consuming task even when key analog signals like the tuning voltageor the output of the Voltage Controlled Oscillator (VCO) canbe accessed fromthe tester. In highly integrated SOCs, this is often not the case, restricting test ofembedded (Σ∆)PLLs to time-consuming and often inaccurate indirect measure-ments.

For these reasons, DfT support forΣ∆PLLs is a highly desirable feature forspeeding up production test and improving testability. Thenext section gives anoverview of the existing approaches to improve testabilityof integrated circuits,and which of them could be suitable for PLLs.

1.2. State-of-the-Art of DfT and BIST

Production test of complex devices like wired circuits, later of printed circuitboards (PCB) and finally of ICs and systems-in-package has been and is per-formed using two fundamentally different approaches:specification orientedtests(SPOT) perform afunctional test, ensuring that the product performs itsspecified functions and fulfills the specifications committed to the customer. Atthe end of the assembly belt of a Ford Model "T", a worker woulde.g. trigger thewinkers and test the breaks, trying to verify all operating modes. However, fullfunctional test of a complex product takes too long and requires specially skilledworkers. Another drawback is that manufacturing defects can cause in-field fail-ures due to untested or unforeseen operation modes.

The alternative,structural or defect-oriented test(DOT) targets manufacturingcorrectness to ensure the product quality. For the example of the Model "T",a worker would check whether all screws are present and tight. Another early,pre-IC example for this kind of test is optical inspection ofthe solder dots of anprinted-circuit board (PCB).

This method lends itself to unskilled workers and automatedprocedures becauseno knowledge about the product is required. However, it may be difficult to mapmanufacturing defects to functional failures: functionally good devices may bethrown away because of insignificant defects, reducing yield and gross marginfor the manufacturer. The other case is even worse: unmonitored defects maylead to shipping of faulty devices and consequently replacement costs and lossof reputation.


1.2.S

tate-of-the-ArtofD

fTand

BIS

T5

Design-for-Test (DfT)

Defect Oriented Test (DOT)

Structural Test

Chip Level

Analog / RF

Scan PathBIST

Analog BIST(ABIST)

OscillationBIST (OBIST)

Hybrid BIST(HBIST)

IDDQ

Digital

Logic BIST(LBIST) Scan Path

Next levelassembly

SPecification Oriented Test (SPOT)

Functional Test

Ad-hoc Test BIST

Analog / RF

Mixed AnalogDigital BIST(MADBIST)

RF loopback

PLL BIST

JitterBIST

Spectral PLLBIST (SP-BIST)

Alternate Test

Figure 1.1.: Overview over DfT techniques

Spe

ctralP

LL

Built-In

Se

lf-Testfo

rIn

tegra

ted

Ce

llula

rTra

nsm

itters

6 1. Introduction

The deep hierarchies of current integrated circuits prevent the direct control andobservation of most components on-chip, giving bad coverage for structural test.Due to the sheer number of operational modes, a pure functional test has alsobecome impractical. Most products are therefore tested using a combination ofstructural and functional test to minimize the "blind spots". Several techniquesare applied during the design phase of an integrated circuitand additional testcircuits are integrated to improve its testability. These techniques are subsumedunder the labelDesign-for-Test(DfT):

• Support for structural IC test (e.g. scan design)

• Support for structural test of next level assembly (boundary scan)

• Support for functional IC test (built-in self-test, built-out self-test)

Fig. 1.1 gives a graphical overview of the different DfT techniques described inthe following.

1.2.1. Automated Test Equipment Based Test

As stated earlier, in production test, typically a combination of structural andfunctional tests is applied at both wafer level and for packaged devices. Aftera first basic test to assure proper contacting of the device, scan test vectors areloaded into the chip and the resulting response is analyzed (structural test withDfT). Current consumption for different test vectors and operation modes is mon-itored (IDDQ / alternate test). Especially for analog / RF devices, several criticaloperating modes are verified (functional test). Although "test coverage" is dif-ficult to define when functional tests are involved, the usualprocedure is tryingto verify all the critical specifications of the customer data sheet. Further de-tails about economical conditions, tester costs etc. can befound in [Int05] and[FWM03].

1.2.2. Structural Test

In IC manufacturing, basic device structures like wires andvias, transistors andgates are checked for manufacturing correctness with the target of achieving thespecified device behavior. As the terms "defect", "failure"and "fault" are oftenmixed-up, Box 1.1 contains a short definition of how these terms are used in thiswork and in most other publications related to test of integrated circuits:


1.2. State-of-the-Art of DfT and BIST 7

A fault is an abstract representation of adefectthat can lead to thefailure of the device.

Every defect should be mapped to a fault, but not every defector fault results inthe failure of the DUT. This is especially true for analog or RF circuits.

Defect: imperfection of a component or structure that violates the technologyspecifications, e.g. a bridge between a pad and ground or an excessivedeviation of a sheet resistance value.

Failure: behavior of a DUT that does not conform to customer specifications, beit functional or parametric, e.g. a microprocessor calculating 2+2 = 5 ora filter with a corner frequency outside the specification band.

Fault: a defect mapped to an abstract, computer-readable representation of thechip which could be a gate level or SPICE netlist of lumped components.Examples for faults are a node stuck at zero level or a resistor with twicethe target resistance.

Box 1.1: Important Definitions

For defect-oriented testing, a set of input patterns, also called test vectors, is de-termined that stimulates a high number of the basic devices,the correspondingideal responses are simulated and recorded. During production test the prede-termined stimuli are applied to the DUT and the responses arecompared to thepredetermined, ideal ones. This only works well when a high percentage of inter-nal nodes iscontrollableandobservable. Finding suitable stimuli is a task wellsuited for computers as structural test is a brute force approach without know-ledge about the function of the circuit. Besides topological information (a netlistor layout),fault modelsare needed for fault diagnosis techniques. A computercannot understand the concept of "defects", instead, hypotheses about how thecircuit will fail - fault models - have to be formulated. Together with an initialset of test vectors, afault simulationis started where various faults are insertedinto the circuit. The simulator then checks whether the current set of test vectorscan detect the difference between faulty and correct circuit behavior and tries tofind new test vectors if the fault coverage is unsatisfactory.

Digital Structural Test

Due to their complexity, digital ICs were the first to suffer from the loss of ob-servability and controllability of internal nodes.Scan techniqueswere introducedto improve fault detection during structural test: The basic idea is to implementa scan mode where all the flip-flops in a design are hooked up as along shift


8 1. Introduction

CLK

QDSESI

QD

SISE

QD

SISE

Sen

Sin

Din

Dout

Sout

Logic

Combinational

Figure 1.2.: Scan structure

register (Fig. 1.2). An additional test multiplexer at the input of each flip-flop isused to select the scan mode (Fig. 1.3). The first and last flip-flop can be writtenresp. read via special pins. When switching from normal operation to shift mode,the state information of all flip-flops can be read out sequentially while shiftingin a new test vector. When switching back to normal operation,the test vectorthat has been shifted into the scan chain serially now is applied to the inputs ofthe combinational logic. The correct behavior of the circuit can now be verifiedfrom either the read-out vector or by using current-based techniques like IDDQtest.

Scan insertion together with Automatic Test Pattern Generation (ATPG) is themost common DfT technique for digital ICs in industry: Mature software, wellintegrated into the design flow, is available for scan insertion and ATPG. As scantechniques are structure based, they work independently ofthe circuit functionand require only little manual intervention of the designer. The additional mul-tiplexer of scan flip-flops and the additional wiring increases the chip area byapprox. 5 . . . 20% [PN03]. This overhead is no longer questioned due to lack ofalternatives.

Stuck-at faultis the simplest fault model for digital circuits, assuming only sim-ple boolean logic errors caused by nodes stuck at 0 or 1.Stuck-open faultsaddmemory effects to the fault model due to the charge storage ofMOS logic. Unfor-tunately, defects in CMOS technologies with feature sizes below 100 nm (verydeep submicron, VDSM) are not well modeled by stuck-at or stuck-open faults.An increasing number of failures is caused bybridging defects, i.e. bridges be-tween nodes. The bridging resistance determines the amountof delay variationand quiescent current. Only very low-ohmic bridges cause boolean errors that



Test MUX

DD−FF D

outDin

1

0

Sin

SoutS

en

CLK

Logic Overhead

Figure 1.3.: Scan flip-flop with test-logic overhead (dashed box)

can be detected by static tests. Fault modeling is complex for this class of de-fects as failures are parametric and so is testing, touchingproblems of analogtest. Additional test methods like at-speed or quiescent current (IDDQ) testinghave to be used to find these defects [SCP+99, SH04].

However, the high leakage currents in VDSM technologies reduce the sensitivityof IDDQ tests. At-speed tests are difficult to implement due to lacking automatedtool support. For these reasons, functional tests are used increasingly to improvetest coverage or for speed binning.

Analog Structural Test

DOT has worked very well for digital circuits for more than 25years now, andthe idea of using a similar approach for analog ICs was and is very appealing.However, the rich parameter space of analog circuit design does not allow a re-duction of complexity similar to digital circuits. While simple Boolean logic andregister-transfer level abstractions are working fine for digital systems, a state-of-the-art BSIM4 analog transistor model has more than 100 principal parameters(and approx. 300 in total). Hierarchical partitioning of analog circuits is difficultand error prone as the selection of which parameters and constraints have to bepassed between abstraction layers is a manual task.

Even the concept of "fault coverage" which is a well acceptedtest quality metricfor digital test is difficult to define for analog test. Only simple open/short de-fects lead to significant performance degradations of the analog DUT that can bedetected easily; these faults are classified ascatastrophicor hard faults. Analogand especially RF circuits usually try to push the limits of the process technology.Consequently,parametric failures, i.e. a DUT performance slightly outside thespecifications, are far more important. Tracking these failures back to individ-


10 1. Introduction

ual defects is daunting, defining limits for the corresponding parametricor softfaultseven more so. DOT approaches are based upon detecting catastrophic andparametric faults due to defects of individual components,however, not everyparametric fault or combination of parametric faults causes a parametric failureof the device. A strict application of DOT principles may therefore lead to a lossof yield for analog devices.

[Mil98] gives an overview over the challenges involved withdefining and findingfaults for analog blocks. The effort of simulating catastrophic and parametricfaults is high, requiring a large number of analog Monte-Carlo simulations todetect these faults. Hence, analog fault simulation so far is restricted to smallcircuit blocks like OTAs and low-order filters [GPG01], it has yet to find its wayinto industry. An automaticRF structural testseems even more unlikely for thenear future, given the difficulties of accurate "normal" RF simulations, except forlow-complexity devices like LNAs [KDCM04]. A similar procedure for complexmixed-signal building blocks like PLLs or ADCs has not been published yet anddoes not seem feasible in the near future. A structural PLL test presented in[MCAS05] e.g. only covers some charge-pump related catastrophic defects.

In contrast to digital ICs, there is also no solution in sightfor monitoring and con-trolling internal analog nodes without signal deterioration. Analog scan chainswere an attempt to adapt the hugely successful digital scan design techniques:[Wey90, SW98] suggest a chain of sample and hold amplifiers as an analog shiftregister for this purpose. Limited scan chain length due to accumulation of er-rors, the large area overhead (one opamp and a sampling capacitor per stage) andthe restriction to near-static signals have so far limited the practical use of thistechnique.

Analog test busesand multiplexers for controlling and monitoring analog nodes[Wur93] are used to some extent in products, though mainly for quasi-static sig-nals like bias currents. As there is no tool for scan insertion like in the digitaldomain, a manual selection of the analog nodes of interest isrequired as well ascareful analog design to avoid performance deterioration due to the loading ofinternal nodes.

1.2.3. Functional Test

On a first glance,functional testingseems to be more economical than structuraltesting because only modes that are important for the customer need to be tested.However, given the multitude of operation modes and input values of SOCs, theduration for an exhaustive functional test would be forbiddingly long. Addition-



ally, the task of finding a sufficient and not too redundant setof test vectors is verytime consuming with little potential for automation. For these reasons, functionaltest for complex chips is oftenhierarchical, i.e. thedevice under test(DUT) ispartitioned into several smallercircuits under test(CUT) that are verified individ-ually using functional and / or structural test. Microprocessors are an examplewhere functional test is applied to test the maximum speed ofcritical blocks, butthe overwhelming part of test coverage is achieved by structural test.

Analog or RF ICs are a different matter: the lack of a feasibleDOT for analogand RF blocks leaves no alternative to specification oriented test (SPOT).

1.2.4. Alternate or Translation Test

Translation test is related to functional test, it translates an on-chip performanceparameter like a signal amplitude to a proportional DC-voltage or a frequency[SK93], requiring precise, linear on-chip converters.

Alternate test is a more general approach; the translated values do not needtohave a direct or linear relationship to the performance parameter. In order toachieve a strong correlation between test response and specification parameter,suitable test stimuli have to be constructed. A single-tonestimulus with a fre-quency of e.g. 2f−3dB is much more efficient than a noise signal to characterizethe -3 dB frequency of a lowpass filter. An alternate test for RF frontends hasbeen developed [Gop05] that deploys a wideband current sensor for on-chip sig-nal monitoring. [AC04] deploys subsampling and a noise reference to extract sig-nal features related to harmonic distortions of RF buildingblocks (hence dubbed"feature extraction").

A strong correlation eases extraction of pass/fail criteria from the test responsebut still requires substantial on-chip or off-chip computing power, limiting thismethod to low-complexity, near-linear blocks like an LNA [CLM+07].

1.2.5. Loop-Back Test

Originally, loop back test is a concept for testing ADCs and DACs by reusinganalog on-chip resources for BIST purposes. The convertersare operated back-to-back in such a way that stimulus generation and response analysis can beperformed entirely in the digital domain. Loop-back test isvery appealing dueto its low hardware overhead and the possibility for a fast system check, how-


12 1. Introduction

ever, several inherent limitations render a loop-back testimpractical for manyapplications:

• Checking two unverified block against each other may mask errors. Priortesting of the higher performance block using ATE or additional BIST com-ponents [Li04] may be a workaround to this problem but reduces the effi-ciency of the loop-back approach.

• "Performance" is a multi-faceted parameter, comprising dynamic range,sampling speed, differential and integral nonlinearity (DNL / INL), inter-modulation distortions etc. One of the converters has to be superior to theother in all aspects which is unlikely for high-performancecomponents.

• Inserting analog multiplexers into the signal path to closethe loop bringsthe risk of performance deterioration.

• Loop-back is an integral system test that provides no information aboutthe cause of the failure which is needed for yield improvement in volumeproduction.

The technique of re-using the on-chip receiver (RX) path to mix down and de-modulate the transmitter (TX) signal in RF transceivers is dubbedRF loop backtest. Some additional problems make a loop back test at RF even harder to im-plement:

• On- and off-chip crosstalk due to RX and TX running at the samefre-quency degrades accuracy.

• In time-division multiple access (TDMA) systems like GSM orBluetooth,RX and TX often cannot operate simultaneously because thereis e.g. onlyone local oscillator shared between RX and TX path or becausepowerconsumption would be too high.

• RX and TX frequency range in frequency division duplex (FDD)systems(all major cellular and short-range communication standards) do not over-lap. Hence, one of the two blocks has to run outside the standard operationrange during test, requiring the design of an extended frequency range. Ad-ditionally, the test results do not reflect the real operation case.

Due to these reasons, loop-back test cannot be applied for most RF systems.



1.2.6. Built-In Self-Test

In order to improve test efficiency,built-off self-test1 (BOST) andbuilt-in self-test(BIST) have been developed as DfT techniques for both structural and func-tional test. The target of BIST / BOST is to minimize ATE requirements byreducing volume and bandwidth of stimulus and circuit response signals. BISTachieves this task by using on-chip test-pattern generation (TPG) and output re-sponse analysis (ORA). The ORA usually generates a compact representation ofthe input data, the so-calledsignature. Pass / fail information is determined bycomparing the signature to the value for the fault-free case.

BOST performs the same tasks not within the chip but on the load board. Thisis achieved e.g. with an RF mixer to reduce the signal frequency or with a field-programmable gate array (FPGA) to compress digital data. Inmany cases, BISTcircuitry can be replaced by BOST and vice versa, trading chip area against inter-face pins and board area. For this reason, BOST is not treatedseparately in thiswork.

Another application of BIST is not regarded here: Fail-safesystems employ BISTfor a continuous on-chip test during operation, switching over to a redundant unitor powering down the system in case of an error.

The main drawback of BIST is that it requires more chip area and more effortduring the design phase than ATE based test. Circuit partitioning and test patterngeneration are mainly performed usingad hocmethods without mathematical un-derpinning and therefore little potential for automation.Design effort and chiparea for the additional BIST blocks have to pay-off in terms of reduced test-timeand tester resources and / or quality improvement. This is best achieved usingdigital, synthesizable test blocks which are compact and reusable, minimizingboth area and design effort. Like other DfT measures, BIST isusually imple-mented on a block level to speed-up both test development andthe test itself,with highest priority on those blocks that are hard to test otherwise. Observabil-ity and controllability for the individual building blocksis provided via a digitaltest bus to avoid the routing of sensitive analog signals across the chip.

Logic BIST

In 1979, the first logic BIST (LBIST) was presented [KMZ79] using a linear-feedback shift-register (LFSR) to generate pseudo-randombinary sequences

1Also called built-out self-test


14 1. Introduction

(PRBS) as test-patterns. Output response analysis and compaction was per-formed with amultiple-input signature register(MISR) (Fig. 1.4), implementedwith an LFSR with additional parallel inputs and combined with the scan chain.This structure was namedbuilt-in logic block observer(BILBO) [KMZ79].

Test coverage and test times have been further improved since by using moredeterministic test generators optimized for individual CUTs [GSHA01, Cha03].

Clock

LFS

R

MIS

R Pass / Fail

BIST

SignatureBIST

Start

Com

bina

tiona

lLo

gic

Figure 1.4.: Principle of digital BIST

BIST for embedded memory blocks (MBIST) [BCW05] is a very successful vari-ant of LBIST: The regular structure of memories facilitate the development ofreusable BIST approaches; the large number of required testvector provide theeconomic momentum to spend additional chip area for the BISTcircuitry. Secu-rity sensitive chips like chip cards are yet another application for LBIST becausescan test mode is a potential security vulnerability.

Analog BIST

Fully analog BIST (ABIST) has only limited applications as low-complexity ana-log chips cannot afford the additional BIST chip area. High complexity devicesusually feature digital signal processing which can provide more efficient TPGand ORA. Examples are [RAB97] who investigates analog output compactionfor transient signals, and [LMP96] who does the same for testtones. In bothcases, a signature is generated by a sampled integrator withthreshold detector.

Oscillation BIST

In oscillation BIST, the CUT is reconfigured as an oscillatorduring test mode,requiring no test patterns. Failure to oscillate or a deviation of oscillation fre-quency indicate a defect. Oscillation test can be an elegantself-test option but



works only for certain filters and amplifiers [AK97, Won00]. Similar schemesmight be feasible for RF blocks like low-noise amplifiers (LNA) but these blocksusually are too sensitive to add parasitic loads and risk unwanted cross-couplingcaused by elements not needed for operation.

Hybrid BIST

Hybrid BIST (HBIST) [Ohl91] was the first attempt to perform abuilt-in self-testof ADC and DAC using simple digital signal processing: An additional LFSRgenerates transient pseudo-random test patterns for the DAC whose output issampled by the ADC. A second LFSR compacts the ADC output intoa signature.This concept of testing ADC and DAC "back-to-back" is similar to a loop-backtest with additional on-chip stimulus generation, response analysis and signaturecomparison.

It also has some additional drawbacks: As small parametric fluctuations of DACor ADC yield completely different signatures, this approach is problematic forproduction testing. Similar to LBIST, the pseudo-random test signals do notreflect ADC / DAC specifications, leading to losses in fault oryield coverage andlong test times.

Mixed Analog-Digital BIST

The use of multi-tone TPG and ORA is a better choice for analogblocks specifiedin the frequency domain. It is also easier to define metrics like the maximumamplitude of an intermodulation product for these test signals that are robustagainst small parametric variations. It is aspecification oriented BISTas stimulican be tailored to the CUT specifications, providing for a more efficient test thanpseudo-random signals.

With this reasoning, multi-tone Mixed Analog-Digital BIST(MADBIST) con-cepts for speeding up the time consuming production tests ofhigh-resolutionADCs and DACs were developed in 1993 [TR93b]. Similar to HBIST, both thestimulus and the response analysis are performed in the digital domain; DAC andADC are also tested back-to-back (Fig. 4.3(a)). However, the authors managed tofind a solution to the chicken and egg problem2 of testing two unverified blocksagainst each other: first, a multi-tone analog stimulus is generated on-chip for aself-test of the ADC. The analog stimulus is extracted with aone-bit auxiliary

2In biology, evolutionary scientists have now proved that the egg came first [CNN06].


16 1. Introduction

DAC and a low-pass filter from an oversampled digital bit-stream. This leavesthe auxiliary DAC and the filter as the only unverified analog circuit block andallows operation in an uncalibrated environment. In the second step, the DAC ischaracterized using the now verified ADC.

1.2.7. PLL BIST

Due to the complexity of conventional PLL verification, the potential reward ofimplementing DfT measures is high and many attempts have been made to targetfunctional and performance verification. Some basic self-test features are im-plemented in most PLLs to detect catastrophic failures [BLBR04, AS07]. Pulsecounting with an on-chip frequency counter is such a simple but effective digitalBIST method for verifying basic PLL functionality and parameters like center fre-quency, frequency range and VCO loop gain [KSR00, MSMG02, MS02b, MS03,YL07].

The complex interactions within a PLL make it difficult to establish correlationsbetween complex specification parameters (e.g. RMS jitter,closed-loop band-width) and simple PLL quantities (e.g. phase detector pulsewidth, loop filtervoltage) [YL07]. In practice, it is also very difficult to measure e.g. the loop filtervoltage with sufficient accuracy without deteriorating PLLperformance. Hence,most successful approaches for detecting parametric failures measure the speci-fied parameters directly.

PLL Jitter BIST

In the last years, several BIST approaches have been presented for PLLs usedin clock synthesis for microprocessors or in clock-and-data recovery (CDR) forhigh-speed wire-bound data transmission. These applications are specified in thetime-domain; signal analysis focuses on time-related parameters like timing jitter.The interest in on-chip measurement of PLL timing jitter hasincreased tremen-dously with the advent of SOC solutions for high-speed serial transceivers inchip-to-chip [CMJ+03] or Gigabit Ethernet [CKTM02] communication. Com-petitive pressure for communication products and the high costs for fast ATEhelped to create the financial momentum for developing DfT / BIST solutions.

Several methods have been published that determine the cycle-to-cycle jitter froman estimation of the autocorrelation function (ACF) around∆t = T0. Collectingmultiple cycle-to-cycle jitter measurements yields the probability density func-tion (PDF) and the cumulative distribution function (CDF) of the jitter. Subse-



quently, the RMS cycle-to-cycle jitter can be calculated [Ros92] from the CDF.The main functions of generating and calibrating the delay and determining theauto-correlation have been implemented in different ways:

Figure 1.5.: PLL BIST for measuring cycle-to-cycle jitter [SR99]

The "Fluence PLL BIST" method [SR99, SR02] utilizes a programmable digitaldelay line and a phase detector for estimating the auto-correlation function (ACF)of the PLL signal (Fig. 1.5). Cycle-to-cycle jitter is measured by counting allevents where original and delayed signal differ and slowly sweeping the delay.The digital delay line is calibrated by operating it in a self-oscillating mode andmeasuring the frequency. This method is applied commercially as it requires onlylittle hardware and no precision components. Variations ofthis method utilize acoincidence detector [VB03] or a phase detector with programmable dead time[Fet05] instead of the simple phase detector.

Vernier delay lines [Kal04] can also be used to measure the instantaneous periodor the phase error in a PLL [SOE01, CR04]. However, the long latency of vernierbased measurements limits the frequency resolution to relatively low frequenciesand requires long measurement times. The solution presented in [HS08] needsmore than 3 s to generate an jitter histogram on-chip with a resolution of 1 ps.

Measuringk-cycle jitter for many different values ofk [Kun05] reveals spectralproperties of the jitter at the cost of even longer measurement times. Additionally,


18 1. Introduction

vernier circuits are large and complex, requiring precision analog components.However, for digital PLLs utilizing vernier based time interval measurements(time-to digital converter, TDC) [MS07], jitter information can be gathered withlittle overhead [EBSB07].

For testing thebit-error rate (BER), receiver and transmitter are connected inloop-back mode, sent and received bits of a pseudo-random binary sequence(PRBS) are compared for errors. Loop-back test is feasible,because receiverand transmitter of wire-bound systems operate at the same frequency and withsimilar signal levels. However, verification of very low BERs requires exces-sive measurement times; [SR07] proposed measurement of thePLL RMS jitterinstead, using subsampling with a slightly offset frequency.

Frequency Domain PLL BIST

In contrast to time-domain specified PLL Jitter BIST, there are bare to none ap-proaches for a PLL BIST in the frequency domain: PLLs in wireless systemsare specified in the frequency domain (frequency response, phase noise, spurioussidebands) and should be tested accordingly. Calculating frequency domain spec-ifications from time-domain measurements is possible but very inefficient withlong measurement times due to the required large number of jitter measurements.

Several publications try to assess the PLL performance at the output of the phase-frequency detector (PFD) because this is a digital, comparatively low-frequencysignal. For high-performance PLLs in wireless systems, this is a dangerous ap-proach: The relative phase error of the VCO signal appears divided byN, makingit moredifficult to quantify the signal error at this node in practical implementa-tions. The output of the PFD is also a very sensitive node in the PLL; disturbancesintroduced at this node appear multiplied byN at the VCO output. Due to thesereasons, most publications, e.g. [ABM+09] only present simulation results.

Figure 1.6.: Self-calibrated on-chip phase noise measurement circuit [KBK07]


1.3. Goals 19

In contrast, [VGKB+07] presents a phase noise BIST based on a tunable delay-line and mixer achieving a measured sensitivity of -75 dBc at100 kHz offset atthe cost of an additional 0.5 mm2 of analog building blocks in a 0.25µm tech-nology. Using the same area in the same technology node, [KBK07] achieves asingle-tone sensitivity of -75 db using a self-calibrated delay-line (Fig. 1.6).

1.3. Goals

Today’s RF SOCs require multiple test insertions, i.e. production test on spe-cialized digital, RF and sometimes also mixed-signal automated test equipment.Power and speed of digital testers have to increase with the growing digital com-plexity of RF SOCs providing ever more features and media support. This means,in the long run, test costs can only be minimized by performing all productiontests on a single digital tester, eliminating RF and mixed-signal ATE.

However, efficient DfT concepts for RF Systems-On-Chip (SOC) are amiss, asshown in the last section. RF PLLs are among the most troublesome buildingblocks on RF SOCs as important signals like RF output or tuning voltage areusually unaccessible from outside. The reduced testability slows down produc-tion test of the whole device under test (DUT). Consequently, this work starts theimprovement of RF SOC testability at the RF PLL. The focus is on Σ∆-modulatedRF PLLs (Σ∆PLLs) as they have become the industry standard for RF synthesisand offer convenient digital modulation capabilities.

Σ∆PLLs are not only hard to test, the tight interaction betweendigital blocks (e.g.Σ∆-modulator) and analog blocks (e.g. VCO and loop filter) is also very hardto simulate, especially when the noise performance is important. Usual mixed-signal, RF or digital simulators do not provide the requiredsimulation perfor-mance out-of-the-box, therefore, a newmodeling and simulation methodologyis needed to complement standard simulators.

As the complexity ofΣ∆PLLs will not allow structural test in the near future, thiswork will focus on functional DfT enhancements onblock level. In contrastto system level tests, block level tests help to improve yield and the portabil-ity of building blocks like theΣ∆PLL. The reuse of e.g. central on-chip DSPresources for computationally intensive test routines would require the routingof high-speed signals across the chip and hinder concurrenttesting of functionblocks. It also complicates test program development as otherwise unrelatedbuilding blocks have to be synchronized.

Ideally, the block level tests should beautonomous, requireno external mea-


20 1. Introduction

surement equipmentand pass only a few parameters or signatures back to thetester to minimize test program development effort and ATE requirements. ABIST solution is favored over BOST approaches as self-test and self-calibrationfeatures of the fully assembled device are getting more and more customer focus.

Catastrophic and important parametric faults have to be detected quickly and re-liably. As RF PLLs are specified in the frequency domain, keyspectral param-eters have to be tested on-chip with the most important PLL parameters beingloop bandwidth, in-band noiseandmodulation mask test. The verification ofout-of-band phase noiseis not targeted here as a sensitivity better than -129 dBc(TX band) resp. -165 dBc (RX band) requires further work and an optimized RFdesign.

The additional test circuits have to besynthesizable digital blockswith only aminimum of analog circuitry to avoid yield reduction; a digital approach also ben-efits most of the high integration densities of modern technologies and enablesan easy reuse path for future chip generations. Onlyminimal modifications tocritical RF and analog paths should be made to avoid performance degrada-tions.

PLL BIST has to be implemented during the design phase and mayrequire sub-stantial chip area and design resources. These resources have to be compensatedfor by reduced test-time or improved testability. Typically, a test time reductionof 200. . . 500 ms for every 0.1 mm222 of additional chip area needs to be achievedwith the exact break-even point depending on technology, production volume,tester cost etc.

The goal of this work is to develop the next step on the roadmapto RF SOCsthat are fully testable on a digital tester, namely, an autonomous RF PLL self-testthat is controlled entirely via low-speed digital interfaces. It is organized in thefollowing way:

Chap. 2 reviews the underlying theory.

Chap. 3 describes the CUT, theΣ∆PLL, and how it is integrated into the DUT,a direct conversion transceiver.

Chap. 4 develops test concept and simulation strategy for RF PLLs.

Chap. 5 deals with on-chip stimulus generation.

Chap. 6 handles the PLL output response analysis.

Chap. 7 describes the SP-BIST implementation on a chip together with the CUTand analyzes measurement results.


What gets us into trouble is not what we don’tknow.

It’s what we know for sure that just ain’t so.

Mark Twain 2Fundamentals

Some concepts are reviewed that are used heavily throughoutthis work, specifi-cally angle modulation, discrete time signal processing, sigma-delta modulationand digital resonators.

2.1. Conventions

2.1.1. Symbols

The following symbols have been adopted throughout this work for denotingcontinuous-time (CT) / discrete-time (DT) signals and terms:

• Time is denoted byt, period byT

• Frequency is denotedf , angular frequencyω = 2π f and complex fre-quencys= σ + jω

• Continuous-time and continuous-value functions have no special prescriptor subscript, e.g.h(t)

• Capital symbols refer to frequency domain functions, i.e.h(t) vs. H( f ) orH(z)

22 2. Fundamentals

• Symbols referring to DT terms are denoted by the prescriptD as in Df =f TS

• Normalized frequencies are written in capital letters, i.e. F,Ω,S

• In the DT domain, (angular) frequency is normalized w.r.t. the samplingfrequencyfS, in the CT domain w.r.t. a center or corner frequencyfc

• Quantized terms have a subscriptQ, e.g.a1,Q

The DT systems regarded in this work operate at uniform sampling intervals andare shift-invariant1, permitting the use offrequency domainsignal-flow diagramswhere the unit delay is represented by the symbolz−1.

2.1.2. Definitions

The following definitions have been taken from [Joi08], terms in round bracketsare additions by the author:

Accuracy: Closeness of agreement between a measured quantity value and atrue quantity value of a measurand

Precision: Closeness of agreement between measured quantity values obtainedby replicate measurements on the same or similar objects under specifiedconditions

Uncertainty: Non-negative parameter characterizing the dispersion of the quan-tity values being attributed to a measurand (usually measured as standarddeviation)

(Measurement) Error: Measured quantity value minus a reference quantityvalue

Bias: Estimate of a systematic measurement error, i.e. componentof measure-ment error that in replicate measurements remains constantor varies in apredictable manner

Resolution: Smallest change in a quantity being measured that causes a percep-tible change in the corresponding indication

Reproducibility: Measurement precision under reproducibility conditions ofmeasurement (e.g. repeated measurements on different testers)

See also Fig. 4.4 for a visualization of accuracy and precision.

1Similar to LTI systems in the CT domain


2.2. Angle Modulation 23

2.2. Angle Modulation

The topic of angle modulation is especially important for this work for two rea-sons:

Signal: The measurement principle described in this work is built upon fre-quency modulation and demodulation of the device under test. Addition-ally, the DUT utilizes angle modulation for signal transmission.

Noise: In a VCO, voltage and current noise in resistive and active elements areconverted into phase fluctuations by a combination of additive and non-linear processes [LH00, RA00]. Amplitude deviations are usually sup-pressed resp. converted to phase or frequency noise by some form of am-plitude gain control or limiting in the oscillator. For thisreason, the qualityof the carrier signal for signal transmission in wireless system is usuallyspecified in terms of phase ("phase noise", "phase instability"), frequency("frequency instability") or time ("time interval error jitter"), all relating toangle modulation.

In the following, phase and frequency modulation are first described in the timedomain for general and for sinusoidal signals. Next, a linear approximation forsmall-angle modulation is derived to allow analysis in the frequency domain anddifferent measures of angle modulation in the frequency domain are given. Fi-nally, the effect of frequency division on angle modulationis explained.

2.2.1. Angle Modulation in the Time Domain

In systems with a fixed frequency and nearly constant amplitude A(t) ≈ A likeoscillators or digital blocks, nearly all noise powerPn near the carrier can becontributed to random phase fluctuationsφn(t). For this work, it is assumedthat amplitude noise contributionsPn,A are suppressed by amplitude control orlimiting, i.e.Pn = Pn,A+Pn,φ ≈Pn,φ in the frequency range of interest. The outputsignal of such a system can be approximated by a purely angle modulated signals(t) with carrier frequencyf0 and a constant amplitudeA (2.2.1):

s(t) = A(t)cos(2π f0t +φ(t)) ≈ Acos(2π f0t +φ(t)) = Acosφi(t) (2.2.1)

whereφ(t) is the phase deviation from the nominal phase 2π f0t. As an anglemodulated signal (2.2.1) has a constant envelope, its poweris alwaysP = A2/2.The sum of nominal (linear) phase and phase deviation is theinstantaneous phase

φi(t) = 2π f0t +φ(t) . (2.2.2)


24 2. Fundamentals

Its derivative is theinstantaneous frequency fi(t) (2.2.3). fi(t) is the sum ofnominal frequencyf0 and the frequency deviation∆ f (t). Bothφi(t) and fi(t) arehypothetical values that cannot be measured directly.

fi(t) =1

2π

dφi(t)dt

= f0 +1

2π

dφ(t)dt

= f0 +∆ f (t)

⇔

φi(t) = 2π

∫ t

−∞fi(τ)dτ

= 2π f0t +2π

∫ t

−∞∆ f (τ)dτ

= 2π f0t +φ(t)

(2.2.3)

Relative frequency deviation y(t) from the nominal frequencyf0 is defined by

y(t) :=fi(t)− f0

f0=

∆ f (t)f0

=1

2π f0

dφ(t)dt

with [y] = 1. (2.2.4)

When the message or modulating signalmPM(t) and thephase deviationφPM(t)=kPMmPM(t) have a linear relationship, the modulation is calledphase modulation(PM) andkPM phase modulation gain. The resulting instantaneous frequencyand phase and frequency deviation are given in (2.2.6). The frequency deviationof PM is proportional to the differential of the modulation signal, hence it is alsoproportional to the modulation frequencyfm (for sinusoidal modulation).

φPM(t) = kPMmPM(t)

fi,PM(t) = f0 +1

2π

dφPM(t)dt

= f0 +kPM

2π

dmPM(t)dt

yPM(t) =kPM

2π f0

dmPM(t)dt

(2.2.5)

When modulation signalmFM(t) and thefrequency deviation∆ fFM(t)= kFMmFM(t)are linearly related, the modulation is calledfrequency modulation(FM), yield-ing the instantaneous frequency and the phase and frequencydeviation in (2.2.6).kFM is the frequency modulation gain. Phase deviation of FM is inversely pro-portional to the modulation frequency for sinusoidal modulation as it is createdby the integral of the modulation signal.

fi,FM(t) = f0 +∆ fFM(t) = f0 +kFMmFM(t)

yFM(t) =∆ fFM(t)

f0=

kFMmFM(t)f0

φFM(t) = 2π

∫ t

−∞∆ fFM(τ)dτ = 2πkFM

∫ t

τ=−∞mFM(τ)dτ

(2.2.6)

A comparison of (2.2.5) and (2.2.6) reveals that FM and PM cannot be distin-guished from the modulated signal: A phase modulation withmPM(t) and a fre-quency modulation withmFM(t) produce the same phase deviation under the



condition

mPM(t) = 2πkFM

kPM

∫ t

τ=−∞mFM(τ)dτ . (2.2.7)

This relationship is utilized in the device-under-test (Sec. 3.2) asindirect PMwhere the carrier is frequency modulated by the differentiated modulation signal.

2.2.2. Sinusoidal Angle Modulation

In the following, the special case of sinusoidal frequency modulation is describedthat can be solved in closed form in contrast to most other modulation cases:A carrier, frequency modulated by a sinusoidal modulation signal mFM(t) =Am,FM cosωmt has the phase and frequency deviation shown in (2.2.10) - (2.2.9).

fi,FM(t) = f0 +∆ fFM(t) with ∆ fFM(t) = kFMAm,FM cosωmt (2.2.8)

yFM(t) =∆ f (t)

f0=

∆ fFM

f0cosωmt = ycosωmt (2.2.9)

φFM(t) = 2π

∫ t

τ=−∞∆ fFM(τ)dτ =

kFMAm,FM

fm︸︷︷︸:=φ

sinωmt (2.2.10)

The ratio of peak frequency deviation∆ f and modulation bandwidthBm (= fmin this case) for analog modulation signals2 is calledfrequency modulation in-dex3 β f (2.2.11) [VDP30]. Another common measure is the peak normalizedfrequency deviationy (2.2.11):

y :=∆ ff0

and β f :=∆ fBm

=∆ ffm

=kFMAm,FM

fm= φ (2.2.11)

with[β f]= 1 and

[φ]

= 1 rad,

(2.2.11) also shows that the FM modulation index has the samevalue as the peakphase deviation measured in rad. As derived in (2.2.7), a PM signal mPM(t) cre-ates the same modulated signalsFM(t) = sPM(t) = s(t) as an FM signalmFM(t)

2The modulation index of digital modulation signals is usuallydefined as the maximum phasedeviation over one symbol period.

3Phase modulation indexβp is defined in a similar way by the ratio of peak phase deviation andmodulation signal bandwidth.


26 2. Fundamentals

when

s(t) = Acos(ω0t +φ(t)) = Acos(

ω0t + φ sinωmt)

with

mPM(t) = 2πkFM

kPM

∫ t

τ=−∞mFM(τ)dτ = Am,PM sinωmt

and Am,PM =Am,FMkFM

kPM fm=

∆ fkPM fm

=β f

kPM=

φkPM

. (2.2.12)

In general, the spectrum of angle modulated signals cannot be given in closedform. However, sinusoidal and small-angle (see below) phase modulated4 signalscan be expanded into an infinite sum of cosine signals, (2.2.13), allowing easycalculation of the spectrum.

s(t) = Acos(ω0t +φ(t)) = Acos(

ω0t + φ sinωmt)

= A∞

∑n=−∞

Jn(φ)cos(ω0t +nωmt) (2.2.13)

whereJn(φ) are Bessel functions of the first kind with integer ordern. When theangle modulation consists of multiple tones, results get much more complicated.For the case of FM with two sinusoids, Bessel expansion yields (2.2.14) [Sch],containing all kind of intermodulation products between the two modulation fre-quencies.

mFM(t) = Am1,FM cosωm,1t +Am2,FM cosωm2t

⇒ φFM(t) = 2π

∫ t

−∞kFMmFM(t)

= φ1sinωm1t + φ2sinωm2t with φi =kFMAmi,FM

fmi

⇒ sFM(t) = Acos(ω0t +φFM(t))

= Acos(

ω0t + φ1sinωm1t + φ2sinωm2t)

= A∞

∑l=−∞

Jl (φ1)∞

∑n=−∞

Jn(φ2)cos(ω0t + lωm1t +nωm2t) (2.2.14)

4FM signals first have to be transformed into the PM form using (2.2.7).



2.2.3. Small-Angle Approximation

Closed-form analysis of most angle modulated signals is either impossible orgives only limited insight as in (2.2.14). However, (2.2.13) can be simplified forsmall modulation anglesφ < 0.25 rad: The carrier amplitude is attenuated by lessthan two percent,J0(φ) ≈ 1. Only the first sidebands have relative amplitudesexceeding one percent and can be approximated byJ±1(φ) ≈ ±φ/2. Higherorder sidebands are neglected,J|n|>1 ≈ 0, yielding thesmall angle approximation(2.2.15):

sFM(t) ≈ A

[cosω0t ±

φ2

cos(ω0t ±ωmt)

](2.2.15)

= Aℜ

ejω0t

(1+

φ2

ejωmt − φ2

e−jωmt

)(2.2.16)

Its complex phasor form (2.2.16) is visualized in Fig. 2.3. Except for the phaseof −π of the lower sideband, small-angle approximation takes thesame form asamplitude modulation, i.e. it can also be described as a linear modulation.

2.2.4. Bandwidth of Angle Modulation

(2.2.15) shows that small-angle frequency modulated signals occupy a bandwidthof BFM ≈ 2Bm = 2 fm (Fig. 2.1a). Hence, this case is also callednarrowbandapproximation.

In contrast, large-angle FM withφ ≫ 1 generates many tones around the carrier,spaced byfm (Fig. 2.1b). Their amplitudes, given by (2.2.13), decreaserapidlyfor offsets f > ∆ f . The resulting bandwidth isBFM ≈ 2∆ f .

For most practical applications, only theN99 sidebands required for transmissionof 99% of the normalized signal powerPFM are regarded:

+N99

∑n=−N99

J2n(φ) = 0.99 (2.2.17)

The required number of sidebands directly depends on the modulation index,N99 ≈ ⌈φ⌉+ 1, leading to the approximation for FM bandwidth known asCar-son’s bandwidth rule(2.2.18) that applies for small and large-angle FM [Vid05].

BFM ≈ 2(⌈φ⌉+1

)fm = 2

(∆ f + fm

)(2.2.18)


28 2. Fundamentals

f0

S (f)FM

m+f

f f

S (f)FM

f0f

S (f)

m+f

f

BFMBy

m

(a)

(b)

(a) (b)

FM

Figure 2.1.: One-sided spectra of frequency deviationSy,FM( f ) and signalSFM( f ) forsmall-angle (a) and large-angle (b) sinusoidal FM

2.3. Phase Noise Metrology

In this work, spectra are represented using only positive frequencies (one-sided)as spectra of real-valued signals are symmetric aroundf = 0 (Fig. 2.2). Thepower spectral density (PSD) of the one-sided representation has to be twice aslarge as the two-sided representation to obtain the same total signal power.

This must not be confused withsingleanddouble-sideband(SSB / DSB) repre-sentation: Spectra of modulated carriers are symmetric around the carrier atf =f0 for real baseband signals and pure amplitude (even symmetry) or phase/fre-quency modulation (odd symmetry). In contrast, complex baseband signals andcombined amplitude / phase modulation schemes produce bothodd and evencomponents, yielding asymmetric sidebands. In the following, it is assumed thatthe signal under analysis is only angle-modulated in the frequency range of in-terest. In practical VCOs and PLLs, this is achieved by some form of amplitudecontrol or limiting.

Theupper sidebandcontains signal components above the carrier frequency,f0+fm, signal components below the carrier frequency,f0− fm, constitute the lowersideband. The frequency variablefm denotes themodulation frequencyor offsetfrequencyfrom the carrier, also calledFourier frequency.

In the frequency domain, signals are usually specified bypower spectral densities(PSD). The PSDS( f ) of a signal resp. processs(t) is obtained by the Fourier


2.3. Phase Noise Metrology 29

m0f +f0−f +fm−f0mf −f0 f +f0 mf0

|S (f)|

f

|S (f)|

f 0f

N /8A20

2A /4

2β2A /16f

A20N /4

2A /82βf

A /22

0 00

Double sidedSingle sided

Figure 2.2.: One-sided and two-sided spectra of the signals(t)

transform of its auto-correlation function (ACF)ρss(τ) [Lük85]

ρss(τ) −• S( f ) with (2.3.1)

ρss(τ) = s(t)s(t + τ) = limT→∞

12T

∫ T

−Ts(t)s(t + τ) dt (2.3.2)

=1T1

∫ T1

0s(t)s(t + τ) dt for T1 periodic signals and 0≤ τ ≤ T1 .

ACF and one-sided PSD of a sinusoidal signals(t) = Amsinωmt are easily de-rived from (2.3.2):

ρss(τ) =A2

m

2cosωmt −• S( fm) =

A2m

2δ ( fm) with 0≤ fm < ∞ (2.3.3)

A similar calculation yields the PSD of the small-angle FM signal (2.2.15):

sFM(t) ≈ A

[cosω0t ±

φ2

cos(ω0t ±ωmt)

]

⇒ |SFM( f )| ≈ A2

2

δ ( f0)+

(φ2

)2

δ ( f0± fm)

(2.3.4)

A narrowband noise signal can be described by white noise with PSDN0, filteredby a narrow bandpass with center frequencyfm, bandwidthB and gainH( fm),ACF and PSD of , [Lük85, p. 193f] are:

ρnn(τ) = 2N0BH( fm)sinc(πBτ)cos(2π fmt) ≈ 2N0BH( fm)cos(2π fmt) for πBτ ≪ 1

−• Sn( fm) ≈ 2N0BH( fm)δ ( fm) with 0≤ fm < ∞ (2.3.5)


30 2. Fundamentals

(2.3.3) and (2.3.5) show that a sinusoid with frequencyfm and a narrowbandnoise signal centered at the same frequency have the same ACFand PSD when

Ps =A2

m

2= 2N0BH( fm) = Pn.

On average, the narrowband noise signal can be represented by a sinusoid withthe same power. Due to the linearity of small-angle modulation, the spectrumcreated by general modulation signal with spectrumH( f ) can be calculated usingsuperposition.

The FM spectrum of a signal with phase deviationφ(t) can be calculated from itsFourier transformΦ( f ): The spectrum due to each individual frequency compo-nent can be approximated by (2.2.15) as long as the (linear) small angle approxi-mation is valid, yielding the complete spectrum by superposition (2.3.7).

φFM(t) = 2πkFM

∫ t

τ=−∞mFM(τ)dτ

−• ΦFM( f ) =MFM( f )

j ffor MFM(0) = 0 (2.3.6)

⇒ |SFM( f0 + fm)|P

≈ Φ2( fm)

4=

(MFM( fm)

2 fm

)2

(2.3.7)

A

A

f

A

0

S(f)

f +f0 mf −f f0 m

A

(a) (b) / 2A = A∆

φ / 2A

φ 22/ 8

/ 22

0ω0ω

+ω m

+ω m

−ω m

t( )φ

φ / 2φ

t( )φ

φ

Figure 2.3.: Phasors for small-angle PM/FM, DSB (a) and SSB (b) representation

Phase fluctuations can be measured by two fundamentally different procedures,either bydirect spectral analysisof the signal or by priordemodulation, also



calleddiscrimination. These procedures are related to SSB and DSB representa-tion of the modulation [Pla00, p. 189ff]:

2.3.1. Double-Sideband Representation

Spectra of angle-modulated signals can be obtained from measurements of thephase resp. frequency deviation, requiring demodulation of the signal. Practicalmeasurements use detectors with an output voltage that is proportional to thephase or frequency deviation. The deviation is measured against an externalreference or a copy of the signal itself (self-referenced).The amplitude of thecarrier is either suppressed (clipping detectors) or needsto be eliminated fromthe results by calibration [Pla00].

Phase Instability

Phase instability Sφ ( fm) is defined as the one-sided PSD of the phase deviationφ(t) −• Φ( fm).

∣∣Sφ ( fm)∣∣= Φ2( fm)

2(2.3.8)

Sφ ( fm) has the unit rad2/Hz. The pseudo-unitdBrad / Hz is defined in this workto expressSφdB( fm) in a convenient logarithmic scale:

∣∣SφdB( fm)∣∣(dBrad / Hz) := 10log

∣∣Sφ ( fm)∣∣

rad2/Hz(2.3.9)

Strictly speaking, "per Hz" relates to the argument of the logarithm instead ofthe logarithm itself - doubling the bandwidth does not give twice the dBrad /Hz value. However, this sloppy use is widely adopted in literature, especially inconjunction with phase noise (see below) and is adopted hereas well.

The phase instabilitySφ ,FM( fm) of a signalsFM(t) frequency modulated bymFM(t) is derived from (2.2.6):

φFM(t) = 2πkFM

∫ t

τ=−∞mFM(τ)dτ

⇒ |Φ( fm)| = kFMMFM( fm)

fmfor M(0) = 0

⇒∣∣Sφ ,FM( fm)

∣∣= k2FM

M2FM( fm)

f 2m

for M(0) = 0 (2.3.10)


32 2. Fundamentals

The phase instability of sinusoidal FM (2.2.12) is derived in (2.3.11).

φFM(t) =kFMAm,FM

fmsinωmt = φ sinωmt

⇒∣∣Sφ ,FM( fm)

∣∣= Φ2( fm)

2=

β 2f

2δ ( fm) =

φ2

2δ ( fm) (2.3.11)

Normalizing the PSD of a small-angle modulated signal (2.3.4) with respect toits powerP = A2/2 shows the equivalence to its phase instability (2.3.12):

|SFM( f0 + fm)|P

= δ ( f0)+

(φ2

)2

δ ( f0± fm) = δ ( f0)+

∣∣Sφ ,FM( fm)∣∣

2(2.3.12)

Frequency Instability

Frequency instabilitySy( fm) is the single-sided PSD of the relative frequencydeviationy(t) with the unit rad2/Hz resp. the pseudo-unit dBrad / Hz.

The relationship (2.3.13) between phase and frequency instability is derived us-ing (2.2.4) and illustrated in Fig. 2.4 for a typical PLL spectrum: Near the carrier,phase deviationSφ ( fm) drops with -30 dB/dec, followed by a region of constantin-band noise. Outside the loop bandwidth, phase noise is dominated by theVCO, decreasing with 20 dB/dec. The slope of theSy( fm) segments in Fig. 2.4 is20 dB/dec larger than the segments ofSφ ( fm) due to thef 2

m term in (2.3.13).

Sy( fm) =f 2m

f 20

Sφ ( fm) (2.3.13)

2.3.2. Single-Sideband Representation

A single sideband of an purely angle-modulated signal with carrier frequencyf0can be downconverted to an intermediate frequency with a mixer in one or morestages (Fig. 6.1). Fig. 2.3 shows that this restriction to a single sideband convertshalf of the phase fluctuations to amplitude fluctuations with∆A = Aφ/2. Thisphase-to-amplitude conversionenables measurements in the amplitude domain.The SSB amplitude noise power after conversion isA2φ2/4.

The ratio of this SSB noise power (due to phase fluctuations only) to the totalsignal power (carrier and sidebands) in a 1 Hz bandwidth is called phase noise



1 Hz

y

f1

f f

S (f)

f0

S(f)

f

f +f0 m c)a) 1fb)

1 Hz

f1 m

1 Hz

S (f)/2

m

f

L (f)

ff

φ

m

Figure 2.4.: PSD of signalS( f ) (a), phase noiseL ( f ) and phase deviationSφ ( f ) (b) andfrequency deviationSy( f ) (c)

L ( fm). It is usually specified in the pseudo-unit dBc / Hz, i.e. dB relative tothe carrier. The same caveats apply for the use of this pseudo-unit as explainedabove for phase instability.

L ( fm) =Pn,φ ( f0 + fm)

Ptot=

∫ f0+ fm+1Hz

f0+ fmS( f )d f

Ptot

≈ S( f0 + fm)/2·1HzA2/2

≈∣∣Sφ ( fm)

∣∣2

(2.3.14)

Note: Recent standards [IEE08] redefine phase noise via the phase instability as

Lnew( fm) ≡ Sφ ( fm)/2 . (2.3.15)

This definition avoids the small angle limitation of the conventional phase noisedefinition (2.3.14) that is no longer valid near the carrier.Both definitions yieldidentical values (but not units!) for small phase deviations when the small-angleapproximation (2.2.15) is valid,Lnew( fm) ≈ L ( fm).

Note: This work does not address the important issue of how the impact of theinevitable amplitude noise in active and passive components upon the oscillatorphase fluctuations can be minimized. To some extent, the amplitude noise is in-dependent of the oscillator amplitude (most obvious for additive noise). Hence,one well-known design strategy is to maximize the VCO amplitude in order tominimize the noise-to-carrier ratio. At first glance, thereseems to be a contra-diction to (2.3.14) and (2.3.15) which claim that the phase instability does notdepend on the carrier amplitude. However, the definition of phase noise containsthe single-sideband noise power that is related to the phaseinstability via thesmall signal approximation.


34 2. Fundamentals

The relationship between different measures for phase / frequency stability isdemonstrated for the example of the reference spur from Fig.4.9 with ∆ f =265Hz, fm = 26 MHz andf0 = 3.434 GHz :

y =∆ ff0

= 7.72·10−8 ⇒ Sy( fm) =y2

2= −145.2dBrad/Hz

β f = φ =∆ ffm

=y f0fm

= 1.02·10−5

⇒ Sφ ( fm) = Sy( fm)f 20

f 2m

=φ 2

2= −102.8dBrad/Hz

andL ( fm) =Sφ ( fm)

2= −105.8dBc/Hz (2.3.16)

GSM applies a form of PM where the modulation signal is filtered using Gaus-sian minimum shift keying (GMSK) for high spectral efficiency. The modu-lation bandwidthBm is determined by the GSM specifications: The symbolrate is 1/Tsym = 270.833 kbit/s, the ratio of modulation bandwidth and sym-bol rate is specified asBmTsym = 0.3, resulting in a modulation bandwidth ofBm = 0.3/Tsym= 81.25 kHz. Maximum frequency deviation is derived from thespecified modulation indexβ f = 0.5:

β f = 2∆ f Tsym ⇔ ∆ f = 1/4Tsym= 67.71kHz

2.3.3. Frequency Modulation and Division

When the frequency of an FM signal is divided byN, a phenomenon is observedthat is well known in PLL and RF design: The carrier frequencyis reduced by afactor ofN as expected, but the distance of the sidebands from the carrier remainsunchanged. This effect is independent from the physical implementation (e.g. adigital divider or an analog mixer) and is best explained in the time domain: Thepositions of the FM signal edges relative to the unmodulatedposition (the phase)are modulated in time. Removing e.g. every other edge (division by 2) does notchange the "rhythm" of the modulation as long as the removingof the edges doesnot create aliasing. This condition is fulfilled for narrowband modulation wherethe spectral components of the sidebands have a much lower frequency than thecarrier.

Theabsolutetiming fluctuation of the edges is not changed by division. However,as the carrier period is increased byN, the amount of fluctuationrelative to theperiod (phase deviation or relative jitter) is decreased bythe same factor.



These effects can be demonstrated for the case of a carrier with frequencyω0,frequency modulated by a sine wave of frequencyωm

5, creating a peak frequencydeviation∆ω and a peak phase deviationφ = ∆ω/ωm.

sFM(t) = Acos

(ω0t +

∆ωωm

sinωmt

)

The signal has an instantaneous phaseφi(t):

φi(t) = ω0t +∆ωωm

sinωmt (2.3.17)

After division byN, instantaneous phaseφi,N(t) and frequencyωi,N(t) are:

φi,N(t) =φi(t)

N=

ω0tN

+∆ω

Nωmsinωmt (2.3.18)

ωi,N(t) =ωi(t)

N=

dφi,N(t)dt

=ω0 +∆ω cosωmt

N(2.3.19)

For φ = ∆ω/ωm≪ 1, small-angle approximation (2.2.15) can be used to analyzethe effect of division upon the sidebands:

sFM,N(t) = Acos

(ω0tN

+∆ω

Nωmsinωmt

)

≈ A

[cos(ω0t

N

)± ∆ω

2Nωmcos(ω0

N±ωm

)t

](2.3.20)

(2.3.20) shows:

• Carrier frequencyf0, peak phase and frequency deviation,φ and∆ f , arereduced byN

• Relative frequency deviationy(t) = ∆ f (t)/ f0 remains unchanged

• Sidebands still are a distance of± fm from the carrier

• The level of the sidebands are reduced byN and hence the power of mod-ulation sidebands and phase noiseL ( f ) are reduced byN2 (when thecarrier amplitudeA remains unchanged)

Note: This simple analysis works only for narrowband modulation.In general,the division should be regarded as asubsamplingprocess [Ter05] that folds backwide-band noise into the baseband.

5This could also be a narrowband noise signal.


36 2. Fundamentals

2.4. Spectral Estimation of Simulation Data

The goal of spectral estimation is to describe the spectral power distribution of asignal, based on a finite set of data. This section reviews thetheory of spectralanalysis using periodograms.

Power Spectral Density Estimation

The power spectral density (PSD) of a stochastic processX is defined by theFourier transform of its auto-correlation function (ACF).A random discrete sig-nal xN with finite lengthN can be seen as a realization ofX from which its trueACF and PSD can only beestimated. It can be shown that the magnitude squaredFourier transform ofxN, a so calledperiodogram, is an estimation for the truePSD ofX [KK06].

Calculating the periodogram of a long sequencexN is very computationally in-tensive which is avoided byaveragingthe periodograms ofK shorter slicesx i

L oflengthL < N (Fig. 2.5). Anaveraged periodogram[PM92] reduces the varianceand spectral resolution of the estimate by the factorK at the same time.

0 L-1 2L-1L N-1-L N-1x [k]

x [k]0L x [k]1

L x [k]K-1L

N

Figure 2.5.: Basic slices of the signalxN

The relationship between spectral resolution and varianceis improved by Welch’smethod [Wel67] ofaveraging modified periodograms, calculated fromoverlap-ping windowed slices xiL (Fig. 2.6)

ΓW(ν) =1

∑L−1k=0 w2[k]︸︷︷︸

window power

1

K ′

K′−1

∑i=0

∣∣∣∣∣L−1

∑k=0

xiL[k]w[k]e−2πjkν

∣∣∣∣∣

2

︸︷︷︸periodogram of windowed slicei

(2.4.1)

whereK′is the total number of slices. The averaged periodogram is normalized

by the power of the window functionw[k] for unbiased results [KK06]. Thisalgorithm is used in the Matlab scripts for spectral estimation of the VHDL -simulations.


2.4. Spectral Estimation of Simulation Data 37

0

x [k]

N-1

N

x * w[k]0L

x * w[k]1L

Figure 2.6.: Overlapping windowed slices of the signalxN

Narrowband and Wideband Signals

The powerPS of a narrowband signal is concentrated in one spectral line and canbe read directly from the display. In contrast, the powerPN of a broadband signallike noise is distributed overM frequency bins. The displayed power per bin istherefore given by (2.4.2).

Pbin = PN/M or Pbin [dB] = PN [dB]−10logM (2.4.2)

The relationship between noise powerdensity P′N (specified for a bandwidth of1 Hz) and displayed power per bin depends on the resolution bandwidthRBWofthe spectral estimation:

Pbin = P′NRBW or Pbin [dB] = P′

N [dB] +10logRBW/1Hz (2.4.3)

with RBW= BNB/M

whereBN is the equivalent noise bandwidth expressed in bins (see next section)andB is the total bandwidth. For anNFFT -point FFT with a rectangular window,BN = 1, B = fS/2 andM = NFFT/2, resulting inRBW= fS/NFFT .

Extracting Noise and Phase Noise from DT Period Data

Spectral estimation of a DT sequence ofamplitudevalues can be performed di-rectly with the periodogram methods described above. When phase noise has tobe estimated from a DT sequence ofperiodvalues, produced e.g. by the simpli-fied DT VCO model described in Sec. 4.5.2, some pre-processing is needed:

The DT period valuesck fluctuate around the average periodT0. The cumula-tive sum of the periods, scaled with 2π/T0 gives the DT approximation to theinstantaneous phaseφi [N] = 2π/T0 ∑N

k ck.

Phase fluctuationsφ [k] = c′k are estimated from the instantaneous phaseφi [N] byremoving the linear phase 2π f0t (Fig. 2.8). This is achieved in Matlab by spec-ifying the option "detrending" for the PSD which is performed using Welch’s


38 2. Fundamentals

Figure 2.7.: Displayed PSD of noise signal [Kes05]

1

kC

3C

2C

NC

4C5C

Remove linear phase

Linear Detrending

k1

C 4C

5C

2C 3C

NC ’’

’

’’

’

2πΣ T / Tk 0

Figure 2.8.: Derivation of phase fluctuations from the VCO periods

averaged, modified periodogram method. By default, Matlab uses a Hammingwindow with an equivalent noise bandwidth ofBN = 1.37 bins [Har78] and scalesthe PSD with 1/BN to give a correct result for wideband signals. This is reversedin the Matlab routine below for proper display of singles tones. The factor isincluded in the reported resolution bandwidth to obtain correct noise power den-sities.

Unfortunately, the original Matlab script taken from [Kun05] incorrectly assumesa Hann(ing) window with an equivalent noise bandwidth ofBN = 1.5 bins, thisvalue has been used through all simulations in this work. As aconsequence, theresolution bandwidth and all simulated values for single tones are too large by1.5/1.37 = 1.095 or 0.4 dB.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%


2.5. Sampling and Quantization 39

% psd_pe r i od .m%% C a l c u l a t e Power S p e c t r a l D e n s i t y f rom p e r i o d da ta%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%%%%%%%%% Def ine c o n s t a n t s %%%%%%%%%%%%%nread = −1; % read a l l samples

% Load Data F i l e g e n e r a t e d by VHDL S i m u l a t i o n[ p e r i o d s ] = t e x t r e a d ( ’ p e r i o d _ d a t a . t x t ’ , ’%f ’ , n read ) ;

p e r i o d s = p e r i o d s / 1 .0 e15 ;% s c a l e f o r f sN_sample = l eng th ( p e r i o d s ) ; % number o f samples

% C a l c u l a t e average and s tanda rd d e v i a t i o n o f p e r i o d da ta% and phase , f i n d t h e maximum phase e r r o rT_m = mean( p e r i o d s ) ; % C a l c u l a t e average per iod ,J_m = s td ( p e r i o d s ) ; % p e r i o d j i t t e r ( StdDev o f p e r i o d ) ,s t d _ d p h i = J_m / T_m;% phase e r r o r ( StdDev o f phase ) andmax_dphi = max( abs( p e r i o d s−T_m ) ) / T_m; % max . phase e r r o r

n f f t = f l o o r ( N_sample / 4 ) ; % number o f FFT b i n swinLen = n f f t ; % Let window l e n g t h = NFFTo v e r l a p = f i x ( n f f t / 2 ) ; % Let s e c t i o n s o v e r l a p by NFFT / 2winNBW = 1 . 5 ; % e q u i v a l e n t n o i s e bandwid th o f Hann window

% C a l c u l a t e i n s t a n t a n e o u s phase v e c t o r :cum_phi = 2 ∗ p i ∗ cumsum( p e r i o d s ) / T_m;

% C a l c u l a t e PSD wi th l i n e a r de−t r e n d i n g% Data i s s p l i t i n t o N_sample / (2∗ n f f t ) s e c t i o n s[ Sphi , f ] = psd ( cum_phi , n f f t , 1 / T_m , winLen , ove r l ap , ’ l i ne a r ’ ) ;

% S ca le PSD wi th NFFT and winNBWSphi = winNBW ∗ Sphi / n f f t ;

N_f = l eng th ( f ) ; % number o f f r e q u e n c y p o i n t s = n f f t / 2 + 1rbw=winNBW / ( T_m∗ n f f t ) ; % r e s o l u t i o n bandwid th i n Hzlog_rbw = 10∗ l og10( rbw ) ;

% P l o t Phase Noise ( sem i l og )f i g u r e ( 1 ) ;semi logx( f ( 2 : N_f ) , 10∗ l og10( Sphi ( 2 : N_f ) ) ) ;x l a b e l ( ’ O f f s e t Frequency from C a r r i e r ( Hz ) ’ ) ;y l a b e l ( ’S_ \ ph i ( dB / Hz ) ’ ) ;t i t l e ( ’VCO Power S p e c t r a l Dens i t y ’ ) ;

2.5. Sampling and Quantization

Digital signal processing operates on signals that are discrete-time (sampled) anddiscrete-valued (quantized):


40 2. Fundamentals

2.5.1. Sampling

Sampling createsimagesof the original signal around multiples offS that overlapwhenB > fS/2 (Nyquist frequency), folding back frequency components abovefS/2 into the base-band. These components cannot be separated from the originalsignal. This process is calledaliasingand can only be avoided by band-limitingthe original signal with ananti-aliasing filterto B≤ fS/2.

Hence, a sampled signal may be recovered without losses as long as theNyquistcriterion is fulfilled:

A signal must be sampled at a ratefS equal to or greater than twiceits bandwidthB in order to preserve all the signal information.

2.5.2. Quantization

Quantization reduces the infinite amplitude resolution of the analog signal to adiscrete number of levels which inevitably adds distortions that cannot be fullyremoved. In general, it is very difficult to predict the levelof distortion as itdepends not only on the quantization step size∆Q but also on the signal amplitudeand statistics.

Note: A physical interpretation of the numeric quantizer output is obtained byscaling the output with the quantization step size∆Q, resulting in a nominal quan-tizer gain of 1.

The quantization errorqe(n) is in the range6 ±∆Q/2 for the case ofrounding. Formulti-bit quantizers and sufficiently large signal amplitudes,qe can be approxi-mated by a stochastic process with uniform amplitude probability density 1/∆Q

and a constant power spectral density (PSD)N′q( f ) in the interval(− fS/2, fS/2).

Outside this interval the noise spectrum repeats due to sampling. The varianceσ2

e of such a process is given by (2.5.1).

σ2e = ∆2

Q/12= Nq(B = fS/2) (2.5.1)

The variance equals the quantization noise powerNq( fS/2) within the Nyquistbandwidth, obtained by integrating the quantization noisePSD N′

q( f ) over(− fS/2, fS/2). This allows the calculation ofN′

q (2.5.2).

Nq(B = fS/2) =∫ fS/2

− fS/2N′

q( f )d f = N′q( f ) fS ⇒ N′

q( f ) =∆2

Q

12fS(2.5.2)

6For truncation,−∆Q < qe ≤ 0


2.5. Sampling and Quantization 41

The peak signal-to-quantization-noise ratio (SQNR) is calculated from the power

/2S

qN’ (f)

f

S/2−f −B B f

Figure 2.9.: Spectral density of quantization noise

Sof a signal exercising the full signal range (FSR) of the quantizer and quantiza-tion noise powerNq. The SQNR for a sine signal with a peak-to-peak amplitudeApp = FSRand a quantizer with 2N quantization levels is given by

App = (2N −1)∆Q ⇒ ∆Q =App

2N −1and Nq =

∆2Q

12(2.5.3)

⇒ S=A2

pp

8=

(2N −1

)2 ∆2Q

8≈

22N∆2Q

8(2.5.4)

⇒ SQNR= 10logSNq

≈ 10log22N 812

= N ·6.02 dB−1.76 dB (2.5.5)

In quantizers with only a few bits (N < 5), quantization gain and quantizationerror are strongly correlated to the signal, creating distortions (harmonics, inter-modulation). The resulting degradation of SQNR can be included in (2.5.5) viaa reduced maximum input amplitude [vdP94, p. 13]:

App =

(2N −2+

4π

)∆Q (2.5.6)

⇒ SQNR= 10logA2

pp

8NqdB = 10log

32

(2N −2+

4π

)2

dB (2.5.7)

2.5.3. Oversampling

TheSQNRof a quantized signal can be improved by reducing the quantizationstep size∆Q but this is often more difficult to achieve thanoversampling, i.e.sampling a signal with a higher rate than the Nyquist frequency ( fS > 2B). Asthe total quantization noise powerNq = σ2

e does not depend on the sampling rate,the quantization noise PSDN′

q( f ) is reduced by oversampling (Fig. 2.9). Hence,


42 2. Fundamentals

the total quantization noise power in the baseband (−B < f < B) depends on theoversampling ratioOSR= fS/2B. For the optimum case of a brickwall filter withfc = B (Fig. 2.9), theSQNRis improved by the oversampling ratioOSR= fS/2B(2.5.8).

Nq(B) =∫ B

−BN′

q( f )d f =∆2

Q

122BfS

= Nq( fS/2)2BfS

=Nq( fS/2)

OSR(2.5.8)

On a logarithmic scale, this means doubling theOSRimproves theSQNRby10logOSR= 3 db, equivalent to increasing the resolution by half a bit.

Another advantage of oversampling is the relaxed requirements for anti-aliasingand reconstruction filters which remove frequency components abovefS/2: InNyquist rate converters, the signal bandwidthB is just below fS/2, requiringsteep analog filters. This is not needed in an oversampling architecture whereB ≪ fS/2. Signal and quantization noise betweenB and fS/2 can be removedlater on in the digital domain.

2.5.4. Subsampling and Downsampling

As the Nyquist criterion only requires that the signalbandwidthis lower than theNyquist frequencyfS/2 thesignal frequencymay be far higher than the samplingfrequency. The signal frequency rangefsig has to fall into asingleNyquist zone(N−1) fS/2 < fsig < N fS (see Fig. 2.10). If this condition is met, the sampledimage of the signal contains all the information of the original signal. When theoriginal signal lies in an even Nyquist zone, the order of frequency components isreversed which can be reversed easily in digital processing. Using a sampling fre-quency below the highest signal frequency (i.e. sampling signals above the firstnyquist zone) is calledundersamplingor subsampling, independent of whetherthe Nyquist criterion is fulfilled or not. In contrast, the term downsamplingisused in this work to denominate the whole process of samplinga signal aroundfsig with a sampling frequencyfS after limiting the signal bandwidth tofS/2[CT92, pp. 1–25].

Decimation7 by a factor ofN operates on a DT signal by keeping 1 out ofNsamples and discarding the others, yielding an output sampling rate offS/N. Thishas the same effect as undersampling a CT signal, consequently, the bandwidth ofan DT signal also has to be limited tofS/2N before decimation to avoid aliasing.

7The term has its origins in the Roman method of punishment where agroup of men were selectedat random and every tenth one was killed.


2.6. Sigma-Delta Modulation 43

Figure 2.10.: Subsampling and frequency translation between nyquistzones [Kes05]

Signals with a high ratio between signal frequency and signal bandwidth (asin the case of the response analysis system in Chap. 6) can be processed veryefficiently by downsamplingresp.decimationas the signal processing can beperformed at a much lower sampling rate.

2.6. Sigma-Delta Modulation

Originally, Sigma-Delta Modulation (Σ∆M) had been developed to reduce thebandwidth for data transmission bydifferential predictivecoding: When thesampling frequencyfS is much higher than the signal bandwidthB, transmis-sion bandwidth can be saved by transmitting only the changes("delta") betweensamples of the signal (Fig. 2.11 and Fig. 2.12) [Kes05], requiring only one bit inits simplest form.

In this work (with very few exceptions) only one-bit quantization and DACs areused as the inherent monotonicity of a one bit DAC allows implementation inlow-cost CMOS technologies. This feature in conjunction with the mainly digitalarchitecture enabled the immense success ofΣ∆M in integrated circuits.

The signal is demodulated by integrating the delta samples and converting themback to the analog domain. This method, calledDelta modulation, is improved byintegrating ("sigma") the input signal, yieldingSigma-Delta modulation(SDM,


44 2. Fundamentals

Q

Q

Q

Qf

−∆

+∆

+∆

−∆−s(t) s(t)

Integrator LP−Filter

d[n]

DAC

Modulator

Quantizer

Integrator

Sampler

DAC Demodulator

δ

Figure 2.11.: Delta modulation and demodulation

1 1 11 1 11 1 1 1 1 1 1 111 10 0 0 0 0 0 0 0 0

∆Input Signal

(Integrated)

TS

Feedback integrator output

(Sigma−) Delta modulated data stream

Granular Noise

QSlopeOverloadDistortion

Figure 2.12.: (Sigma)-Delta modulation signal forms

Fig. 2.13). Due to the integration, low-frequency signal components are ampli-fied, improving the correlation between samples. As integration reduces the slew-rate of the signal, slope overload conditions (Fig. 2.12) also become less likely.Additionally, the dynamic specifications for the quantizer/ sampling stage arerelaxed as well. When theintegratedinput signal is regarded instead of the inputsignal, Fig. 2.12 also shows theΣ∆M principle.

Q

Q

Q

Q

f

DAC

−∆

+∆

δ+∆

−∆SamplerQuantizerIntegrator

sd[n]

LP−Filter

s(t)

−

Integrator DAC

s(t)

Modulator Demodulator

Figure 2.13.: Sigma-Delta modulation and demodulation



The major advantage ofΣ∆M over delta modulation is that only a low-pass filterwith relaxed specifications instead of an integrator is required for signal recon-struction. Further simplification is obtained by moving both integrators behindthe subtractor (Fig. 2.14).

Q

Q

Q

Q

f

δ

+∆

−∆

−∆

+∆sd[n]

LP−Filter

s(t)

DAC

−Quantizer

DAC

Integrator Sampler

s(t)

DemodulatorModulator

Figure 2.14.: Sigma-Delta modulation and demodulation (efficient implementation)

The advantage of exchanging amplitude resolution against oversampling ratio isalso frequently applied digital signal processing. In thiswork, Σ∆M is used inthree different forms:

Σ∆PLL: The circuit-under-test (Sec. 3.2) uses anΣ∆PLL to achieve a fine fre-quency granularity with a high ("coarse") reference frequency.

Σ∆-attenuator: In the digital sine generator (Sec. 5.1), a largeN-by-N bit multi-plier is replaced by a compactΣ∆M attenuator.

Σ∆-FM discriminator: In the output response analyzer (Sec. 6.2.2), the RF sig-nal is demodulated and quantized with an Sigma-Delta Frequency Discrim-inator (Σ∆FD), yielding anΣ∆M bitstream approximation to the frequencydeviation.

Q∆

−1zsd[n]

−

Accumulator

s[n]

Quantizer

Figure 2.15.: Digital sigma-delta modulator

In digital Σ∆M, the integrator is replaced by an accumulator, the DAC in thefeedback path is implemented by a MUX selecting±∆Q/2 or 0,∆Q.

As the signal is already DT, the sampler becomes a unit delay that is drawn into


46 2. Fundamentals

the accumulator (Fig. 2.15) with a transfer functionHA(z) of

HA(z) =z−1

1−z−1 and |HA(Ω)| = 1√2−2cosΩ

. (2.6.1)

2.6.1. Single Bit Quantizer

For multibit quantizers, the quantizer gain is usually approximated asgQ ≈ 1.The output of a single-bit quantizer only depends on the signof the input value,hence, its "gain"gQ strongly depends on the input signal. Useful approximationsfor gQ can only be made by regarding the closed loop.

The same is true for the full scale amplitude, which is usually defined as thevalue where the input signal becomes equal to the DAC output∆Q as higherinput signals overload the converter.

For frequencies well belowfS/2, the loop gain isHA( f )gQ ≫ 1 and overall gainis determined by feedback. Correspondingly, the quantization error is−∆Q ≤e[n] < ∆Q with a noise power ofe2

n = (2∆Q)2/12= ∆2Q/3.

For the purpose of analysis, the DAC gain factor is absorbed into the quantizerΣ∆-output, yielding a∆Q instead of a±1 stream. This has the advantage that thelow-pass filtered output can directly be interpreted as an approximation to theoriginal signal.

2.6.2. Quantization Noise in Σ∆M

z −1

1 − z−1

ne [n]

−

s[n]

Quantizer

sd[n]

Accumulator

Figure 2.16.: Model for quantization noise inΣ∆M bit stream

The model in Fig. 2.16 is used for the analysis of quantization noise in theΣ∆Mstreamsd[n] where the quantizer action has been replaced by adding the quanti-



zation noise voltageen[n] to the original signal. The digital output stream is

SD(z) = (S(z)−SD(z))z−1

1−z−1 +en(z)

=

(S(z)

z−1

1−z−1 +en(z)

)(1+

z−1

1−z−1

)−1

= S(z) z−1︸︷︷︸Hs(z)

+en(z)(1−z−1)︸︷︷︸

Hn(z)

. (2.6.2)

e [n]

−1

(1−z )

z

n−1

sd[n]s[n]

Figure 2.17.: Signal and noise transfer functions in first orderΣ∆M

The resulting bit stream contains the input signal plus the quantization noise.While the signal is merely delayed by one sample, i.e. thesignal transfer function(STF) isHs(z) = z−1, the quantization noiseen = ∆Q/

√12fS is shaped with the

noise transfer function(NTF) Hn(z) = 1− z−1 (Fig. 2.17). Hn attenuates lowfrequencies ofen by taking the difference between two consecutive samples. Thefrequency response is calculated using sin2x = 1

2(1−cos2x):

Hn

(ejΩ)

= 1−e−jΩ = 2je−jΩ/2 ejΩ/2−e−jΩ/2

2j

= 2ej(π−Ω)/2sinΩ2

(2.6.3)∣∣∣Hn

(ejΩ)∣∣∣=

∣∣∣∣2sinΩ2

∣∣∣∣=∣∣∣∣2sin

π ffS

∣∣∣∣ (2.6.4)

(2.6.4) shows that the quantization noise at theΣ∆M output is high-pass shaped inthe frequency range 0. . . fS/2, returning to zero atfS. The noise power containedin the bandwidth of interestB is given by (2.6.5):

Nq(B) =∫ +B

−BH2

n( f ) ·N′q( f )d f =

∫ +B

−B4sin2

(π ffS

)e2

n

fSd f

=∫ +B

−B2

(1−cos

2π ffS

)e2

n

fSd f =

2e2n

fS

[f − fS

2πsin

2π ffS

]+B

−B

=e2

n

π

[2π ffS

−sin2π ffS

]+B

−B=

2e2n

π

[2πB

fS−sin

2πBfS

](2.6.5)


48 2. Fundamentals

The quantized noise is now concentrated at higher frequencies where it can befiltered out for a small signal bandwidthB≪ fS/2. In this case, it can be approx-imated using sinx≈ x−x3/6:

Nq(B≪ fS/2) ≈ 2e2n

π

[2πB

fs− 2πB

fs+

16

(2πB

fS

)3]

=π

2e2n

3

(2BfS

)3

=π

2e2n

3OSR3 =

(π∆Q

6OSR3/2

)2

(2.6.6)

A sinusoid with amplitudeApp = (4/π)∆Q = 1.27∆ that uses the full input rangeof the Σ∆-quantizer without clipping has a signal power ofA2

pp/8 = 2∆2Q/π

2

(2.5.6), yielding anSQNRof

SQNR= 10log

(√2∆Q

π· 6OSR3/2

π∆Q

)2

dB = −6.6 dB+30logOSRdB (2.6.7)

First orderΣ∆M improves the SQNR by 30logOSR, compared to only 10logOSRfor oversampling without noise shaping (2.5.8). Fig. 2.18 visualizes the differ-ences between Nyquist-rate, oversampled and noise-shaping data converters.

Figure 2.18.: Nyquist rate (a), oversampling (b) andΣ∆M (c) converters [Kes05]



2.6.3. Spurious Tones of First Order Σ∆M

When a constant signal is applied to a first orderΣ∆M, the internal quantizedsignal changes between two levels, keeping the mean equal tothe input signal.Depending on the level of the input signalx = Qi + b/a∆Q with respect to thetwo nearest quantization levelsQi andQi+1, the output pattern can have a shortpattern length, concentrating the quantization noise in a few strong spectral lineswhich are also called "idle tones". The worst kind of input signals are DC signalswith a low-valued denominator, i.e.a = 2,3, . . .. ThisDC pattern noiseis a well-known issue of first order SDMs; expressions for the frequency and power ofthese lines have been derived by [CB81, Gal93] amongst others.

Figure 2.19.: SDM noise for DC inputs [CT92, p. 5]

Fig. 2.19 shows that the peak noise regions are indeed aroundlow-values fora,i.e. around 1/2, 1/3 etc. When a low-frequency (f ≪ fS) signal is present, theSNR is defined by integrating the noise over time while movingalong the x-axisin Fig. 2.19. Choosing a bias point around one of the peak noise regions ofFig. 2.19 will therefore lead to a bad SNR.

2.6.4. Higher Order Σ∆M

In first orderΣ∆M, the correlation between input signal and quantization erroris rather strong, leading to patterns in the output bit stream which show up asspurious lines in the spectrum. Additionally, the noise shaping only has a weak,first order characteristic.

One way to improving first-orderΣ∆M is to apply the integrated error between


50 2. Fundamentals

z−1+∆

−∆

a2z−1

a1

Quantizer

First order SDM

− −s[n] sd[n]

Figure 2.20.: Second order multi-loop SDM

input signal and quantizer output to its input instead of theoriginal input signal(Fig. 2.20). This topology is calledmulti-loop Σ∆M. The quantizer output isscaled and fed back into multiple stages of the modulator. The resulting signaland noise transfer functions are given by:

Hs(z) =z

z2 +(a1 +a2−2)z+1−a2= z−1 for a1 = a2 = 1 (2.6.8)

Hn(z) =(z−1)2

z2 +(a1 +a2−2)z+1−a2=(1−z−1)2

" (2.6.9)

⇒ |Hn ( f )| =∣∣∣1−e−j2π f Ts

∣∣∣2= 4sin2 π f

fS(2.6.10)

Choosinga1 = a2 = 1 yields an especially simple implementation (Fig. 2.21) thathas also been used in the digital sine generator (Sec. 5.1).

−11−z1

−11−z1

z−1+∆

−∆

Quantizer

−−

s[n] sd[n]

Figure 2.21.: Second order multi-loopΣ∆M with a1 = a2 = 1

−11−z1

−11−z1

−12−z

z−1

−1

+1

Quantizer

sd[n]

−s[n]

Figure 2.22.: Equivalent second order single-loopΣ∆M for Fig. 2.21

The STF of the second orderΣ∆M in Fig. 2.20 is just a delay of one sample (2.6.8)as with a first order SDM. The NTFHn( f ) (2.6.10), however, has a second order



behavior, resulting in a stronger noise shaping. It is calculated exactly as theNTF of the first orderΣ∆M (2.6.4). The structure in Fig. 2.21 can be rearrangedto obtain the second order single-loopΣ∆M in Fig. 2.22 with identical STF andNTF. The quantization model for both version is given in Fig.2.23

ne [n]

sd[n]−11−z1

−11−z1

z−1−12−z

Quantizer−s[n]

Figure 2.23.: Quantization noise model forΣ∆M in Fig. 2.21 and 2.22

A different architecture for higher-order noise shaping isknown under the nameof cascaded SDMor MultistAge noise SHaping(MASH). In this topology, single-and second-order loops are cascaded (Fig. 2.24), their single-bit outputs are com-bined in anoise-cancellationblock.

The difference between the quantizer output and the output itself of the first ac-cumulator is quantization noise which is integrated in the second accumulator.The output of the first stage is summed with the differentiated output of the sec-ond stage. This way, the quantization noise is high-pass shaped while the signalpasses without disturbance.

2 bit

xd(n)

x(n)

−CO CO −1z

−1z−1z

Figure 2.24.: Second order digitalΣ∆M with multistage noise shaping

The main advantage of the MASH architecture is that it is unconditionally sta-ble as it is made of first order sections without overall feedback. The multi-bitoutput stream necessitates a multi-bit DAC (Σ∆-ADCs) which may suffer of non-linearities (in contrast to a one-bit converter). In the circuit-under-test, a third-order MASH is used within theΣ∆-PLL to achieve fine frequency granularity


52 2. Fundamentals

with a high reference frequency. A multi-modulus divider (MMD) converts themulti-bit stream to division ratios, linearity problems (i.e. divider delay depend-ing on the division ratio) can be avoided by proper design techniques [LRP+04].

More in-depth information on various aspects ofΣ∆ modulation can be found in[CT92].

2.6.5. Terminology

Historically, the notationDelta-Sigma Modulationwas used first in 1962. Thisterminology describes the causal sequence of operations (difference operationfirst, followed by integration). In the 1970s, the termSigma-Delta Modulationwas coined to reflect the functional hierarchy: Similar to "Root-Mean-Square"where the actual sequence of operations is "Square-Mean-Root", "Sigma-Delta"describes how a difference is integrated [Kes05]. Nowadays"Sigma-Delta Mod-ulation" is more popular than the original terminology, this terminology is alsoused throughout this work.

2.7. Digital Resonators

The most important building block of recursive digital filters is thedigital res-onator, a system with one or two complex poles8. First order resonators with acomplex pole require a complex coefficient (i.e. two multipliers) and are most ef-ficient for processing complex input signals. Here, only themagnitude responseof real signals is of interest and only second order resonators with real coeffi-cients are regarded. One or two zeros can be included in a separate section.

2.7.1. Basic Properties

A purely recursive second order system with real coefficients a1,a2 is describedby the transfer function (2.7.1).

H(z) =g0

1+a1z−1 +a2z−2 =g0z2

(z−zp,1)(z−zp,2)(2.7.1)

8Systems with real poles have no resonant behavior (ringing, peaking) and are not regarded here.


2.7. Digital Resonators 53

The zeros of the characteristic equation∆ define the poleszp,i of the system(2.7.2):

∆ = 1+a1z−1 +a2z−2 ⇒ zp,i = −a1

2±

√a2

1

4−a2 (2.7.2)

For the casea2 > a21/4, the system has two conjugate complex poleszp,1 = z∗p,2 =

rpe±jθp that are written in polar form for this analysis, i.e. aspole radius rp (2.7.3)andpole angleθp (2.7.4).

r2p = r2

p,1 = r2p,2 =

∣∣zp,i∣∣2 =

a21

4+

(a2−

a21

4

)= a2 (2.7.3)

θp,i = arctanℑzp,iℜzp,i

= ±arctan

√a2−a2

1/4

a1/2= ±θp (2.7.4)

⇔ a1 = −ℜzp,i = −2rpcosθp and a2 = r2p (2.7.5)

The system is stable when all poles are inside the unit circlei.e. thepole radiusrp is less than one.

1

a

complex poles

2

a

1

1

−1

−1−2 2real poles

Figure 2.25.: Stability region of a second order system with real coefficientsa1,a2

The stability condition (2.7.6) for complex poles is derived directly from (2.7.3)and visualized as thestability trianglein Fig. 2.25.

a2 < 1 for a2 >a2

1

4(2.7.6)


54 2. Fundamentals

The transfer function in polar form is given in (2.7.7).

H(z) =g0z2

(z−zp,1)(z−zp,2)=

g0(1− rpejθpz−1

)(1− rpe−jθpz−1

) (2.7.7)

=g0

1−2rpcosθpz−1 + r2pz−2 (2.7.8)

Ω1

ejΩ

P1

P2

Z1,2

Lz

ℜz

ℑz

| z | = 1

Figure 2.26.: Poles’ and zeros’ contribution to magnitude frequency response|H(Ω))|

The frequency responseH(Ω) is determined by regarding the system function(2.7.7) along the unit circle9, z= ejΩ.

|H(Ω)| =∣∣∣∣

g0e2jΩ

(ejΩ −zp,1)(ejΩ −zp,2)

∣∣∣∣=g0

LP1 ·LP2(2.7.9)

(2.7.9) can also be interpreted geometrically (Fig. 2.26):The magnitude fre-quency response|H(Ω)| is given by the product of the distances between allzeros and the pointL = ejΩ on the unity circle divided by the product of the dis-tances between all poles and that pointL. The length of the individual sectionsLPi (2.7.10) is calculated from Fig. 2.27 using thecosine formula.

LPi =√

1+ r2p−2rpcos(θp,i −Ω) (2.7.10)

9only for a stable system



Ωθp,1

LP1

1

P1

rPθp,1−Ω L

ℜz

ℑz

Figure 2.27.: Calculation of distanceLP1

Finally, the magnitude response|H(Ω)| is obtained usingθp = θp,1 = −θp,2.

|H(Ω)|2 =

g20(

1+ r2p−2rpcos(θp−Ω)

)(1+ r2

p−2rpcos(θp +Ω)) (2.7.11)

2.7.2. Undamped Resonators

In the limiting case ofa2 = r2p = 1, the poles lie on the unit circle, and the system

shows undamped oscillation at theresonance frequencyΩr (2.7.12).

±Ωr = θp = arctanℑzp,iℜzp,i

= arctan

√1−a2

1/4

a1/2= arccos

a1

2(2.7.12)

The resonance frequency is identical to the pole angleΩr = θp as the normalizedfrequencyΩ = 2ω/ fS has the same values as the corresponding angle in radians,the characteristic equation is given by

∆ = 1−2cosΩrz−1 +z−2 = 0 . (2.7.13)

2.7.3. Resonance Gain and Peak Gain

The magnitude transfer function of a resonator with two complex poles has twomaxima at thecenteror peak gain frequency±Ωc. As the pole radiusrp ap-proaches one, these peaks become more pronounced and move closer to theres-onance frequencyΩr ≈ Ωc.


56 2. Fundamentals

When the poles are very close to the unit circle (rp ≈ 1), there is little mutualinfluence on the resonant behavior in (2.7.9) and the peak gain frequency isΩc ≈Ωr = θp (Fig. 2.28). In this case, peak gain at frequencyΩc is nearly identical tothe resonance gain at frequencyΩr = θp (Fig. 2.29) which is easier to calculate(2.7.14).

Figure 2.28.: Frequency response of the two-pole resonator (solid line) and contributionof individual poles (dashed lines) [Smi05]

H(ejθp) =g0(

1− rpejθpe−jθp)(

1− rpe−jθpe−jθp)

=g0

(1− rp)(1− rpe− j2θp

) (2.7.14)

The strong variation of resonance gain with resonance frequency is seen clearlyby regarding the special cases of resonance frequencies 0,π/2 andπ (2.7.15).

H(0) = H(

ejπ)

=g0

(1− rp)2 > H

(ejπ/2

)=

g0

1− r2p

(2.7.15)

The exact value forΩc can be found by setting the derivative of (2.7.11) to zero(2.7.16):

∂ |H(Ω)|∂Ω

= sinΩ [a1 (1+a2)+4a2cosΩ] = 0 (2.7.16)

Local minima are atΩ = 0 andΩ = π (except forθ = 0), the peak gain frequencyΩc (2.7.17) is found by setting the second part of (2.7.16) to zero.

cosΩc = −a1 (1+a2)

4a2= cosθp

1+ r2p

2rp(2.7.17)

2.7.4. Constant Peak-Gain Digital Resonator

The strong variation of peak gain over resonance frequency of the basic resonatorcan be reduced or avoided altogether by placing zeros at suitable positions, yield-



0

10

20

30

40

50

60

70

80

0 0.2 0.4 0.6 0.8 1

|H(Ω

)| (

dB)

Normalized frequency Ω/π

Resonator with b = 1, r = 0.99 and θ = 0 ... π

Figure 2.29.: Frequency response of the two-pole resonator withr = 0.99 for differentvalues ofθ

ing abiquadraticor biquadtransfer function (2.7.18).

H(z) =b0 +b1z−1 +b2z−2

1+a1z−1 +a2z−2 = g0(z−zz,1)(z−zz,2)

(z−zp,1)(z−zp,2)(2.7.18)

Placing zeros atz = ±1 (Ω = 0 andΩ = π) results in a biquad with constantpeak-gain over the whole frequency range that is also very simple to implement[Ste94]. The values for the coefficientsa1 = −2rpcosθp anda2 = r2

p have beenselected as before.

|H(Ω)| = g0

∣∣∣∣∣

(ejΩ −zz,1

)(ejΩ −zz,2

)

(ejΩ −zp,1)(ejΩ −zp,2)

∣∣∣∣∣= g0LZ1 ·LZ2

LP1 ·LP2(2.7.19)

Similar to (2.7.17), the frequency of peak gain can be derived as (2.7.20). Obvi-ously, the zeros atz= ±1 prevent setting the peak gain at and nearΩ = 0 andΩ = π. As the factor for cosθp in (2.7.20) is always less than 1, a value forΩc

exists for every setting ofθp. This means, in contrast to (2.7.17), the resonatorshows peaking for every value ofθp but peak gain frequencies nearΩ = 0 andΩ = π cannot be set.

cosΩc = cosθp2rp

1+ r2p

(2.7.20)


58 2. Fundamentals

Ω−1 1

ejΩ

P1

P2

Z1 Z2

Lz

ℜz

ℑz

| z | = 1

Figure 2.30.: Constant peak gain resonator with zeros atz= ±1

The peak gain atΩc depending on the pole radius is given by [Ste94].

Hc(Ωc) =2

1− r2p6= f (θ) (2.7.21)

Fig. 2.31 shows the behavior of the constant peak-gain resonator for differentpole frequenciesθp. The transfer function has been scaled withH−1

c (Ωc).

2.7.5. Bandwidth and Settling Time of High-Q Resonators

Bandwidth

For a second order band-pass, bandwidthB is usually defined as thehalf-powerbandwidth B−3, i.e. the difference of the upper and lower -3 dB frequenciesω+

andω− where the magnitude response has dropped by 3 dB compared to the gainAc at the center frequencyωc =

√ω+ω− (Fig. 2.32).

The resolution bandwidth(RBW) of a spectrum analyzer is the -3 dB frequencyof the resolution filter, describing the minimum frequency difference of two sinetones with equal amplitude that can be resolved.

Theshape factor SFor selectivityof a band-pass filter is important for applica-tions where tones need to be separated that are close to each other. It is usu-ally defined by the ratio of the -3 dB and the -60 dB bandwidthB−60 (Fig. 2.32)



-50

-40

-30

-20

-10

0

0 0.2 0.4 0.6 0.8 1

|H(Ω

)| (

dB)

Normalized frequency Ω/π

Resonator with b = z-2 - 1, r = 0.99 and θ = 0 ... π

Figure 2.31.: Frequency response of the constant peak-gain resonator withr = 0.99 fordifferent values ofθp

−60

−40

−20

−30

Frequency

A [d

B]

B−3

B−60

60dB

3dB

ω−ωc

ω+

Figure 2.32.: Band-pass filter specifications


60 2. Fundamentals

[Agi06]. Typical values for the selectivity in a spectrum analyzer are 1:5 for adigital and 1:10 . . . 1:15 for an analog filter implementation.

Normalized bandwidth is defined as∆Ω = Ω+−Ω−, relative bandwidth Brel asthe ratio of bandwidth and center frequency.

For resonators withrp ≈ 1, the normalized center frequency is very close tothe pole angle,Ωc ≈ θp and the bandwidth can be estimated graphically fromFig. 2.33: The -3dB pointsΩ− andΩ+ are

√2 farther away from the pole than

the resonance frequencyΩr , yielding

∆Ω ≈ 2(1− rp) ⇒ B =∆Ωπ

fs2≈ 1− rp

πTs. (2.7.22)

≈ Ωc

Ω+

Ω−

1

1

Ω+ −θp

P1

rP

θp

1− rP

≈ 1− rP

≈ 1− rP√

2(1− rP)

ℜz

ℑz

Figure 2.33.: Estimation of resonator bandwidth

For a second order system, thequality factor Qis approximately the reciprocalof the relative bandwidthBrel (referred to the center frequencyfc):

Q≈ 1Brel

=fcB

=Ωc

∆Ω≈ θp

2(1− rp)(2.7.23)

Settling Time

As the bandwidth of a narrow-band filter determines its settling time, bandpassspecifications always are a compromise between spectral andtemporal resolution.



For high-Q digital filters with a dominant pole, the settling time-constantτ canbe estimated from the pole radius (2.7.24) [Smi07].

τ ≈ 12πB

=TS

2(1− rp)(2.7.24)

The other pole has a strong influence on the frequency response for frequenciesnear 0 orπ, resulting in a large error of the estimations above.

2.7.6. Resonator Implementations

As the poles are mainly responsible for stability and quantization effects, onlythe differences between recursive structures are regardedhere.

Various structures have been developed to optimize different aspects of resonatorbehavior like robustness, signal-to-noise ratio or tunability. An overview overdifferent structures can be found e.g. in [MS86] or [Zöl05],the latter comparesdifferent second-order sections with respect to their SNR.

Direct Form Resonator

A rational transfer function inz can be immediately implemented in hardware,yielding the well-knowndirect formstructures. The filter coefficientsai ,bi areidentical to the polynomial coefficients as shown in Fig. 2.34 for a purely recur-sive transfer function (2.7.1). Due to this equivalence, the formulas that havebeen derived for resonance frequency etc. in the last sections, apply directly forthe direct form resonators.

y[n]

1z −1 z −1

−a2

x[n]

−a

Figure 2.34.: Direct form resonator (second order)

(2.7.5) shows that the pole positions due to a quantized coefficient a2,Q are con-centrated near the unit circle. Fora2,Q = 1, the pole moves along the unit circlewith Ωr = θp = arccos(−a1,Q/2). Pole density is high aroundΩr = π/2, at lowfrequenciesΩr ≪ 1 thereduced pole densityleads to large errors due to coeffi-cient quantization and degrades the SNR [Zöl05].


62 2. Fundamentals

LDI Based Resonator

The structure in Fig. 2.35(a) is known in literature under different names:state-variable biquad[MS86] as it can be derived from analog state-variable filters orKingsbury structureafter [Kin73]. Here, structures built around a loop of twolossless digital integrators(LDI) are given the more general nameLDI basedresonator.

z−1

−1z

−

k1

k2

k3

xi,LP xi,HPxi,BP1

xi,BP2

yo

yo,n

yo,b

(a)

−1z−11−z

1

L2

−11−z

L1k1

−k2

k3

(b)

Figure 2.35.: LDI based resonator (a) and SFG of loops (b)

The LDI based resonator has a good SNR aroundz= 1 and it can be tuned witheither parameterk1 or k2. This is especially simple for the Kingsbury structurewherek1 = k2. Settingk3 = 0 places the poles on the unit circle.

Coupled-Form Resonator

Thecoupled-form resonator, also calledRader-Gould resonatorin Fig. 2.36 hasthe transfer function (2.7.25).

−1−1z z

β −βx[n]

y[n]

α α

Figure 2.36.: Coupled-form resonator

H(z) =1

1−2αz−1 +(α2 +β 2)z−2 (2.7.25)

(2.7.25) shows that one filter coefficient determines the real part and the otherone the imaginary part of the poles. Hence, the density of poles within the unitcircle is constant.


2.8. Fixed-Point Number Format 63

However, it is obvious that the condition√

α2 +β 2 = 1 for undamped resonancegenerally cannot be achieved for quantized coefficientsαQ,βQ. It is also unprac-tical that both coefficients have to be tuned to modify the resonance frequency.

2.8. Fixed-Point Number Format

When minimum hardware complexity is important, digital signal processing isperformed with fixed point arithmetics. In contrast to software and digital sig-nal processor solutions, FPGA and ASIC implementations allow a free choiceof number representation (scaling, bias, two’s complement, ...), the number ofinteger bitsQI and fractional bitsQF (the position of the binary point) and thetotal word lengthWL= QI + QF (Fig. 2.37). In this work, the "Q-notation" isused:

QU[QI].[QF] for unsigned andQS[QI].[QF] for signed numbers.

MSB

QI

WL

QF

LSB

b0b1b2bQF bQF−1bWL−1 bWL−2 bWL−3

Figure 2.37.: Fixed-point number representation

The same binary wordBinWord represents different real-world values (RWV),depending on the number format (Tab. 2.1). For unsigned numbers, this relationis simply:

RWV= 2−QFWL−1

∑i=0

bi2i =

WL−1

∑i=0

bi2i−QF

For signed numbers, the MSBbWL−1 represents the sign bit. The correspondingrelation is

RWV=

WL−2

∑i=0

bi2i−QF for bWL−1 = 0

WL−2

∑i=0

bi2i−QF −2QI for bWL−1 = 1


64 2. Fundamentals

Encoding QU8.0 QU2.6 QU1.7 QS8.0 QS2.6 QS1.7

2QF 1 64 128 1 64 128

BinWord Real World Value (RWV)

00000000 0 0.000 0.000 0 0.000 0.000

00000001 1 0.016 0.008 1 0.016 0.008

00011000 24 0.375 0.188 24 0.375 0.188

01111111 127 1.984 0.992 127 1.984 0.992

10000000 128 2.000 1.000 -128 -2.000 -1.000

10000001 129 2.016 1.008 -127 -1.984 -0.992

11111111 255 3.984 1.992 -1 -0.016 -0.008

Table 2.1.: Examples for binary encoding with corresponding real world values (roundedto 3 decimal digits)

The resolutionε of a fixed-point number is given byε = 2−QF. The effect ofexceeding the numeric range during an arithmetic operationdepends on the hard-ware implementation:Saturationlogic clamps the result to the maximum resp.minimum value when an overflow resp. underflow condition occurs, moduloorwrap-aroundlogic simply drops the overflow bit which has the effect of subtract-ing 2WL from the result. The latter results in a more unpredictable behavior andpossibly oscillations (limit cycles) but needs no additional hardware. For this rea-son, modulo arithmetics is chosen in this work, overflow conditions are avoidedby proper scaling.

2.9. Digital Filters

Many different topologies for DT filters have been developedwith specific ad-vantages and disadvantages. The overview in Fig. 2.38 only shows the types thatare described in this section.

2.9.1. Direct Form and Related Filters

A rational DT transfer functionH(z) (2.9.1) (e.g. obtained via bilinear transformfrom a rational CT transfer functionH(s)) can be written in different forms, pro-


2.9. Digital Filters 65

digital filters

recursive

direct form

DF I DF II

reference network

WDF LDI

resonator based

non-recursive

Figure 2.38.: Types of digital filters

viding different "construction plans" for implementation. For real filter coeffi-cientsam,bn, poles and zeros are either real or complex-conjugate pairs.

H(z) =Y(z)X(z)

=

:=H1(z)︷︸︸︷M

∑m=0

bmz−m

1+N

∑n=1

anz−n

︸︷︷︸:=H2(z)

= H1(z)H2(z); M ≤ N (2.9.1)

When the difference equation (2.9.2) is deriveddirectly from H(z) in polynomialform, the corresponding recursive DT filters (Fig. 2.39) arecalleddirect form(DF) filters. A common implementation is the so calleddirect form type II(DFII) shown in Fig. 2.39 with a minimum number of registers (canonical form).

Y(z)

(1+

N

∑n=1

anz−n

)= X(z)

M

∑m=0

bmz−m

⇔ y[k] = −N

∑n=1

any[k−n]+M

∑m=0

bmx[k−m] (2.9.2)

It is well-known that DF filters are very sensitive to coefficient truncation andquantization [Smi05, Mey07], making them impractical for applications withshort word length.


66 2. Fundamentals

z −1 z −1z −1

b10b

−aN−aN−1−aN−2

bMbM−1bM−2

−a1

g[k]g[k+1]

x[k]

g[k+N−1]

g[k+N]

y[k]

Figure 2.39.: Type II direct form filter

Cascaded (SOS) filters

Rearranging the transfer function (2.9.1) into products offirst and second order(2.9.3) is the starting point forcascaded filters:

H(z) =

M∑

m=0bmz−m

1+N∑

n=1anz−n

=

M∏

m=1z−z0,m

N∏

n=1z−z∞,n

; M ≤ N (2.9.3)

Individual product terms are implemented assecond order sections(SOS), eachrealizing one or two (complex-conjugate) poles and zeros. The robustness ofsuch a cascade of first and second order filter sections is muchhigher than adirect implementation.

Parallel form

The transfer function (2.9.1) can also be written as asumof first and/or secondorder terms (2.9.4), obtained by partial fractional expansion [Smi05]

H(z) =

M∑

m=0amz−m

1+N∑

n=1bnz−n

= F(z)+NP

∑k=1

M

∑m=1

r i

1− piz−1 ; M ≤ N (2.9.4)

wherepi are the poles of the transfer function andr i are theresidues.



This structure can be implemented as aparallel filter, where the outputs of indi-vidual first and second order sections are summed up. Parallel filter structuresare preferred when the different sections havedisjoint passbands[Smi05] (e.g.for multiple passbands). Parallel filters are also much morerobust than a directimplementation; for the same word length, parallel filters have a more ideal pass-band and worse stopband characteristic than cascaded filters.

A serious disadvantage of DF and derived filters is that thereis no simple corre-lation between filter coefficients and frequency response: Tuning e.g. the centerfrequency of a band-pass requires re-calculation of all coefficients.

2.9.2. Passivity and Reference Network Filters

At the beginning of the 1970’s, analog (LC) filter topologies like doubly termi-natedLC ladder networks (Fig. 2.40) [TR86] and design methodologies had beendeveloped for the construction of robust higher order filters with low sensitivityto component variations.

vin

R0

R0C1L1

C2 L2

vo

Figure 2.40.: Doubly terminated fourth order ladder LC band-pass filter

Alfred Fettweis was probably the first to understand that therobustness of thosepassive filters can be linked to "zero loss". In an interview he pointed out thatthis is one of the rare cases where engineers get a "free lunch":

"Anyhow, I realized that this sensitivity problem was related tobasic loss. Zero loss in a passive circuit is something you can nevergo below, because it would mean you have an active device. [...] Soif you have passive devices, at any frequency where the loss reacheszero, that’s rock bottom. [...] If you change a component, ifyoulower it or make it larger, you cannot get below that value, and there-fore the derivative is zero, so you have zero sensitivity. [...] Supposeyou have a filter of degree ten, you may have in that filter, let’s say,twenty components. With a filter of degree ten, you can have zeroloss at five different frequencies in the pass-band. Now, thesensi-tivity at any of these five frequencies is zero, and this with respect


68 2. Fundamentals

to any of the parameters. You have twenty parameters times five,that is a hundred conditions you impose on the sensitivitiesto bezero. Now you have only twenty parameters in your circuit; howcan you satisfy a hundred conditions? In addition, you don’twantto waste your freedom completely for getting good sensitivity coeffi-cient; you want to use it to get a good filter curve. Now, the amazingthing is you get the good sensitivity free of charge. Just design thefilter to be a good filter, and these one hundred conditions areauto-matically fulfilled. That is a fantastic property of passivecircuits."[Fet97].

Once this property ofpassivitywas understood, a lot of research was conductedto derive DT filter structures from theseanalog referenceor prototype networks.

i in

R

i0

vL,1

vC,1

i1

C1

L1

vo

(a)

1

1

1i in

R

i0

vL,1

−vC,1

−i1

−1/sL11/sC1

vo

(b)

−1sC1

1sL1

R

x0x1

xin

yo

(c)

z −1

z −1z −1

z −1

dela

y−fr

ee lo

op

R

TS/2C1

−TS/2L1

x0

x1

xin

yo

(d)

Figure 2.41.: Singly terminated second order LC band-pass (a), its SFG in V/I (b) andabstract form (c) and its unrealizable bilinear DT simulation (d)

One way to maintain passivity of a DT filter is theoperational simulation10 ap-

10"Simulation" in the general meaning of mimicking the behavior ofone system with a differentsystem.



proach: The Kirchhoff equations of an analog reference network aretransformedin such a way that the transmittances and immitances of allLi andCi elementsare mapped to integrators(sLi)

−1 resp.(sCi)−1. This is usually performed with

the help of a voltage-current(V/I) signal-flow graph(SFG), which can be imple-mented as an active, inductorless analog filter [MS78] or as an SC filter for fullcircuit integration without resistors [GMT83].

However, this approach fails for fully digital filters: In Fig. 2.41(a), the ex-ample of a second order band-pass is shown with the corresponding V/I SFG(Fig. 2.41(b)) and abstract SFG (Fig. 2.41(c)). Approximating the individual CTintegrator blocks by bilinear transform DT integrators results in a DT networkwith unrealizabledelay-free loops(Fig. 2.41), due to the zero latency of the DTintegrators.

i0 = i in − i1 vout = i0R vL,1 = vout−vC,1 (2.9.5)

−vC,1 = −i11

sC1−i1 = vL,1

−1sL1

(2.9.6)

To overcome the problem of delay-free loops, Alfred Fettweis introducedwavevariables- linear transformations of theV/I equations known from microwaveand transmission line theory. Constructing the SFG from thewave variable equa-tions and transforming it to the DT domain [Fet86] yields so calledwave digitalfilters (WDF). WDFs maintain the properties of the reference networks, espe-cially their passivityandrobustnessagainst quantization and coefficient trunca-tion, making WDFs the most popular filters next to DF filters.

Lattice filters are a special case of WDF used in adaptive filtering because theirstability can be assessed easily. They are all-pole filters,lattice-ladder-filtersalsohave zeros.

While WDF and related structures are much more robust than DF filters, a seriousdisadvantage remains: There is no simple correlation between filter coefficientsand frequency response. This is similar to higher order analog filters which aredifficult to tune, requiring the simultaneous variation of multiple elements. As aconsequence, WDF battle with the same difficulty, leading to complex structures[ST76, SK97].

2.9.3. Resonator Based Filters

Filters based on undamped DTresonatorsare less well known than WDFs, al-though passivity and the same degree of robustness against coefficient truncation


70 2. Fundamentals

and quantization can be achieved [Pec88]. Similar to parallel filters derived di-rectly from the transfer function, resonator based filters consist of a set of paralleldigital resonators (Fig. 2.42). However, there are two important differences:

• The resonators are embedded in a common feedback loop.

• The resonators are undamped.

g

Nxx2x1x0xin

H (z)1 H (z)2H (z)N

Figure 2.42.: Resonator based filter bank

Due to the parallel structure, these filters have so far mostly been used in thecontext of adaptive filtering [MS86] with multiple outputs and filter banks forspectral analysis and decomposition [Pec86, PM91]. General transfer functionsH(z) can be implemented, using a design procedure described in [Pec89, PM93].

The filter bank in Fig. 2.43 shows the principle: a common input currenti in isdivided into currentsi1 . . . iN into the individualLC-series tanks which are takenas outputs. At the resonance frequencyωi , the impedance of a branchi becomeszero, sinking the complete input currenti in. This means, the magnitude of thetransfer function becomes one for branchi and zero for all other branches. In ananalog implementation of the reference circuit, it would ofcourse be difficult toextract the branch currents without damping the series tanks.

As shown in Fig. 2.41(d), bilinear transform of individual integrators in a loopleads to delay free loops that can not be realized. In contrast, replacing the wholeloop (Fig. 2.41) by a digital resonator is feasible. [TR95a,TR96] also build uponthis approach. Similar structures have been derived in different ways [PM91]:

Observer theory: An input signal is modeled by a hypothetical system of res-onators. The states of these resonators (and hence the inputsignal) is esti-mated by minimizing the error between the input signal and the output ofa set of actual observers [Pec89].

Simulation of singly terminated ladder filter: In the singly terminated ladderfilter in Fig. 2.43, each CT integratorloop is replaced by an undampeddigital resonator [PM91].



Iin

R

i0 i1 i2 iN

C1

L1

C2

L2

CN

LN

(a) Schematic

1 11 -1-1 -1R

x0

x1 x2 xNxin

sC1 sL1 sC2 sL2 sCN sLN

(b) Abstract SFG

Figure 2.43.: Singly terminated LC ladder filter bank

The different approaches described above differ in the choice of resonators: Pub-lications based on [Pec89] utilize first order complex filters with transfer func-tionsHi(z) (2.9.7)

Hi(z) =ziz−1

1−ziz−1 (2.9.7)

wherezi are complex coefficients.

[PM91, PM93] start with analogLC-ladder filters Fig. 2.43 and arrive at DT res-onator based filters built around second order resonators with real coefficients.Under certain restrictions, these resonators can be implemented with very hard-ware efficient structures requiring only two multipliers.

The above publications utilize a large number of resonators. However, the tun-ability, simplicity, scalability and robustness of resonator based filters makesthem an attractive choice for BIST applications, even with only one or a fewresonators.


72 2. Fundamentals

2.9.4. Comparison of Filter Structures

Tab. 2.2 summarizes the specific advantages and disadvantages of the DT fil-ters that have been presented in this section (Fig. 2.38). The target applicationrequires tunable narrowband band-pass filters with minimalarea, favoring theresonator-based filter structure.

Direct Form WDF Resonator-Based

Ease of design + - o

Flexibility + + -

Robustness - + +

Area Consumption - + +

Tunability - - +

Table 2.2.: Qualitative comparison of digital filter families


Any sufficiently advanced technology isindistinguishable from magic.

Arthur C. Clarke 3Introduction to the Circuit-Under-Test

After some general background on phase-locked loop (PLL) theory, the circuit-under-test (CUT), a sigma-delta modulated radio-frequency PLL as a centralpart of the DUT is described. A short overview of the device-under-test (DUT)is given as well, a highly integrated wireless transceiver for GSM and EDGEapplications. Finally, the critical specifications that need to be verified duringtest are summarized.

Frequency synthesizers belong to the most critical components of modern com-munication systems. They generate the local oscillator (LO) signal for upconver-sion and transmission of data over the air or some kind of wire-bound interfaceand for downconversion of the received signal back down intothe baseband do-main. In most systems, frequency synthesis is performed with a phase lockedloop (PLL) which locks the divided signal of a high frequencyoscillator to thesignal of a stable reference oscillator.

An ideal carrier signal would have a single spectral line at the oscillation fre-quency. In reality, random noise and other unwanted signalsmodulate the carrier.In the time domain, these disturbances can be seen as jitter,reducing e.g. the“data eye” of a clock and data recovery unit. In the frequencydomain, the dis-turbances show as noise skirts as well as discrete lines around the carrier. Theselines, created by periodic disturbances are calledspurious sidebands. (Fig. 3.1).

74 3. Introduction to the Circuit-Under-Test

Vctrl + ve

Vctrl

Tref

|S (f)|vco

f0f0 ref−f f0+f reft f

Figure 3.1.: Disturbance of the VCO control voltage producing phase noise and spurioussidebands on the VCO output

As the limited number of frequency channels has to accommodate more and morenetwork subscribers, bandwidth has become a valuable resource that may not bewasted by spurious emissions. In order to use this resource most effectively,frequency synthesizers have to fulfill ever increasing demands:

Fast settling time: GSM and some other communications standards use fre-quency division duplexing (FDD) / time division multiple access (TDMA)which changes frequencies between every receive and transmit slot. Foroptimum usage of time and frequency slots, this “frequency hopping”has to be as fast and smooth as possible, requiring tight control of loopbandwidth and phase margin.

Low phase noise and spurious sidebands: Noise and sidebands from the lo-cal oscillator can leak into other frequency channels during transmission,disturbing other subscribers. While receiving, local oscillator disturbancescan convert signal disturbances down into the target channel, desensitiz-ing the receiver. Noise within the channel bandwidth is alsounwantedbecause it increases the SNR and hence the bit error rate (BER) for bothreceive and transmit case. As a consequence, in-band and out-of-band PLLnoise needs to be tightly controlled to fulfill communication standards andsystem specifications.

Concepts for on-chip calibration and test help achieving these goals: BISC in-creases the yield by calibrating the loop parameters under all conditions, avoid-ing costly calibration routines during production. BIST reduces production testtimes and cost by running slow tests on-chip and reducing therequirements forexternal test equipment.


3.1. Basic PLL Theory 75

3.1. Basic PLL Theory

Detailed analysis is found in [Bes98, Gar79]; in the following, only some impor-tant results are excerpted:

φ ref

φ0

φ0

φ N=div F(s)

N1

PD+

CP

cut hereto open loop

VCO

Divider

Loop Filter

Phase Detector /Charge Pump

Figure 3.2.: PLL block diagram

Fig. 3.2 shows a block diagram of a PLL, Fig. 3.3 its control theory equivalent.

G(s)

Divider

φ e φ 0

H (s)

loop

φdiv

φ ref

open

PD / CP / LF / VCO

FB

Figure 3.3.: PLL block diagram - control theory point of view

Usually, the reference phaseφre f is regarded as the input and the VCO phaseφ0

as the output signal of a PLL (Fig. 3.2). Then, theforward transfer function G(s)(open feedback path) is given by

G(s) :=φ0(s)φe(s)

= Kφ KF0F(s)Kvco

s(3.1.1)

whereKφ is the (linearized) gain of the phase detector (PD), definingthe ratio



of average output voltage and phase error at the input.KF0 is a proportionalityfactor of the loop filter, including e.g. the current of a charge pump (CP),F(s)is the frequency dependent part.Kvco defines the ratio of frequency change ofthe VCO and the change of its input voltage. The PLL controls the phaseofthe (divided) VCO signal, the inherent perfect integrationof the VCO frequencyalways creates one pole at the origin (1/s, Type I PLL). An integrating loop filteror a charge pump (CP) add a second pole at the origin (Type II PLL), requiring azero for stabilization. The divider divides phase and frequency byN (Sec. 2.3.3).

The product of forward and feedback transfer function is the(open) loop gainG(s)/N (3.1.2).

As(s) = G(s)/N =Φdiv(s)Φre f(s)

=KPDKvcoKF0F(s)

Ns=

KOF(s)Ns

(3.1.2)

As the loop filter is a low-pass, the loop gain also has a low pass characteristic.Its order - which is also the order of the PLL - is the total number of poles of theloop gainG(s)/N. It is larger by one than the order of the low pass due to theintegrating behavior of the VCO.

Like most control systems, the behavior of a well-designed PLL can be approx-imated by a second order system, neglecting the higher orderpoles of the loopfilter:

F(s) ≈

11+s/ω1

for type I PLLs

1+s/ω1

sCfor type II PLLs

(3.1.3)

For the loop filter of a type I PLL, only the dominant loop filterpoleω1 is takeninto account; for a type II CP PLL the main integration capacitor C and the zeroat ω2 = (R2C)−1 are regarded.

Closing the loop in Fig. 3.3 gives theclosed loop transfer function T(s) (3.1.5):


3.1. Basic PLL Theory 77

T(s) =Φ0(s)

Φre f(s)=

G(s)1+G(s)/N

=KOF(s)

s+KOF(s)/N(3.1.4)

≈

Nω2n

s2 +2ζ ωns+ω2n

for type I PLLs

N(2ζ/ωns+ω2

n

)

s2 +2ζ ωns+ω2n

for type II PLLs

(3.1.5)

whereωn is thenatural frequencyandζ thedamping, the usual nomenclature forsecond order systems with

ωn =

√KOω1

Nζ =

12

√Nω1

KO=

Nωn

2KOfor type I PLLs and (3.1.6)

ωn =

√KO

NCζ =

R2

2

√KOC

N=

ωn

2ω2for type II PLLs. (3.1.7)

Theloop gain transit frequencyωsT where the loop gain magnitude becomes one,|G( jωsT)/N| = 1, is an important parameter for the design of PLLs (and othercontrol systems):

Type I PLLs: ωc ≈ ωn

Type II PLLs: ωc ≈ 2ωn

for ζ = 0.707 (3.1.8)

(3.1.4) shows that the closed loop transfer function ofall PLLs can be approxi-mated by (3.1.9), visualized in Fig. 3.4: For frequencies far below the loop gaintransit frequency,ω ≪ ωsT, the loop gain magnitude|G( jω)/N| ≫ 1 and theclosed loop gain|T( jω)| is only determined by the division ratioN in the feed-back path. Deviations of e.g. the reference phase are multiplied by the dividerratio, PLL phase noise in thisin-bandregion typically has a constant PSD and isdominated by reference, charge pump and phase detector noise.

|T( jω)| ≈

N for ω ≪ ωsT [|GH(ω)| ≫ 1]

|G(ω)| ∝ (ωsT/ω)p−z for ω ≫ ωsT [|GH(ω)| ≪ 1]

(3.1.9)



At frequencies above the unity gain frequency,ω ≫ ωsT, the feedback loop isno longer effective (|G( jω)/N| ≪ 1) and the transfer function is determined bythe forward gain functionG( jω). In this frequency range, the PLL behaves likea low-pass of ordernp− nz and the closed loop transfer function drops with(np−nz) ·20 dB/dec. PLL phase noise outside the loop bandwidth is dominatedby the VCO with a PSD that drops with -20 dB/dec. Depending on the phasemargin,|T( jω)| may exhibit peaking at frequencies aroundωsT.

Bn

ωT(j )log | |

Nlog

f

−3dB

B

Figure 3.4.: Closed loop gain|T( jω)| and noise bandwidthBn

The loop gain transit frequency is also approximately equalto the -3 dB fre-quencyB of the closed loop (exact for a second order system with phasemarginof 45 deg),B[rad/s] ≈ ωc. It specifies the maximum change rate of the referencesignal the PLL output still can follow. This is also true for changes of the dividerratio which is used to modulateΣ∆PLLs. Hence, the noise bandwidthBN for thereference input and the divide ratio input also directly depends upon the closedloop bandwidthB.

|T( jω)| .= |T(0)|/

√2 = N/

√2 (3.1.10)

B also gives the maximum frequency up to which noise from the VCO is sup-pressed by the control loop operation - for this noise component, a smaller band-width meansworsenoise performance.

This shows that the closed loop bandwidthB is a key performance parameter thathas to be verified during production test.

3.2. Circuit-Under-Test

Only a few years ago, most commercially available GPRS / EDGEtransceiverswere based on direct conversion architectures. A severe challenge in the design of


3.2. Circuit-Under-Test 79

direct modulation transmitters is preventing feedback from the Power Amplifier(PA) output to the unmodulated VCO which creates spurious sidebands [Lee98].This was achieved with cost-intensive shielding boxes and external filters forintegrated BiCMOS transceivers until commercial pressureforced chip makersto come up with more robust architectures and to migrate to low-cost CMOStechnologies.

Figure 3.5.: Principle ofΣ∆-modulated PLL with predistortion [GKM+03]

High integration density of modern CMOS technologies enabled the implemen-tation of advanced DSP techniques for digital signal generation. In [GKM+03],a quad-band GSM transceiver is presented in a 130 nm CMOS technology thatutilizes a digital sigma-delta modulation transmitter (Fig. 3.5). The integratedVCO is modulated digitally and runs at a multiple of themodulatedtransmit fre-quency, making it much less sensitive to PA feedback than a direct conversionarchitecture.

On-chip calibration loops (Built-In Self-Calibration, BISC) were used to over-come one of the main drawbacks of CMOS technologies, the increased parame-ter spread compared to technologies optimized for analog performance. Specifi-cally, VCO bands and loop gain have to be calibrated before each frequency hop[MSMG02, MS03]. Fig. 3.6 shows a simulation of lock-in, obtained with thesimulation methodology described in Sec. 4.5. Despite all digital calibrations,an excellent overall settling time of less than 120µs is achieved. These BISCblocks were also used for a basic Built-In Self-Tests (BIST)of the VCO and themulti-modulus divider to speed up production tests.

Due to the combined advantages of fine frequency granularity, fast settling, low



∆ f

TuneV

∆φ

Analog Lock−In

Built−In Self−CalibrationSignalsDigital

Figure 3.6.: Simulation of PLL lock-in with built-in self-calibration

phase noise and digital modulation capabilities [CKHS04, MS02a], most inte-grated transceiver circuits presented in the last few yearsutilize Σ∆ fractional-NPLLs (Σ∆PLLs) for frequency synthesis.

The device-under-test (DUT) is a wireless transceiver for GSM and EDGE buildaround aΣ∆PLL for frequency synthesis and digital modulation (Fig. 3.8). Fre-quency modulation is achieved modulating the division ratio of theΣ∆PLL, en-abled by the small granularity. Phase modulation for GSM is implemented asindirect PM, i.e. by frequency modulation with the differentiated message sig-nal.

The higher device noise level of CMOS technologies comparedto bipolar andBiCMOS technologies mandates a narrow PLL loop bandwidth. Typical in-band phase noise levels that can be achieved withΣ∆PLLs with a reference fre-quency of 13 or 26 MHz are -90 . . . -100 dBc/Hz, requiring a loopbandwidth of80 . . . 100 kHz to meet the spectral mask requirements at an offset of 400 kHz[Mär00]. This is in contrast to the goal of wide modulation bandwidths: Fig. 3.7shows the RMS phase error of a typical GSM modulation loop without predistor-tion as a function of the loop bandwidth, demonstrating thata bandwidth of ap-prox. 500 kHz is needed to meet GSM specs (5), neglecting other error sources.Therefore, manyΣ∆PLLs applybandwidth extension techniquesto achieve a sig-


3.2. Circuit-Under-Test 81

nal bandwidth exceeding the PLL bandwidth: The modulator architecture de-picted in Fig. 3.5 uses digital filtering pluspredistortionor pre-emphasis. Sig-nal bandwidth is extended by using a pre-emphasis filter withthe inverse to theclosed-loop transfer functionT(s) [PTS97].

The characteristic of the digital filter with pre-emphasis is defined by designwhile the PLL transfer function depends on technology and environmental pa-rameters [Per97, p. 65 – 93]. In practical implementations,this requires someform of adjustment or, preferably, self-calibration to ensure sufficient matchingbetween loop and pre-emphasis.

f = 1358.7 kHz = 0.74° @φrms −3 dB

−3 dBrmsφ = 4.81° @ = 540.42 kHzf

105

[Hz]

2

0

8

10

12

6

f−3 dB

710

610

[° ]

reff = 13 MHz

φ

4

rms

Figure 3.7.: RMS phase error as a function of the open loop bandwidth [Mär00]

Σ∆PLLs with bandwidth extension have first been used forFrequency ShiftKeying (FSK) applications where the hard switching between frequencies re-quires a large bandwidth [Per97] and a few years later for modulation standardswith tightly controlled bandwidth likeGaussian Minimum Shift Keying(GMSK)[Bax99, Mär00].



Figure 3.8.: Block diagram of quad band GSM transceiver

3.3. PLL Specifications and Test Methods

Three aspects are especially important for the performanceof RF PLLs:

Loop bandwidth and open loop gain are critical for performance in modula-tion loop architectures, especially when bandwidth extension techniquesare applied. These techniques rely on the matching of analogPLL char-acteristic and digital pre-emphasis filter, deviations distort the modulationsignal. Both parameters also directly influence the noise bandwidth andhence the

Total in-band phase noise of the PLL that has to be low enough not to degradethe bit error rate in both receive and transmit mode.

Spectral mask requirements need to be fulfilled in transmit mode to avoid dis-turbances of neighbor channels and receive band. One of the parametersthat is especially difficult to achieve is the specification of -113 dBc/Hz atan offset of 400 kHz, requiring a narrow PLL noise bandwidth in the rangeof 80 . . . 100 kHz.

Communication standards operating with constant envelopemodulation (GSM,TDMA) specify peak and RMS phase error over one burst, non-constant enve-lope standards like EDGE or UMTS usually specify the maximumerror vector


3.3. PLL Specifications and Test Methods 83

magnitude (EVM). Typically, half of the error budget has to be reserved for othererror sources outside the PLL like frequency difference between handheld deviceand base station, wideband noise of the VCO buffer or imperfections of modula-tor / demodulator. Within the PLL, both modulation distortions and phase noisecontribute to the integral error.

Pow

er D

ensi

ty [d

Bc(

Hz)

]

Offset Frequency [kHz]

Figure 3.9.: Power spectral density mask for GSM 900 and DCS 1800 [Mär00]

The maximum emission levels in the GSM system specification at given offsetfrequencies are measured with a spectrum analyzer with defined measurementfilter and resolution bandwidth (RBW). In Fig. 3.9 [Mär00], the GSM spectralspecifications are shown as PSDs for a bandwidth of 1 Hz for comparison withthe SP-BIST spectral analyzer.

The question how much the bandwidthB of the closed loop may deviate from itsnominal value depends on the transceiver architecture: Forunmodulated PLLs,the integrated VCO noise (∼ B−1) and reference noise (∼ B) as well as the set-tling time (∼ B−1) determine the acceptable bandwidth range, requiring controlto typically±20%.



ModulatedΣ∆PLLs require a tighter control of bandwidth variations as mis-matches between the modulation / pre-emphasis filter and thelow-pass charac-teristic of the PLL create distortions of the modulated signal. WhenΣ∆PLLsare used to create the angle modulation part in polar modulators [MKNM05,MNM+05], the loop bandwidth has to be controlled even tighter to minimizemismatches between phase and amplitude modulation paths.

[%]

φ rms

[° ]

εOLG

7.5

10

0 5 10 15 20

5.0

2.5

0−5−10−15−20

Figure 3.10.: RMS phase error as a function of the open loop gain error [Mär00]

Time-constant variations of integrated loop filters typically are in the order of20%, creating a bandwidth variation of the same order (3.1.8).

Open loop gainKO is another main contributor to bandwidth variations in thesame order of magnitude as it includes the gain variations ofVCO, PD, CP andloop filter. Consequently, several methods have been developed for loop gaincalibration / testing, either operating on the open [MSMG02] or the closed loop[MS02a]. However, these methods cannot track the variations due to loop filtertime constants, resulting in a larger tolerance band. Alternatively, precise exter-nal components (usually too expensive and large) or switched capacitor solutions(potential issues with switching noise) can be used.

The following estimations have been made for the RMS phase error due to loopbandwidth variations in a typical GSM systems with modulation loop [Mär00]:

• Variations of open loop gain in the range of±10% typically result in an


3.3. PLL Specifications and Test Methods 85

additional phase error of 3. . .5

• Variations in the loop filter components of only±10% create an RMSphase error ofφrms≈ 3.

Either case consumes more of the phase error budget than is typically allowedfor the complete PLL, showing the need for precise monitoring and possiblycalibration of the loop parameters. As a consequence, the closed loop bandwidthincluding the aforementioned error sources should be measured to an accuracy of±5%. Near the -3 dB point, the closed loop transfer function behaves like a first-order lowpass, rolling off with ca. -20 dB/dec. Hence, an amplitude measurementerrorAε directly translates to a bandwidth measurement error−Bε :

|Bε | < 5%⇒ |Aε | < 5%≡ 0.4dB

As loop bandwidth and in-band phase noise influence all critical PLL perfor-mance aspects, precise on-chip measurement of both parameters is of paramountimportance. Additionally, the RF signal has to measured at afew critical offsetfrequencies to verify conformance to spectral mask for modulated and unmodu-lated signal. These frequencies are usually known from lab evaluation. Finally,the out-of-band noise, dominated by VCO and VCO buffer has tobe determined.For the GSM case, the following requirements result:

Amplitude Accuracy: Frequency response has to be measured with an ampli-tude accuracy of±0.4dB.

Noise Floor: Phase noise floor has to be below -90 dBc/Hz for in-band noisemeasurements, preferably even lower.

Spectral Mask: Spurious tones and modulation have to be measured, the mostdifficult being the 400 kHz corner where the maximum emissionlevel is-113 dBc/Hz.

Out-of-Band Noise : Maximum emission level in TX mode is -129 dBc/Hz at 6MHz offset

Similar requirements can be collected for other wireless standards.


If at first the idea is not absurd, then there is nohope for it.

Albert Einstein 4Concept and Simulation Methodology forSpectral BIST

A self-test concept for integrated PLLs is introduced that allows the direct mea-surement of spectral parameters in RF PLLs. The measurementprinciple andthe partitioning of signal processing between chip and production tester areexplained. Furthermore, a new simulation methodology is introduced for RFsystems with a large digital part like PLLs, allowing efficient co-simulation ofanalog blocks in a digital simulator by using discrete-timebehavioral VHDLmodeling.

4.1. RF PLL Test Concept

Wireless devices and circuits are usually specified in the frequency domain, re-flecting the specifications of transmission standards usingfrequency divisionmultiplexing and duplexing. During production test, thesespecifications haveto be verified. In highly integrated RF ICs, the test of individual building blocksproves increasingly difficult as internal signals are not routed to package pinsto save area and to reduce the risk of unwanted crosstalk. Fig. 3.8 shows theblock diagram of an integrated GPRS - transceiver produced by Infineon Tech-

88 4. Concept and Simulation Methodology for Spectral BIST

nologies in 2003. By today’s standards, the level of integration is comparativelylow, but already here the PLL is inaccessible from the outside. Multiplexing thePLL RF output to a shared test pin does not work well as parasitics and crosstalkdeteriorate the signal quality, possibly also during normal operation mode.

DUT

BIST Control and Data BusSP−BIST

mod RFSpectral Output

AnalysisResponse

Multi−ToneStimulus

GeneratorCUT

BISTBUS

PLLΣ∆ f

Figure 4.1.: Spectral PLL BIST Concept

This makes on-chip spectral analysis of RF PLLs a highly attractive feature forimproving the testability; it can also reduce the hardware requirements for theproduction tester. While spectral parameters could be derived from e.g. the stepresponse, a direct measurement of spectral parameters (Fig. 4.1) is desirable asthe translation of time domain parameters into the frequency domain requireshigh digital signal processing power.

4.2. Measurement Principle

4.2.1. PLL Bandwidth

As shown in Sec. 3.1, the loop bandwidth defines the maximum modulation fre-quency of a PLL at the low-pass modulation points (referenceinput, loop filterinput, divider ratio). Modulation frequencies above the loop bandwidth give re-duced frequency excursions, corresponding to a smaller modulation index.

A PLL operates on phase excursions (as the name implies), however, it is easierto generate frequency modulation using digital techniques: Varying the divisionratio changes the output frequency, applying the frequencycontrol word as anoversampledΣ∆M bitstream achieves a fine granularity of frequency variation.This is utilized inindirect PM where the PLL is frequency modulated with thedifferentiated modulation signal.


4.2. Measurement Principle 89

The resulting modulation of the PLL signal can be determinedfrom its frequencydeviation, phase deviationor its amplitude spectrum. While the latter is thestandard measure used e.g. in a spectrum analyzer, a simple relation to phase orfrequency deviation only exists for small angle modulationindices (Sec. 2.2.2).However, high modulation indices are advantageous for a good SNR with simpledemodulators. Phase deviation is inversely proportional to modulation frequency(-20 db/dec), attenuation due to the loop bandwidth can be only be determined asa deviation from this slope (Fig. 4.2). This makes an FM discriminator the idealchoice as its output is a direct measure for the frequency response of the PLL(Fig. 4.2).

m1m1 m2

φ ,PLL

m2m2m1f f

S (f)

Characteristic

f f

ym2

ym1

ff

Loop S (f)

f1β

βf2

f

ff

S (f)Ad1Ad2

S (f)

f

Loop

f

Characteristic

A

f

f Demod.

FM

∆

s

mff

m1,2

sPLLf

BW

ora

0f

stim

Frac−NΣ∆−

0

−20 dB/dec

y,PLL

m2m1

mf

sstim

m PLLf

CUT

ora

Figure 4.2.: Principle of PLL bandwidth measurement

4.2.2. Spectral Analysis with FM Discriminator

In addition to PLL bandwidth measurements, the SP-BIST shall also be used tomeasure unwanted sidebands and in-band noise. As the SP-BIST only deliversthe power spectral density (PSD) of frequency deviation, ithas to be converted tophase noise to obtain results that can be compared to conventional lab equipmentand ATE hardware.

As shown in Sec. 2.3, PSD of phase deviationSφ is derived from frequency devi-ationSy via (4.2.1):

φ =∆ ffm

and 4Su( f0 + fm) ≈ 2L ( fm) = Sφ ( fm) =f 20

f 2m

Sy( fm) (4.2.1)



(4.2.1) also shows that frequency discrimination emphasizes high-frequencyphase modulation components.

4.3. From MADBIST to SP-BIST

The Mixed Analog-Digital Built-In Self-Test (MADBIST) concept [TR93b] de-scribed in Sec. 1.2.6 was introduced to ease production testof embedded ADCsand DACs in ICs. The following features make MADBIST a good starting pointfor the development of an RF self-test concept:

• The stimulus, a multi-tone signal, is generated entirely inthe digital do-main.

• The response is analyzed entirely in the digital domain, delivering spectralinformation.

• Analog signal paths remain (nearly) untouched.

In contrast to e.g. HBIST, parameters extracted by spectraltechniques have "real-life" meanings like noise level or tone amplitude which allow easy implementa-tion of tolerance bands for pass / fail decisions. As a consequence, complex mea-surement scenarios like signal-to-noise ratio or -3dB frequency can be reducedto a few measurements.

Building upon the basic MADBIST concept, a new self-test solution for RF PLLshas been developed under the name ofSpectral PLL BIST(SP-BIST). Fig. 4.3shows both concepts side by side. The main difference between the two conceptsis the embedding of the DUT:

• The PLL RF output has to be demodulated and digitized to obtain a base-band signal containing frequency and phase deviation. The ADC output isdigital and can be processed right away.

• The PLL can be modulated directly with a digital bit stream. In contrast,the analog ADC input requires an analog multiplexer, an auxiliary DACand an analog reconstruction filter.

SP-BIST has been optimized for low chip area and low ATE requirements. Thishas been achieved mainly by an optimized test partitioning between BIST andATE and by reducingaccuracywithout sacrificingprecision(Sec. 4.4); the mea-surement bias is removed on the ATE:


4.3. From MADBIST to SP-BIST 91

CUT

Ana.

Dig.SDM

DA

C

Data Bus

AA−Filter

f

DSP

DUT Optional Loop−Back Test

Control Bus

Rec−Filter

fSW

MUX

1b A

ux−

DA

C

Multi−ToneGenerator

MADBIST

f

Bandpass

ANA

BIST

IN

CTRL

OUT

ANA

DATABIST

AD

C

(a)

Multi−Tone

−FM−DemodΣ∆

SP−BIST

Generator

f

Envelope

t

Dig.

RFSDM

DSP

CUT

Polar−Modulator

RF TransmitDUT

FrequencyWord + Modulation

Control and Data Bus

Bandpass

PathTX

OUTBTX

Σ∆ −PLL

BUSBIST

OUT

(b)

Figure 4.3.: Mixed Analog-Digital BIST (MADBIST) (a) vs. Spectral PLL BIST(SP-BIST) (b)



Reduction of tester bandwidth: Only high-speed operations are performed on-chip; the result is generated as a static word that is read-out via the controland data bus of the DUT.

The staggered forth order tunable band-pass filter has a low scalloping lossthat tolerates slight deviations between stimulus and band-pass filter fre-quency. This allows coarse coefficient quantization reduced coefficientaccuracy improves selectivity in comparison to the second order filter ofthe original design.

The coarse coefficient quantization results in a slight deviation between tone fre-quency and the center frequency of the filter which could be tolerated due to thelow scalloping loss of the new staggered filter. The remaining systematic errorsand bias were removed in software on the ATE.

It should be noted that MADBIST can be implemented with nearly no cost to-gether with the SP-BIST: The multi-tone generator has a parallel output that canbe used to stimulate e.g. DACs and anΣ∆M output for ADC - testing, requiringonly an additional one-bit DAC and a simpleRC low-pass filter.

4.4. Partitioning of Test Hardware

Minimum hardware complexity of the additional BIST blocks is obtained by per-forming as much signal processing as possible on the automated test equipment:high-speed data acquisition and compaction is performed on-chip, linearizationand other slow but complex algorithms can be performed by theautomated testequipment (ATE). Measurements need to beprecise(highly repeatable) but notnecessarilyaccurate(close to the true value) as long as thebiascan be correctedlater on (Sec. 2.1.2). Fig. 4.4 visualizes the difference between accuracy andprecision using the well-known target analogy.

(a) (b) (c)

Figure 4.4.: Measurements with low accuracy and high precision (a), high accuracy andlow precision (b) and high accuracy and high precision (c)


4.5. Simulation Methodology 93

In this work, the following operations are performed on the ATE to minimizehardware:

• Gain correction (neither stimulus nor band-pass gain is normalized)

• Frequency dependent band-pass gain (Sec. 6.3.4)

• Correction of non-linear dependency between programming parameter andstimulus resp. band-pass center frequency (Sec. 7.1.1)

• Frequency dependent stimulus amplitude (Sec. 7.1.2)

4.5. Simulation Methodology

The paradigm shift from pure analog RF ICs to highly integrated System-On-Chip (SOC) solutions described in the introduction also hasa major impact onverification methodology. A few years ago the borderline between analog anddigital circuitry was well defined: RF ICs had a relatively low complexity andwere implemented on technologies optimized for analog performance. RF blockswere simulated using special RF simulators like SpectreRF or ADS which offersimulation modes optimized for RF problems like harmonic balance or periodicsteady state analysis. These simulation modes are extensions of SPICE-like (Sim-ulation Program with Integrated Circuit Emphasis) analog simulators which areessentially non-linear differential equation solvers. Detailed device and parasiticsmodels and the complex simulation algorithms limit the number of devices thatcan be simulated at the same time. Therefore, verification onchip level usuallyis performed by running an analog simulation of the whole chip with simplifiedanalog behavioral models for the RF blocks.

DSP functionality was implemented on a separate chip in a standard CMOS tech-nology and verified using digital hardware description languages (HDL’s) likeVerilog, VHDL etc. with event-driven simulators optimizedfor large digital de-signs.

Simulation of analog designs with small digital parts (big A, small d) like anADC with self-calibration can be sped up using mixed-mode simulators whichcouple an event-driven simulator core with a non-linear differential equationsolver. However, this approach is still too slow for complexchips, long timeframes or when there is a close interaction between analog and digital parts.

Analytical approaches using Matlab, Excel etc. can verify chip performance onan abstract level (level plans etc.) but integration of digital circuit blocks to verify



e.g. a calibration algorithm is difficult and slow.

Current RF SOCs integrate RF building blocks together with digital logic ex-ceeding a million gates in some cases [SML+04]. Calibration algorithms involvecomplex interactions between RF and digital parts, noise performance is deter-mined by analog and digital parameters alike. These systemscannot be simulatedwith a mixed-mode simulator, much less with SPICE type tools. The target is an"unified functional verification approach" i.e. using behavioral models for the RFblocks that can be simulated using an event-driven, discrete time simulator.

Fortunately, modern HDL’s like VHDL have powerful signal algorithmic capa-bilities allowing an efficient modeling of analog blocks in the digital domain:s-domain transfer functions can be translated into the discrete-timez-domain[Mün04]; oscillators generate events timed with their oscillation frequency andphase noise is described by jitter processes [SFB05]. This approach allows tofreely mix abstract behavioral models with gate level digital blocks. In this work,VHDL was chosen as the modeling language because its behavioral possibili-ties are far superior to Verilog. The suitability of SystemCwas also tested in aMaster thesis [Lay05] but at that time, stability and tool chain support were notconvincing.

Matlab provides the missing capabilities of digital simulation environments forpost-processing and plotting data in the frequency domain (Sec. 4.5.5).

4.5.1. Special Requirements for PLLs

The simulation of PLLs is a challenging task due to the large range of time con-stants: TheΣ∆PLL of the CUT has an output frequency around 4 GHz (Tvco =250 ps), a reference frequency of 26 MHz (Tre f = 38.5 ns) and a loop filter cornerfrequency of 100 kHz (τ = 15.9 µs). In order to verify spectral purity, the loopfilter voltage has to be calculated with a precision of a fewµV. Classical mixed-signal simulation has proved to be far too time consuming, a faster method is toapply the event-driven approach known from digital simulation.

A block diagram of the CUT is shown in Fig. 4.5. The simulationmethodologyhas originally been developed by the author to verify the correct lock-in behav-ior of the PLL and to simulate the total phase noise performance at the VCOoutput stemming from digitalΣ∆-quantization noise and jitter in the VCO.Σ∆-quantization noise is produced by the SD-modulator and the multi-modulus di-vider. Accumulative (FM) and non-accumulative (PM) jitters are included in theVCO model as described in [GKM+03, SFB05]. The required noise parametersare extracted from analog simulations.



In this work, correct interaction betweenΣ∆PLL and SP-BIST in the time andfrequency domain is verified using this method.

Phase Frequency

Detector

Loop Filter VCO

∆Φ

reference

frequency output

frequency

1/N

Divider

Σ∆ Modulator

Σinteger

part

fractional

part

Figure 4.5.: Block diagram of Fractional-N PLL

Fig. 4.6 shows the partitioning of the system for simulationpurposes: Most partsof the PLL and the BIST circuit like theΣ∆ modulator and multi-tone generatorhave been designed in VHDL anyway, others like the multi-modulus divider orthe phase detector are high-speed logic blocks that are described in behavioralVHDL easily. The modeling of two analog blocks - the VCO and the loop filter -in a discrete-time environment is described in the next section.

4.5.2. Discrete Time Modeling of Analog Blocks

Loop Filter

The loop filter of the CUT is a non-integrating (type I PLL), third order analoglow-pass (Fig. A.1). For DT simulations, it is modeled as a DTdirect-form filter(A.1.2), obtained by bilinear transform of the CT transfer function (A.1). Thefilter calculation is performed twice per filter clock periodwhich has an arbitraryfrequency that should be 10x ... 20x higher than the maximum input frequencyto achieve a reasonable accuracy of the DT filter characteristic. Higher clockfrequencies slow down the simulation unnecessarily.

However, the sampled filter model creates major problems forPLL simulations:The filter runs with a fixed sampling periodTS, f ilt while the charge pump can



MMDVHDL (Beh)

VHDLBISC

CUT

SP−BIST

DUT

VCOVHDL (real)

Loop FilterVHDL (real)

PD/CPVHDL (Beh)

VHDLControl Unit and Registers

MASHVHDLPredist.−Filt.

Gauss− and

VHDL

FIFO

VHDL

Plo

t

Stim

uli

VH

DL

VH

DL

ref

fref

mod

Stim

ulus

Gen

erat

orM

ulti−

Ton

e

RF

Res

pons

e A

naly

zer

Spe

ctra

l Out

put

f

Figure 4.6.: Simulation setup for CUT and SP-BIST

basically switch at any time1. This means, the filter model will react to a changeof the charge pump output with an average latency ofTS, f ilt /2, creating the beatfrequency effect betweenfS, f ilt and fre f shown in Fig. 4.7 forfS, f ilt = 2 GHzand fre f = 26 MHz. In the frequency domain, the strong ripple of the loopfiltervoltage in Fig. 4.7 created spurious sidebands with a level of -81 dBc. The filtersampling frequency has to be increased to thousands of GHz before the simula-tion artifacts become reasonably small, slowing down simulation tremendously.

Figure 4.7.: PLL simulation error due to sampled filter model

1Limited only by the minimum VHDL simulator resolution of 1 fs.



Instead, a much more efficient solution has been developed where the timingerror of the sampled filter is translated into a scaled amplitude of the next inputvalue for the filter (App. A.1):

The timing error is corrected in the filter model by translating it into an “analog”amplitude value which can be handled by the filter without error. The modeltracks the time between the last switching of the phase detector / charge pumpand the next sampling clock event and scales the filter input with the ratio of thistime and the full sampling period (“fractional” compensation) (Fig. 4.8).

t

Filt in

V tune

Thigh

CP

FiltClk

S,FiltT

Figure 4.8.: Principle of fractional compensation

This linear compensation produces small "kinks" in the loopfilter voltage everytime the charge pump CP switches that are visible in Fig. 4.9.However, the spuri-ous sidebands due to the sampling error are reduced by approx. 40 dB, requiringno further refinement of the model.

VCO Modeling

The efficiency of VCO simulation is increased tremendously by ignoring theamplitude information and regarding only the zero crossings. This simplificationis justifiable for the case of PLL simulation as the output is amplitude limitedanyway. In the analog world, VCO amplitude noise is converted to phase noisein the limiting stages that can be included in the VHDL phase noise model.

The VHDL model in App. A.2 calculates the ideal VCO period in fs. Last cy-cle’s truncation error, i.e. the remainder is added to the current period to avoidaccumulation of the truncation error as this would give a period error of ca. 0.5 fs(Sec. 4.5.3).



4.5.3. Limitations of Event-Driven Analog Simulation

Analog simulators use elaborate algorithms to solve non-linear differential equa-tions and adjust the simulation time-step according to signal transients and ac-curacy requirements. An event-driven simulator is only capable of calculatingexplicit equations likex(n) = Asinω0tn at pre-calculated times stored in an eventqueue.

Simulating the amplitude and frequency of anLC-oscillator with a SPICE sim-ulator requires only the model parameters and netlist elements without user in-teraction. For an event-driven simulation, the oscillatorneeds to be modeled e.g.using the well-knownLC-tank formula.

The amplitude resolution of floating point real numbers in event driven simula-tors is the same as in analog simulators (data type double with 52 bits for themantissa):

ε = 2−52 ≈ 2.2·10−16

This corresponds to approximately 16 decimal digits of accuracy and is morethan sufficient for most applications.

Timestep resolution is a different matter: In VHDL and SystemC, events aretimed using a 64 bit integer variable and a minimum timestep of Tq = 1 fs. Theresulting maximum simulation time is 263fs≈ 2 1/2 hrs which is plenty for thepurposes of this work. However, this quantization leads to atiming error∆T < Tq

when timing events are derived from calculations in real format (see VCO model).The truncation will create the event a fraction of a fs earlier than calculated. Foran oscillator, the calculated periodT0 is shortened by∆T resulting in a smallfrequency error∆ f .

∆ f = f0,Q− f0 =1

T0−∆T− 1

T0≈ 1+∆T/T0

T0− 1

T0=

∆T

T20

≤ TQ

T20

(4.5.1)

For a target oscillator frequency aroundf0 = 4 GHz, a worst case estimation∆T = TQ = 1 fs yields∆ f = 16.8 kHz (4.5.1). This frequency error is too largefor a precise simulation of most communication standards.

Tracking the difference between calculated and quantized period and correctingit in the next period brings the average frequency error to zero at the price ofintroducing a period jitter. The jitter has a uniform distribution in the range



−TQ/2. . .+TQ/2 with zero mean, varianceσ2 = T2Q/12 and an RMS valueσ =

TQ/(2√

3) = 0.29 fs.

In driven blocks like flip-flops or buffers, this jitter modulates the phase witha constant power spectral density (PSD) in the range 0. . . f0/2 (cyclostationarynoise). Converting the jitter to phase error by multiplyingit with ω = 2π f0 yieldsthe quantization noise power, constant phase PSD and the phase noise over thebandwidth ofB = f0/2 (4.5.2) - (4.5.4):

PQ,N = σ2ω2 =(π f0TQ)2

3= 52.6·10−12W ≡−102.8dBW (4.5.2)

Sφ ( f ) =2PQ,N

f0= 2.63·10−20 W

Hz≡−196dBc/Hz (4.5.3)

L ( f ) =Sφ ( f )

2≡−199dBc/Hz (4.5.4)

This "simulation quantization noise floor" is low enough forPLL / VCO applica-tions with a minimum noise floor of -160 . . . -170 dBc/Hz. In autonomous blockslike oscillators, the jitter modulates the period: Referred to T0 = 250 ps, the unitinterval jitter isJUI ,rms ≈ 1.2 ·10−6. This jitter is white FM phase noise with aPSD of ca. -134 dBc/Hz at 1 MHz offset.

The period quantization error bears a strong correlation tothe carrier periodwhich may produce spurious lines. To decorrelate the quantization error, some jit-ter with defined amplitude and spectral characteristic is added (Sec. 4.5.4) whichis also used to model FM and PM noise in the time domain.

4.5.4. Noise / Jitter Modeling

In an event-driven language like VHDL, phase noise can only be representedin the time domain i.e. as jitter. Therefore, the first step has to be to transferphase noise specifications from the frequency into the time domain. Here, onlythe special case of white noise is described, although methods for discrete-timemodeling of colored noise and power-law random processes like 1/f noise havebeen developed [DDHSW01].

In the simplest case, phase noise has a white spectrum and a Gaussian amplitudedistribution. It is specified by a single figure in the frequency domain because thePSD is constant over frequency. Correspondingly, in the time domain the jitter



is completely described by its standard deviationσ . In spite of its simplicity,this noise / jitter model describesAdded White Gaussian Noise(AWGN) that ispresent in many real-world systems with sufficient accuracy. It is converted totiming jitter by non-linear signal processing stages like limiters or logic gates.

How can white noise be modeled in VHDL?Non-autonomousblocks like a logicgate or a buffer process events at their inputs and pass the result on to the outputwith a certainlatency. This latency depends on the slew rate at the input, thespeed of the actual circuit etc. and varies in a random fashion due to thermal noisein the circuit. Modulating thelatencyof the digital model with a random processwith Gaussian distribution gives white phase (PM) noise spectrum, achievingthe wanted effect. The VHDL model for such a random process isdescribed inApp. A.3.

Oscillators areautonomousblocks where thermal noise creates to random fluc-tuations of the oscillation period. Hence, modulating theperiodof an oscillatormodel with a suitable random process creates whitefrequency(FM) noise. AVCO model containing both FM and PM noise is described in App.A.2.

4.5.5. Spectral Estimation of Simulation Results

In contrast to analog or mixed-signal simulators, digital simulators offer no post-processing options to regard simulation results in the frequency domain. Theworkaround to this drawback is based on the solution described in [Kun05],where the period data of the VCO is written to a text file. Spectral analysisof the period data, contained in the deviations of the zero crossings from idealtimes, is performed with MATLAB (Sec. 2.4).

4.5.6. PLL Simulation Results

Some simulation results are presented to demonstrate the power of the developedsimulation and modeling method. All the examples in this section have beensimulated with an unmodulated PLL at a fractional frequency. The left abscissadisplays the level of spectral (spurious) lines, the right one has been correctedwith the resolution bandwidth for noise levels.

Fig. 4.9 shows a simulation of the loop filter output voltage ripple, createdby the filter’s finite suppression of the PLL reference frequency. The pk-pkamplitude is approx. 10µV, as predicted by circuit simulations, resulting in aVCO peak frequency deviation of∆ f = 265Hz. The VCO gain is 53 MHz/V.



Fig. 4.10(a) shows the corresponding PLL phase noise spectrum with the spu-rious line at 26 MHz and a level of -106 dBc, the same result is obtained bycalculation (2.3.16), proving the validity of the simulation setup. Phase noise inthe simulation is due to theΣ∆-modulation of the MASH modulator.

Tune

∆f

fref1 /

10 µVpp

530 Hzpp

V

CP

Figure 4.9.: Simulation ofΣ∆PLL tuning voltage withfre f = 26 MHz andfS, f ilt = 1 GHz

In a practical PLL, thermal noise sources lead to a much higher noise level. In-stead of adding individual noise source, their integral effects are modeled inFig. 4.10(b): At high frequencies, noise typically is dominated by the VCObuffer (PM jitter, noise floor), at lower frequencies by the VCO itself (FM jit-ter, -20 dB/dec). For frequencies below the loop bandwidth (in-band noise), thenoise level should be constant (disregarding flicker noise). However, this canonly be guessed from looking at the simulation results as long simulation timesand very large result files are needed to improve the frequency resolution.



Figure 4.10.: Simulation ofΣ∆PLL spectrum without modulation (a) and with FM andPM jitter modeling (b)


There is no carrier, there is only concentratednoise.

B.-G. Goldberg 5Test Tone Generation

Test signal generation as the first part of SP-BIST is developed in this chapter.The most suitable method for this work, a digital oscillatorbased upon a tunable,undamped resonator with a low-passΣ∆-attenuator, is described in detail. Up-conversion by theΣ∆PLL as the circuit-under-test (CUT) into the RF domain isanalyzed as well.

As shown in Sec. 3.2, most analog parameters (e.g. VCO and phase detectorgain, loop filter time constants) of the PLL directly influence the loop bandwidth,making measurement of this parameter especially powerful for detecting catas-trophic and parametric faults. For this purpose, a base-band test-tone generatoris needed with the following requirements:

• Little area overhead

• Reusability for new products and technologies

• Robustness against parameter variations

• Autonomous operation, i.e. without interaction with otherblocks

• Multi-tone generation for efficient tests in the frequency domain

These demands can only be fulfilled with a mainly digital concept. As men-tioned before, quantitative frequency domain characterization is performed more

104 5. Test Tone Generation

efficiently using multi-tone signals. Several methods for the digital generation ofsuch signals are compared next.

5.1. Principle of Digital Sine Generator

5.1.1. Direct Digital Synthesis

Direct digital synthesis (DDS) is a table look-up scheme where a digitized sinefunction is suitably compressed and stored in a read-only memory (ROM). Differ-ent signal frequencies are generated by using a phase accumulator with differentincrements to address the ROM, the content is converted intoan analog signalwith a DAC. For the purpose of BIST tone generation, this approach is too com-plex and leads to a large area overhead.

5.1.2. Arbitrary Waveform Generation

Arbitrary waveforms can be efficiently encoded into aperiodic pulse-density mod-ulated (PDM) orΣ∆M serial bit streams. This principle is also based on a look-up table, although the "table" contains only single-bit data that are read out witha high oversampling rate. Compact implementations mandatethe use of ringbuffers and hence approximating the signal byperiodicbit streams, still requir-ing a large number of registers (a few hundred to a few thousand) for high-qualitysignals.

Generation of multi-tone signals has been demonstrated in [HR98, DR99]. How-ever, the proposal of re-using on-chip RAM or scan chain flip-flops for patternstorage is in contrast to the requirement of an autonomous test block and is diffi-cult to implement in a standard digital design flow. Another disadvantage is thata new pattern needs to be loaded into the chip for each different test case (e.g.amplitude, frequency), increasing test time and volume of test patterns.

5.1.3. Lossless Digital Resonator

In principle, a lossless resonator is the most simple implementation for a sineoscillator with tunable frequency and amplitude. While analog oscillators requiresome form of gain control to stabilize the amplitude in presence of gain and other


5.1. Principle of Digital Sine Generator 105

parameter variations, this should not be necessary for digital implementationsdue to their deterministic nature.

Here,direct-form(Fig. 5.1(a)) resonators and resonators based onlossless digitalintegrators(LDI) are regarded (Fig. 5.1(b)) as both allow placing the pole on theunit circle and tuning the resonance frequency with a singleparameter:

2−a = −1

y[n]

−1z−1z1−a

(a)

z −1

−1zLDI (BE)

LDI (FE)

−g

x[n]

(b)

Figure 5.1.: Implementations for undamped digital resonators: directform (a) andLDI-based (b)

The characteristic equation for an undamped resonator (poles on the unit circle)has been derived in (2.7.13):

∆ = 1−2cosΩrz−1 +z−2 = 0

The coefficients of the two resonator types above for undamped resonance aredetermined by comparing the coefficients of their characteristic equation to thegeneral resonator equation (2.7.13). The following condition for undamped reso-nance has been derived in Sec. 2.7.1 for thedirect form resonator in Fig. 5.1(a):

∆ = 1+a1z−1 +a2z−2 ⇒ a1 = −2cosΩr and a2 = 1 (5.1.1)

TheLDI-based resonator in Fig. 5.1(b) is a loop of twolossless digital integra-tors, one of them in a forward Euler (FE), the other one in a backward Euler (BE)integrator configuration. Its characteristic equation is derived using Mason’s rule[Dor92], yielding the condition for undamped resonance as

∆ = 1− (2−g)z−1 +z−2 ⇒ 2−g = 2cosΩr . (5.1.2)

It can be shown that the LDI-based resonator has a higher poledensity and hencebetter SNR for low frequencies (nearz = 1), making it more suitable for thiswork.



In both implementations, the coefficienta2,Q is exactly 1, ensuring place-ment of the pole on the unity circle. The quantization of coefficient a1,Q =Q−2cosΩr,Q = −2cosΩr,Q generally results in a slight shift of the resonancefrequencyΩr,Q but does not move the pole from the unit circle.

For small resonance frequenciesΩr ≪ 1, the approximation cosΩr ≈ 1−Ω2r /2

yields the result

Ωr = arccos(

1− g2

)≈√

g for Ωr ≪ 1 (5.1.3)

which is the same result as for an analog or SC oscillator consisting of a two-integrators loop (Fig. 5.2), e.g. [HBKZ84]. Its oscillation frequency is deter-mined by the characteristic equation

∆ = 1− gs2 = 0 ⇒ ω =

√g. (5.1.4)

x(t)

−g

(a)

−g x(t)

s1

s1

(b)

Figure 5.2.: Oscillator based on analog integrators (gain control not shown): (a) principleand (b) signal-flow graph

In general, implementations of digital oscillators made from these resonators (orany other) will fail. This can be traced back to the inevitable signal quantizationafter multiplication, creating pseudo-random errors thatcan create distortions,amplitude fluctuations or even quench the oscillation. A solution to get aroundthis problem is shown in Sec. 5.2.


5.2. Digital Resonator with Low-PassΣ∆-Modulation 107

5.2. Digital Resonator with Low-PassΣ∆-Modulation

5.2.1. Principle

In principle, a compact test-tone generator with programmable resonance fre-quency can be constructed from the ideal digital undamped resonator (Fig. 5.3)described in Sec. 2.7.2.

z−1

z−1

x [n]b

ax [n]LDI a

LDI b

b

z

a

−1

Figure 5.3.: Principle of LDI based oscillator

Analytical expressions for output signal frequencyωsig, amplitudexa,xb and ini-tial phaseφa,φb depending on sampling frequencyfs, coefficientsa, b and theinitial conditionsxa(0),xb(0) have been derived in [LRJ94]:

ωsig = fsarccos

(1− ab

2

)for 0 < ab≤ 2 (5.2.1)

φa = arctansin(ωsigTs)xa(0)

(1−ab−cos(ωsigTs))xa(0)+axb(0)

= arctansin(ωsigTs)xa(0)

−abxa(0)/2+axb(0)(5.2.2)

xa =(1−ab)xa(0)+axb(0)

sin(ωsigTs+φa)(5.2.3)

Results forφb andxb are attained by exchangingxa with xb anda with −b. Forsmall coefficients|ab| ≪ 1, the following approximations hold true

1−cos√

ab≈ ab2

and arccos

(1− ab

2

)≈√

|ab|,



yielding the following simplified relations by settingxb(0) = 0 [Mün05]:

ωsig ≈√

ab fs (5.2.4)

φa = −arctan2sin(ωsigTs)

ab≈−π/2, φb = 0 (5.2.5)

xa ≈xa(0)

sinφa≈ xa(0), xb ≈ xa(0)

√ba

(5.2.6)

(5.2.4) - (5.2.6) show that frequency and amplitude of the test tones can be setindependently. The amplitude is controlled via the initialconditions of the statevariables.

Practical implementations battle with with finite accuracy, making it difficult tomaintain a stable oscillation. This is true even for a resonator topology like theLDI based resonator where the poles remain on the unit circlewhen the idealcoefficient values are quantized. A solution is shown in the next section.

5.2.2. Σ∆-Attenuator

As multiplication increases the word length, the product has to undergosignal re-quantization before it can be fed back into the loop again. This process createsor destroys energy, depending on the kind of quantization applied (truncation,rounding etc.) and the sign of the signal, preventing stableoscillation for allresonators.

[LRJ94] describes a stable digital oscillator based on Fig.5.3 where one multi-plier is replaced by a fixed bit shifter, providing multiplication by 2−α withouthardware. The second multiplier is substituted by aΣ∆-attenuator that first con-verts the parallel datax[n] into an equivalent oversampled single-bit streamxd[n](Fig. 5.4(a)). Multiplication ofxd[n] with the coefficientb now only requires se-lection of+b or−b in a multiplexer, depending on the sign ofxd[n] (Fig. 5.4(b)).

[LRJ94] and subsequent publications focus on the facts thatthis Σ∆-attenuatorsaves chip area and delivers an oversampledΣ∆M-bitstream from which variousanalog and digital output signals can be derived. While this is certainly true,the main benefit of theΣ∆-attenuator is that itavoids truncation or rounding,enabling stable oscillation in the first place: It processesthe result of the multi-plication bya (= bit shifter) with full word length, its output has the wordlengthof coefficientb. The sampling rates at both input and output of theΣ∆M are the



SDM LPF

fs/2 fs/2

b x[n]

x[n] b x[n]

b

M x N Bit Multiplier

M x 1 Bit Multiplier

xd[n]

M

M

N

M+N

N

x[n]

b

(a)

SDM LPF

LPFSDM0

1

xd[n]

+b

−bx[n]

x[n]

b x[n]

N Bit 2:1 Multiplexor

b

N x 1 Bit Multiplierb x[n]

N

N

xd[n]

(b)

Figure 5.4.:Σ∆M attenuator, principle (a) and MUX implementation (b)

same, there is no decimation involved. The two integrators in the loop limit thesignal bandwidth and attenuate the quantization noise.

Proving the stability of the oscillator described above is not trivial: The signaltransfer function of theΣ∆M has to have exactly unity gain and a latency of oneclock sample, otherwise the oscillation condition is violated, leading to satura-tion or quenching of the oscillation. Many publications describing this kind ofoscillator only rely on empirical observations; [Zie96] proves rigorously that astable oscillation can be achieved with an oscillator building upon a 2nd orderΣ∆M.

For this work, additional VHDL simulations have been performed to verify the



x [n]

x [n]0

1

SDMdigital

z−1

z−1

b

a = 2−α

a xd [n]a

MUX +b

LDI a

LDI b−b

z−1−1

+1

z−1Quantizer

xd[n]

−−x[n]

Figure 5.5.: LDI oscillator usingΣ∆M attenuator

amplitude stability over a period of several 100 ms.

5.2.3. Multi-Tone Signal Generation

Multi-tone signals can be generated by adding the signals ofseveral sine gen-erators, increasing the hardware complexity in a linear waywith the number oftones. A more economic approach is using time division multiplexing for shar-ing the oscillator hardware. The price for generatingL tones is a reduction oftheeffective sampling rateto fS,e f f = fS/L; each register has to be replaced by achain ofL registers to store the independent state variables for eachtime slot (=phase). During theL different phases, the multiplexer selects the correspondingpair of coefficientsbi , −bi to implement theL different multiplication factors. Atthe outputsxb[n] andxda[n], theL different tones are contained in theL phasesof the signal. Subsequent low-pass filtering removes the frequency componentaroundfS/L and leaves the sum of the baseband component of all tones.

This modification requires only four additional registers per tone (Fig. 5.6)[LRJ94] in theΣ∆M and the oscillator itself. The adders and the bit shifter areshared among the signals saving approx. 50% chip area compared to individualtone generation.

The comparison of Fig. 5.7 and Fig. 5.8 confirms that the inband spectra (f <100 kHz) of parallel output and SDM bit stream are essentially the same. Erro-neously, both spectra have been normalized with the FSR of the parallel output,



MUX

SDMdigital

z−1

z−1 z−1

−1

+1

z−1

−−Quantizer

x[n] xd[n]

f /2s

−b2

2+b

1+b−b1

1011

0100

z−1 z−1

z−1z−1

a = 2−α

xd [n]ax [n]a

2 k

Figure 5.6.: Two-tone LDI oscillator usingΣ∆M attenuator

104

105

106

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Frequency (Hz)

> 60

dB

SF

DR

(In

band

)

stim

S

(

dB /

Hz,

Spu

rs)

a1 = 2−4

b1 = 0.012634 => f

1 = 55.9 kHz

b2 = 0.12201 => f

2 = 173.7 kHz

Figure 5.7.: Spectrum of two-tone signal (parallel output) (fS = 26 MHz)



104

105

106

107

−150

−140

−130

−120

−110

−100

−90

−80

−70

−60

−50

Frequency (Hz)

stim

S

(

dB /

Hz,

Spu

rs)

a1 = 2−4

b1 = 0.012634 => f

1 = 55.9 kHz

b2 = 0.12201 => f

2 = 173.7 kHz

40dB/dec

> 60

dB

SF

DR

(In

band

)

→

Figure 5.8.: Spectrum of two-tone signal (SDM bit stream) (fS = 26 MHz)

which explains the difference in displayed output levels. The spurious lines areharmonic and intermodulation distortions created by quantization.

5.2.4. Quantization Noise

The quantization noise of theΣ∆M limits the useful signal bandwidthB of theoversampled oscillator. The achievable signal-to-noise ratio SNRdepending onthe effective oversampling ratioOSRe f f = fS,e f f/2B is [LRJ94]

SNR=π

2√

60OSR5/2

e f f. (5.2.7)

The effective sampling rate of a two-tone generator (L = 2) running with a sam-pling frequency offS = 26 MHz is fS,e f f = 13 MHz. The PLL under test hasa nominal loop bandwidth of 100 kHz, resulting SNR for different bandwidthvalues is given in Tab. 5.1.


5.3. Upconversion inΣ∆PLL 113

BW [kHz] 50 100 150 200 300 400

OSRe f fOSRe f fOSRe f f 130 65 43.3 32.5 21.7 16.3

SNR [dB] 108 93 84 78 69 63

Table 5.1.: SNR of two-tone generator depending on bandwidthBW

5.3. Upconversion in Σ∆PLL

In the MADBIST concept, the digital multi-tone signal had tobe converted andlow-pass filtered to obtain an analog test signal for the ADC.This auxiliary testDAC1 needs to have a performance that is superior to the ADC under test, re-quiring precision analog techniques. This is true even for oversampled single-bitΣ∆-DACs, where finite slew-rate, mismatch of rising and falling edge or ringingdeteriorate the analog signal [TR96].

In contrast, the digital modulation input of theΣ∆PLL offers a very efficient wayto apply a digital phase / frequency correction [MMNV04] or test tones to thePLL (Fig. 5.9): No additional filter is needed to reconstructthe sine tones fromthe oversampled data stream of the sine generator due to the low-pass character-istic of the PLL.

The output frequencyfout of a fractional-N PLL with a reference frequencyfre f

and a division ratioN = NI +NF , consisting of integer partNI and fractional partNF = FRAC/2w f , is given by

fout = fre f

(NI +

FRAC2w f

)= N fre f (5.3.1)

wherew f is the word length of the fractional accumulator andFRACis the frac-tional word. The PLL is frequency-modulated in the digital domain by addingmodulation dataD[n] to the fractional word. The modulation data is low-pass fil-tered by the closed loop transfer functionT(ω) of the PLL [GKM+03]. Withinthe loop bandwidth,|G(s)| ≈ 1 and the digital data directly affects the PLL fre-quency:

fout(n) ≈ fre f

(NI +

FRAC+D[n]

2w f

)= fre f

(N+

D[n]

2w f

)(5.3.2)

1Not to be confused with functional DACs on-chip which can be tested against the verified ADC.



PFDf

digitalSDM

÷N / N+1

0

1

f

dig

BIST BlockAdditional

0

1

VCOLoop FilterReference

RF out

Frequency

WordCarrier Freq.

TX Filter

Dig. MultitoneGenerator

TE

Data [SDM]

[SDM]

Figure 5.9.: Fractional-N modulator with test tone generation

WhenD[n] is a digital sine wave with frequencyfm and amplitude ˆm, a (normal-ized) peak PLL frequency deviation∆ f resp.y is created of

∆ f =m

2w f−1

fre f

2=

m2w f fre f and y =

∆ ff0

(5.3.3)

for m< 2w f−1. This corresponds to a frequency modulation indexβ f of

β f =∆ ffm

= yf0fm

=m

2w f

fre f

fm. (5.3.4)

Fig. 5.10 shows the simulated phase spectrum of a PLL, modulated by a two-tone signal (fm1 = 51 kHz and fm2 = 130 kHz). The phase deviation due to aconstant frequency drops with 20 dB/dec. Tones outside the loop bandwidth of100 kHz are attenuated additionally by the loop bandwidth. The tone outside theloop bandwidth appears attenuated by∆Sφ ≈ 12 dB. The conversionSy → Sφaccounts for 8 dB, the other 4 dB are due to the loop attenuation which is theparameter of interest. Obviously, an FM discriminator thatdeliversSy directlywould be a better choice for measuring the loop bandwidth.

A single-tone modulation of the RF carrier atf0 = 3.812 GHz with fm =67.7 kHz,w f = 23,m= 45800 andfre f = 26 MHz produces a peak (normalized)

frequency deviation of∆ f = 142 kHz resp.y = 3.72· 10−5 ≡ −85.6 dB. This


5.3. Upconversion inΣ∆PLL 115

104

105

106

−80

−70

−60

−50

−40

−30

−20

−10

0

10

20

20 lo

g |S

|

Avg. Freq. = 4.0001e+09HzMax: 23.7 dB at 50799.9 Hz

φ

Offset Frequency from Carrier (Hz)

∆

RBW = 600.0 Hz (27.8 dB Hz)

S

φ

Samples: 20000499

Figure 5.10.: Simulated phase spectrum of two-tone modulated PLL

corresponds to an FM indexβ f = 2.1 = φ that is identical to the peak phasedeviation, givingSφ ( fm) = φ2/2 = 2.2≡ +3.4 dB.

The small angle approximation is no longer valid for such a large phase deviation;relative carrier and sideband amplitudes in the amplitude spectrum have to becalculated via (2.2.13):

a0 = J0(2.1) = 0.1666≡−15.6dB

a1 = J1(2.1) = 0.5683≡−4.9dB

a2 = J2(2.1) = 0.3746≡−8.5dB

Most conventional spectrum analyzers cannot demodulate FMsignals, display-ing theamplitudespectrumS( f ) as in Fig. 5.11 from which information aboutthe modulation signal can only be extracted with difficulty.As the PLL output isnot routed to a pin, the RF signal had to be tapped off by inductive coupling witha "sniffer" coil to the VCO coil inside the chip which accounts for the attenuationof ≈ 30 dB.

In contrast, the built-in FM discriminator gives the frequency deviation spectrumin Fig. 7.13 resp. Fig. 7.14 for a two-tone spectrum.



Att 10 dB*

1 AP

CLRWR

A

* RBW 5 kHz

VBW 20 kHz

SWT 40 msRef −20 dBm

Center 3.8122787 GHz Span 1 MHz100 kHz/

−120

−110

−100

−90

−80

−70

−60

−50

−40

−30

−20

1

Marker 1 [T1 ]

−76.26 dBm

3.812195513 GH z

Da e: 16.MAR.2007 13:59:55t

Figure 5.11.: Single-tone modulation (measured with spectrum analyzer)

All simulations in this chapter were performed with a standard VHDL simulator,using the methodology described in Sec. 4.5.


Wichtig ist, was hinten raus kommt.

H. Kohl 6On-Chip PLL Response Analysis

On-chip response analysis in the frequency domain is developed as the secondpart of a SP-BIST. After an overview of conventional, swept-tuned spectrumanalysis techniques, a robust sigma-delta frequency discriminator (Σ∆FD) ispresented as an alternative technique for demodulation anddigitization. TheΣ∆-modulated bit stream of theΣ∆FD is decimated and filtered with a digitalnarrowband filter, based on digital resonators. It is very robust against quanti-zation and coefficient truncation errors and requires only one parameter to tunethe center frequency. The amplitude of the filtered frequency band is estimatedwith a digital envelope detector.

6.1. Spectrum Analysis Overview

6.1.1. Direct Spectrum Analysis

As shown in Sec. 2.3.2, phase noise can be measured by selecting a single side-band, converting phase to voltage that is measured in the amplitude domain. Inpractical implementations, the filtering is performed at anintermediate frequencyto relax the filter requirements. In the lab, thisdirect spectrum analysisis often

118 6. On-Chip PLL Response Analysis

performed with a spectrum analyzer. Fig. 6.1 shows a typicalanalog implemen-tation of aswept-tuned, superheterodyne spectrum analyzer[Agi06] (simplifiedrepresentation). The RF input frequency range of interest is mixed down to afixed intermediate frequency (IF) in several stages by sweeping the first localoscillator frequency.

IF = 321.4 MHz IF = 21.4 MHz3 GHz

3.3 GHz 300 MHz 18.4 MHz

IF = 3.6214 GHz

RF in

LO2 LO3 LO4

Display

FilterVideo

BW = RBWIF = 3 MHz

Log. Amp.

Env

elop

eD

etec

tor

6.52 GHz...

3.62 GHz

Swept LO

SweepGenerator

Figure 6.1.: Principle of analog swept spectrum analyzer [Lil05]

A band-pass filter withfixedcenter frequency and selectable bandwidth filters outthe frequency of interest, the frequency axis of the displayis swept synchronouslywith the first LO to plot amplitude values at the corresponding frequency points(Fig. 6.2). The narrowband output signal of the band-pass isthen demodulatedby an envelope detector.

With the advent of fast, high resolution ADCs in the 1970s, digital signal pro-cessing (DSP) started to replace more and more analog signalconditioning inspectrum analyzers, enabling faster sweep times and higherdynamics.

Envelope and Signal Detection

Analog swept-spectrum analyzers demodulate the intermediate frequency signalfor the video display by envelope detection. In its simplestanalog form, this isachieved with a resistively loaded diode and a low-pass filter (Fig. 6.3) whoseoutput only follows the average of the signal envelope but not its instantaneousvalue.


6.1. Spectrum Analysis Overview 119

fIF

Frequency (Hz)

φ| (

dB /

Hz)

|S

Figure 6.2.: Swept-tuned spectrum analysis: The input signal is converted with a variableLO frequency and analyzed with a fixed band-pass

t

IF Signal

t

Demodulated Signal

Figure 6.3.: Envelope detector

Video Filtering

The video filter in Fig. 6.1 smooths the (logarithmic) PSD data for the displaywhen the video bandwidth is smaller than the resolution bandwidth. A very sim-ilar effect can be achieved by averaging several measurements (trace averaging)which is preferable for a BIST application as it can be performed off-chip insoftware.

The advantages and disadvantages of a conventional spectrum analyzer for phasenoise measurements are:

+ Available in most labs

- AM and PM cannot be distinguished



- Resolution limited close to the carrier due to drift between device and spec-trum analyzer frequency

- LO phase noise limits sensitivity

6.1.2. Indirect Measurement of Angle Modulation

High resolution phase noise measurements are often performed indirectly by de-modulating the signal. This can be performed by aphase detectorthat convertsphase fluctuations to amplitude fluctuations. Hence, the PSDof the phase de-tector output voltage is proportional to the phase instability. The most commonimplementation is a mixer operating in quadrature (both inputs at same frequencybut phase shifted by∆φ = π/2) (Fig. 6.4). The second input can be a copy of thesignal to be measured (self-referenced measurement) or be provided by a PLL tomaintain quadrature.

v(t) ∝ sin(∆φ(t)) ≈ ∆φ(t) for ∆φ(t) < 0.1 rad (6.1.1)

+ Highest dynamic range

- Tunable resolution filter required

- Delay difference between both paths limits the

- Sensitive against frequency difference between both paths (drift)

LPF

s(t)

π/4

Kφ ∆φ(t)

Figure 6.4.: Phase detector phase noise measurement

Introducing a delay∆T in one path of Fig. 6.5 creates a linear phase shift with off-set frequencyfm of δφ ∝ 2π fm∆T. Hence, frequency fluctuations are convertedto phase fluctuations that can be measured with a phase detector as before.

+ More robust against frequency difference between both path

- Low sensitivity at low offset frequenciesfm


6.2. FM Demodulation UsingΣ∆ Frequency Discriminator 121

LPF

PSfrag s(t)

∆T

K f ∆ f (t)

Figure 6.5.: Frequency discriminator based phase noise measurement

- Resolution filter needs to be tunable

The latter architecture has been used for on-chip phase noise measurement[VGKB+07, KBK07] with excellent results, however, for this work the chip areafor the analog components is far too large. An architecture that avoids the tunabledelay line and the high-performance analog mixer is described in Sec. 6.2.

6.2. FM Demodulation Using Σ∆ FrequencyDiscriminator

6.2.1. Overview of FM Demodulation

Demodulating and digitizing of the frequency information has to be performedunder the same restrictions as outlined in the motivation:

• Little area overhead

• Reusability for new products and technologies

• Robustness, i.e. mainly digital implementation

• Autonomous operation, i.e. requiring no functions from other blocks

The spectrum analyzer architectures described in Sec. 6.1 are "very analog" andcomplex, requiring large area implementations [VGKB+07, KBK07]. Therefore,a different approach is needed for extracting and digitizing the phase / frequencymodulation information from the PLL signal without analog downconversion.On the other hand, the output of a PLL used for frequency multiplication is anarrowband RF signal with a constant, nearly rail-to-rail amplitude. Such a signalcan be processed with digital circuits, requiring no precision analog components.



Subsampling

Subsampling or downsampling (Sec. 2.5.4) is a well known technique in digitalmultirate systems or high-speed ADCs for processing a high-frequency, narrow-bandwidth signal in a lower Nyquist zone (Sec. 2.5.4).

As RF signals in most transmission standards are narrowbandsignals, subsam-pling recently has received a lot of attention for RF downconversion. No analogmixer is required and the concept is seemingly digital, however, practical im-plementations of "digital" subsampling receivers battle with mainly analog prob-lems:

Aliasing: The frequency bands ofall Nyquist zones are mapped onto the base-band which can create huge aliasing problems and SNR reduction whenoperating in a high order Nyquist zone i.e. with a large ratiobetween band-width and sampling frequency.

Bandwidth: The bandwidth of the sampler needs to exceed the highest signalfrequency independently of the sampling frequency.

Jitter: The sampling clock needs to be exceedingly stable as jitter introduced atthat point of the signal chain is referred to the RF period, not the samplingperiod.

Consequently, the subsampling receiver presented in [MLS+04] operating di-rectly in the RF domain is a complex analog circuit, consisting of a cascadeof filters, subsamplers and a precision ADC which is unsuitable for a BIST im-plementation.

PLL FM Discriminator

PLLs are frequently used for FM demodulation by tapping off the control voltageof the VCO but obviously it makes no sense to implement a second PLL on-chipfor testing purposes with a performance superior to the circuit-under-test.

Digital FM Discriminator

Digital FM demodulation of high-level signals is possible by only evaluating theposition of the zero crossings. This can be performed by somesort of early-late detection against a reference signal. In this work, asigma-delta frequencydiscriminator(Σ∆FD), a fully digital circuit, is used for FM demodulation.



The period deviations could also be measured directly with atime-to-digital con-verter (TDC) (Sec. 1.2.7). However, TDCs are large precision analog blocksthat are ill suited for BIST purposes. In a digital PLL where aTDC is used forphase detection, the availability of a digital measure for the phase error offersnew self-test options with very little overhead [EBSB07, SP09].

Q

−1

+1

Q

−1z

Σ∆

∆

QuantizationSubtraction

−

s[n] sd[n]

Integration

Accumulator

(a) First order sigma-delta modulator (Σ∆M)

D−FFD

QΣ∆

÷N / N+1modN φdiv

φrefif (t)

Channel Word(Integer Part)

Subtraction QuantizationPhase

y[n]

Integration and

Modulus DividerDual

(b) First order sigma-delta frequency discriminator (Σ∆FD)

Figure 6.6.: Comparison ofΣ∆M andΣ∆FD

6.2.2. Principle of First Order Σ∆FD

In analogy to the conventionalΣ∆M in Fig. 6.6(a) (Sec. 2.6), a sigma-delta fre-quency discriminator (Σ∆FD, Fig. 6.6(b)) generates a coarsely quantized, noiseshaped, oversampled approximation to the instantaneous input frequencyfi(t).It is capable of replacing both the demodulator and the ADC, making it an idealcandidate for robust BIST applications.

The principle ofΣ∆FD is closely related to a fractional-N synthesizer [BC94]where a fine granularity of output frequencies is achieved byalternating the di-vision ratio between two or more values. When the divider values are switchedsufficiently fast, most of the switching activity is suppressed by the loop filter andthe output frequency is proportional to the average division ratioN. This works



particularly well when the divider sequence is coded as aΣ∆M data stream wherethe switching activity is concentrated at high frequencies(Sec. 2.6).

f

D−FFD÷N / N+1

N mod

N.F

divf

SDM

frefFilter VCO

WordFrequency

Mod in

PFD

RF out

(a)

Frequency Word

D−FFD

÷N / N+1N mod

fdiv

freff

N.F Filter

Dem.

Out

RF in

N

(b)

Figure 6.7.: Principle ofΣ∆FD (b), derived fromΣ∆-Frac-N-PLL (a)

If the VCO is replaced by an input signal with a frequencyfi,0(t) in the range

N fre f < fi,0(t) < (N+1) fre f , (6.2.1)

a divider sequence can be constructed that minimizes the phase deviation be-tween reference signal and divided input signal and thus produces an averagedivided frequency that is equal to the reference frequency,

fi,0(t)/N = fdiv[i] = fre f and φi,div(t) = φdiv(t)+2π fre f (6.2.2)

When the divided input frequency is higher than the referencefrequency, thedivision ratio has to be set to÷(N + 1) until the reference phase overtakes thedivided RF phase. At that point, the division ratio is set back to ÷N until thedivided RF phase leads again (Fig. 6.8). In other words: the phase of the divideroutputbracketsthe reference phase (Fig. 6.9) rather than locking to it.

A suitable divider sequence is provided by a D-Flip-Flop (D-FF) which samplesthe divided RF phase at each rising edge of the reference clock (Fig. 6.6(b)),providing a binary quantizationy[i] of the divider phase deviationφdiv = φi,div−φi,re f (bang-bangor early-late phase detector).

Starting with perfectly aligned phases att = 0 and a division ratio ofN, the



divider phase deviation after one reference period is

φdiv(Tre f) = φi,div(Tre f)−φi,re f(Tre f) =φi,0(Tre f)

N−2π

=Nφi,re f(Tre f)

N−2π = 2π

N−NN

<2π

N. (6.2.3)

A similar result is obtained easily for a division ratio ofN+1, defining the rangeof the phase deviation at the divider output:

− 2π

N+1< φdiv(t) <

2π

N(6.2.4)

For input frequencies outside the range given above, the phase deviation becomeslarger than 2π/N and cycles are lost, overloading theΣ∆FD. A PLL signal gen-erated from the same reference frequencyfre f has a bandwidthB≪ fre f for sta-bility reasons, fulfilling (6.2.1) in most cases. The notable exception is when theaverage input frequencyf0 is near one of the integer frequencies and additionalfrequency modulation pushes the instantaneous frequencies outside the range.

N + 1 = 5N = 4 N = 4

N = 4.25

N = 4 N = 4 N + 1 = 5

div,kt

y[i]

REF

RF

DIV

t/Tref

φ [i]div

t

t k−1∆ t k∆div,2Tdiv,1T

div,1

10 2 k

Figure 6.8.: Signals in first orderΣ∆FD: Transient view

Modulation frequency has to be less thanfre f/2 to avoid aliasing. As the multi-modulus divider averages overN resp.N + 1 input cycles, it acts as an anti-aliasing filter on the frequency deviation.

The equivalence to conventionalΣ∆M is seen clearly by regarding

• For each reference cycle where the division ratio is set to÷(N+1) insteadof ÷N, one RF cycle is swallowed from the output of the divider, subtract-ing a phase of 2π/N.



10 01

φ / 2π

41 2 3

Binary phase error approximation

4

/ Nφi,0

i,0φ / (N+1)

φ i,0φ i,div

1

/ N[i]

i,refφ

i,refφi,div

− φ [i]

[i] =φdiv

3

2

1

ref

[i] =

t / T

i

N N+1 N N+1N+1

y[i]

Figure 6.9.: Signals in first orderΣ∆FD: Phase view

• As phase is the integral of frequency, this corresponds to a perfect integra-tion of the frequency error.

6.2.3. Signal-to-Noise Ratio of Σ∆FD

In this section, a linearized model for theΣ∆FD is developed to calculate thesignal-to-quantization noise ratio (SQNR) [Bax99, p. 39 ff.,p. 107 ff., 146 ff.],[BC94]. It will also be shown that the output signal of theΣ∆FD is a coarselyquantized approximation to therelative frequency deviation y(t) which has beendefined in (2.2.4) as

y(t) :=fi(t)− f0

f0=

fi(t)f0

−1 =∆ f (t)

f0=

12π f0

dφ(t)dt

.

The average deviation∆t0[i] from the ideal periodT0 is a good approximation tothe frequency deviationy[i] ≈ y(t) during that cycle:

y(t) =fi(t)f0

−1≈ y[i] =f0[i]f0

−1 =T0

T0[i]−1 =

T0

T0 +∆t0[i]−1

=1

1+∆t0[i]/T0−1≈−∆t0[i]

T0(6.2.5)



In the derivation of (6.2.5), two approximations have been made:

• The duration of thei-th divider cycleTdiv[i] at the output of the MMDis equal to the accumulated RF signal periodsT0, j of the previousN[i]RF cycles (approx.Tre f ). Consequently, only the average periodT0[i] ofthese accumulated cycles can be measured instead offi,0(t) or T0, j . This isequivalent to a low-pass filtering of the period / frequency deviation withsincπ f Tre f .

T0[i] =Tdiv[i]N[i]

=∑N[i]

j=1T0, j

N[i]= T0 +∆t0[i] with T0 =

Tre f

N(6.2.6)

• Truncating the series expansion 1/(1+x) = 1−x+x2− . . . after the first

term introduces a nonlinearityε ≈−x2 = −(∆t0[i]/T0

)2. For narrowband

modulation,x≪ 1, and the nonlinearity can be neglected.

First, a linearized model is developed for the multi-modulus divider as the centralcomponent:

Them-th rising edge of the divider output is triggered by thek-th rising edge ofthe RF signal at the timetdiv[m]. The modulus inputb[i] ∈ 0;1 and the integerdivision ratioN set the division ratioN[i] = N+b[i] of the i-th divider cycle:

tdiv[m] =m

∑i=1

Tdiv[i] =k

∑j=1

T0, j =m

∑i=1

N[i]

∑j=1

T0, j =m

∑i=1

N[i]T0[i]

−• tdiv(z) =N(z)T0(z)1−z−1 =

N(z)1−z−1

(T0 +∆t0(z)

)(6.2.7)

(6.2.7) is the base for the MMD model in (6.10(b)).

÷N / N+1N mod

divt [m]T0,j

N + b[i]

(a)

0T (z) = T +0 ∆t (z)0

−11−z1 t (z)divN

b(z)N(z)

(b)

Figure 6.10.: Multi-modulus divider (a) and DT model (b)

As it has been assumed that the average period of the divided signalTdiv[i] is madeequal to the reference periodTre f in a feedback loop and as

∣∣N−N[i]∣∣ < 1, the



difference between the average division ratioN (m→ ∞) and its approximationoverm divider cycles is bounded by|ε[m]| < 1/m:

NT0 = Tdiv[i] = Tre f with N = limm→∞

1m

m

∑i=1

N[i] =1m

m

∑i=1

N[i]+ ε[m] (6.2.8)

The instantaneous output phase of the dividerφi,div[m], referred to the referenceperiod, is calculated from (6.2.7) and (6.2.8):

φi,div[m] =2πtdiv[m]

Tre f=

2π

NT0

m

∑i=1

N[i](T0 +∆t0[i]

)=

2π

N

m

∑i=1

N[i]

(1+

∆t0[i]T0

)

= 2πm+ ε[m]+2π

N

m

∑i=1

N[i]∆t0[i]

T0with |ε[m]| = 2πm|ε[m]|

N<

2π

N

−• φi,div(z) =2π

N

N(z)1−z−1

(1+

∆t0(z)T0

)(6.2.9)

≈ 2π

N(1−z−1)

(N+N(z)

∆t0(z)T0

)(6.2.10)

(6.2.10) is the base for the multi-modulus divider (MMD) model in Fig. 6.11.

1 / T0

−11−z1 2 π

Nφ

i,div (z)

0 ∆t (z)0T +

N

b(z)N(z)

Figure 6.11.: Linearized model for multi-modulus divider phase

Next, the D-FF with the reference frequency input is added tothe model to com-plete theΣ∆FD. The instantaneous phase of the reference frequency after m ref-erence cycles isφi,re f [m] = 2πm. The output of the D-FF is a coarse quantiza-tion of the difference between instantaneous reference anddivider phase with∆Q = 2π/N: When the divided phase is early, the output goes high, otherwise itis low. Using (6.2.2), the difference of both instantaneousphases is the divider



phase deviationφdiv[m]:

φdiv[m] = φi,div[m]−φi,re f [m] =2π

N

m

∑i=1

N[i]∆t0[m]

T0−• (6.2.11)

φdiv(z) = φi,div(z)−φi,re f(z) =2π

N

N(z)1−z−1

(1+

∆t0(z)T0

)− 2π

1−z−1

=2π

N

11−z−1

(N(z)

(1+

∆t0(z)T0

)−N

)

=N(z)

N

2π

1−z−1

(1+

∆t0(z)T0

)− 2π

1−z−1 (6.2.12)

The effect of the quantizer is modeled by adding the quantization noiseen =∆Q/

√12= π/N

√3 and one delay, yieldingb(z). The loop is closed by setting

N(z) = N+b(z):

b(z) = (φdiv(z)+en)z−1 =N+b(z)

N

2πz−1

1−z−1

(1+

∆t0(z)T0

)− 2πz−1

1−z−1 +enz−1

=

[1− (•)

N

2πz−1

1−z−1

]−1(N

N

2πz−1 (•)1−z−1 − 2πz−1

1−z−1 +enz−1)

=N(1−z−1

)

N(1−z−1)−2π(•)z−1

2πz−1

1−z−1

(N

N(•)−1+en

1−z−1

2π

)

=1

1−z−1

2πz−1 − (•)N

(N

N(•)−1+en

1−z−1

2π

)

≈−N+N(•)−1−N(•)−1en1−z−1

2πfor∣∣z−1

∣∣≈ 1

≈ N

(−N/N+

(1− ∆t0(z)

T0

)−en

1−z−1

2π

)for

∆t0(z)T0

≪ 1

≈ N

(y(z)+

N−N

N−en

1−z−1

2π

)(6.2.13)

(6.2.13) shows that the outputb[n] of the Σ∆FD is an approximation to the fre-quency deviationy(t), scaled withN. The DC-component ofy(t) is the fractionalword, i.e. the relative deviation from the integer channel.Quantization noise ishigh-pass shaped with 1− z−1. (6.2.12) and (6.2.13) are the base for Fig. 6.12.The high-pass characteristic of 20 dB/dec can be seen in Fig.6.13.



1N 1−z−1

z−1π2

1 / T0 refT ref1 / T0 ∆t (z)0T + e

n

Nb(z)

1

Figure 6.12.: 1st orderΣ∆FD model

The PSDSY of a signal with sinusoidal frequency modulation and peak frequencydeviationy is

Sy( fm) =y2

2=

(∆ f√2 f0

)2

.

At the output of the first orderΣ∆FD, frequency deviation is scaled withN, re-sulting in a signal power of

Sy,Σ∆FD( fm) = N2

(∆ f√2 f0

)2

. (6.2.14)

The noise power of a general first orderΣ∆-modulator is given by (2.6.6):

Nq(Bm ≪ fS/2) ≈ π2e2

n

3

(2Bm

fS

)3

=

(π∆Q

6

[2Bm

fS

]3/2)2

For the case of the first orderΣ∆FD,e2n = σ2

e = ∆2Q/12= π

2/3N2, noise is scaled

with (N/2π)2, resulting in

Nq,Σ∆FD(Bm ≪ fS/2) ≈ π2

3

(2Bm

fS

)3

· π2

3N2 · N

2

4π2 =

(π

6

[2Bm

fS

]3/2)2

.

(6.2.15)The ratio between modulation bandwidthBm and sampling frequencyfS, theoversampling ratioOSR, determines the SQNR of theΣ∆FD. In analogy to aconventionalΣ∆M (2.6.6), the SQNR of a first orderΣ∆FD can be calculatedfrom (6.2.14) and (6.2.15):

SQNR= 20log

(N∆ f√

2 f0

)

︸︷︷︸S

−20log

(π

6

[2Bm

fS

]3/2)

︸︷︷︸NQ

(6.2.16)

= −48.3dB− (−69.1dB) = 20.8dB (6.2.17)



using the numbers from the example in Sec. 5.3:f0 = 3.812 GHz andfS= fre f =26 MHz result inN = 146.62. The peak (normalized) frequency deviation is∆ f = 142 kHz resp.y = 3.72·10−5 ≡−85.6 dB. A bandwidth ofBm = 100 kHzhas been assumed. This low SQNR is partially due to the relatively low fre-quency deviation∆ f in comparison to the DC offset(N−N/N). Hence, a pre-cise measurement of the frequency deviation of single tonesnecessitates a narrowbandwidth.

103

104

105

106

107

−120

−100

−80

−60

−40

Frequency (Hz)

20 lo

g |S

| y

Samples: 145600

RBW = 1071.4 Hz (30.3 dB)

Figure 6.13.: Simulated two-tone spectrum atΣ∆FD output

104

105

−120

−100

−80

−60

−40

Frequency (Hz)

Samples: 145600

Freq. Points: 18201

RBW = 1071.4 Hz (30.3 dB)

20 lo

g |S

| y

Figure 6.14.: Simulated two-tone spectrum atΣ∆FD output (zoomed in)



The zoomed-in spectrum in Fig. 6.14 reveals some spurious lines between thetwo modulated tones, generated by the first orderΣ∆FD.

Spurious Tones of First Order Σ∆FD

As there is only one integrator in the loop (Fig. 6.12), the first orderΣ∆FD showsthe same spurious tones as a first orderΣ∆M (Sec. 2.6.3). These tones are dueto insufficient decorrelation of signal and quantization noise. In Σ∆FDs, espe-cially unmodulated signals (constant input frequency) canproduce strong spuri-ous lines. Modulation with e.g. a two-tone signal improves the decorrelation andhence the spurious performance.

6.2.4. Second Order Σ∆FD

Increasing the order of noise shaping reduces the spurious tones and improvesthe signal-to-noise ratio by shifting more quantization noise to higher frequen-cies. Unfortunately, the order of aΣ∆FD cannot be increased as simply as witha Σ∆PLLas the quantization error of the first stage is given by thephase differ-ence between reference and divided RF signal that is smallerthan an average RFcycle. It can either be integrated in an analog fashion with e.g. a charge pump ordigitally by oversampling the first.

Figure 6.15.: 2nd orderΣ∆FD (simplified) [BCR96]

[BC94] presents a second order multi-loopΣ∆FD architecture similar to Fig. 2.20using two charge pumps and an analog comparator. Mismatch between chargepumps in the multi-loop architecture can be avoided by an equivalent secondorder single-loopΣ∆FD (Fig. 6.15) similar to Fig. 2.22 [Bax99]. However, bothapproaches are not attractive for BIST implementations as they require large areaanalog blocks.


6.3. Spectral Analysis of Baseband Signal 133

The use of a multibit quantizer would also improve the SQNR. For this approach,the simple D-FF has to be replaced by multi-phase phase detector [RS01]. Thisrequires multiple phases of the reference clock which is themain drawback ofthis approach. The multibit "DAC" could be implemented witha multi-modulusdivider.

6.3. Spectral Analysis of Baseband Signal

6.3.1. Overview

In the last section, it has been shown that the output of theΣ∆FD is an oversam-pled,Σ∆-modulated approximation to the frequency deviation of theRF carrier.In contrast to a swept spectrum analyzer (Fig. 6.1 and Fig. 6.2), the demodulatedspectrum is fixed, starting at DC. As a consequence, the resolution filter now hasto be swept across the baseband (swept-filter spectrum analyzer, Fig. 6.16). Onepractical difficulty that has to be solved is that the bandwidth of the filter has toremain constant over the tuning range.

[TR95a] discusses the quality of three different methods for achieving this target:

Frequency (Hz)

| (dB

/ H

z)φ

|S

Figure 6.16.: Swept filter spectrum analysis: A tunable filter is swept across the basebandspectrum



Fast Fourier Transform (FFT)

While FFT has become the most common method for on-chip spectral analysis,it also requires the most hardware resources by far. More hardware efficient forthe calculation of individual spectral components of a discrete-Fourier transform(DFT) is the recursiveGoertzel algorithm. It can be implemented and analyzedas a direct-form IIR filter [TGS+09]. The high sensitivity of this filter type toquantization effects requires multipliers with a large word length.

Correlation

The spectral component at a certain frequency in a measured set of data can befound by correlation with a sine wave of the target frequency. This procedurecan also be related to the discrete Fourier transform and hasbeen standardizedas IEEE Std 1057. The quality of the spectral estimate is identical to a DFT.Unfortunately, the computational effort is also very high.

Narrowband Filtering

Using narrowband filtering, a similar quality of the spectral estimate can beachieved with low hardware complexity. As this is one of the main restrictions inthis work, the spectrum will be estimated with the narrowband filtering approach.This approach is especially well suited when only the analysis of a few frequencypoints is required as in the SP-BIST application.

6.3.2. Filter Topology

The output of theΣ∆FD is fed into the tunable narrowband filter, its center fre-quency is selected by the ATE or an external PC (Fig. 6.17). A digital envelopedetector (Sec. 6.3.5) tracks the amplitude of the frequencyband. Slow but com-putation intensive tasks like linearization, smoothing and logarithmic scaling areperformed off-chip.

Component variations and area limitations mandate the use of digital filters.Many different architectures for DT filters have been developed in the lastdecades, first for switched-capacitor (SC) implementations (continuous-valued),later for fully digital implementations (discrete-valued) to implement a desiredtransfer functionH(z). Under the assumption of infinite precision (or at least



fRF

Σ∆

N

PC or ATEEnvelopeFM Discriminator MultirateDetector

|| yS ( )cf

reff cf

demod. signal

modN÷N / N+1 D

t

of BP signalEnvelope

t

BP−filtereddemod. signal

Oversampled

BP Filter

SweepSP−BIST

f

Figure 6.17.: Principle of on-chip spectral PLL analysis

with floating-point arithmetics), these architectures produce identical input-output behavior. However, in most hardware implementations, silicon area andcomputing power are limited, permitting onlyfixed-point arithmetics. Thisis especially true for BIST applications where minimum areaoverhead is ofparamount importance.

With fixed-point arithmetics, filter architecture, internal word length and scal-ing strongly influence the performance: overflow, excessivequantization noise,deviations from the target transfer function or even instability may occur for non-optimum choices [CT06].

While non-recursive filters are inherently stable and relatively insensitive againstword length effects, low hardware complexity can only be achieved withrecur-sive filters: The poles in the transfer function enable sharp transitions betweenpass and stop bands with a much lower filter order than with non-recursive filterswhich are restricted to all-zero transfer functions. The non-linear phase trans-fer function of recursive filters can be ignored for applications where only themagnitude transfer function is specified (as in this work).

Still, recursive filters have lost a great deal of their popularity which may bedue to the available high integration densities, requiringno longer minimum areasolutions and to a lack of IIR design skills as the focus in most courses is on non-recursive filters [Lyo06]. This is especially true for more exotic topologies likethe resonators-in-a-loop described below which have sunk into near-oblivion.

The higher sensitivity of recursive filters to word length effects requiresrobustfilter topologies to achieve good performance even with short word-length of



registers (quantization) and coefficients (truncation). This allows reducing thesize of the coefficient multipliers which are the largest blocks in a digital filter.Dynamic range is limited by quantization noise on one side and saturation / over-flow on the other side. It can be shown that a robust filter design automaticallygives a good dynamic range [Fet97].

Tunable filters in BIST / BISC applications mandate a minimum number of tun-able coefficients as each coefficient has to be programmed during test and storedon chip. Especially for BISC applications, the computational complexity for cal-culating the coefficients e.g. from the center frequency of afilter has to be lowas well. Most tunable filters use non-recursive structures to guarantee stabilitywhile tuning the coefficients. These approaches also require high computationaleffort for coefficient calculation [SK97, ZB95].

256CIC

S,R2f = 3.2 kHzS,R1f = 812.5 kHz

BPA(f )| |x [n]i

fS = 26 MHz

CIC2

32

BP FilterDownsampling Envelope Detector

Figure 6.18.: Block diagram of spectral estimation

Signals with a high oversampling rate (ratio of sampling rate to signal bandwidth)like the sigma-delta modulated bitstream of theΣ∆FD in this work can be pro-cessed efficiently withmultirate systems. Fig. 6.18 shows the principle of themultirate spectral estimation developed in this work [MW06]. The band of in-terest is selected with a narrow, programmable resonator based band-pass filterrunning at a reduced sampling rate. The moving average in theenvelope detectoris calculated at an even further reduced sampling rate.

6.3.3. Downsampling Cascaded-Integrator-Comb Filters

The Σ∆FD bit stream has a high oversampling ratio that would require a highorder bandpass filter with precise coefficients when operating at the full samplingrate. Filter specifications can be relaxed bydownsampling(Sec. 2.5.4) beforedoing actual signal processing. TheΣ∆M coding of the bit stream concentratesthe quantization noise aroundfS/2, hence, proper low-pass filtering is requiredbefore decimation to avoid excessive aliasing.

Downsampling Cascaded Integrator-Comb(CIC) filters, are frequently used foranti-alias filtering of oversampledΣ∆M bitstreams before decimation because



Decimator

−R

−

z−1 z−R

−

z−1

R

f /Rsf s

CIC 2

x[n]

CIC 1

y[n] y[n/R]

z

Figure 6.19.: 2nd order CIC as anti-aliasing filter

of their hardware efficient, multiplier-less architecture(Fig. 6.19). The coarselyquantizedΣ∆M bitstream is converted to a wider word length at a lower samplingrate. The actual (single rate) CIC filter consists ofN sections of a digital integra-tor and a comb filter withR unit delays and behaves as amoving average filter,implemented in recursive form.

The integrator section generates a pole of orderN on the unit circle atz = 1( f = 0), the comb filterR zeros of orderN, distributed along the unit circle atej2kπ/R, k = 0. . .R− 1. The filter is only stable because the integrator pole iscanceledexactly(requiring fixed-point arithmetics) by a zero in the comb filtersection.

Integrator:HI (z) =Y(z)X(z)

=1

1−z−1 |HI ( f )| =∣∣∣∣

12sinπ f TS

∣∣∣∣ (6.3.1)

Comb Filter:HC(z) = 1−z−R |HC( f )| = |2sinπR f TS| (6.3.2)

Combining the transfer functions of integrator (6.3.1) andcomb filter (6.3.2)yields the CIC transfer functionsHCIC(z) andHCIC( f ) (6.3.3):

HCIC(z) =

(1−z−R

1−z−1

)N

and |HCIC( f )| =∣∣∣∣sinRπ f TS

sinπ f TS

∣∣∣∣N

(6.3.3)

OrderN and number of delaysR are the only two parameters for controlling thefrequency characteristic of a CIC filter.

When the number of delays in the comb filter is the same as the decimation ratio(Fig. 6.19), an especially efficient implementation is achieved by swapping deci-mator and comb filter stages and applying the Noble identity:The resulting struc-ture Fig. 6.20 (also called Hogenauer filter [Hog81]) has thesame transfer func-tion as Fig. 6.19 and requires only one delay per comb filter section ([Mey07]).Further reduction of hardware complexity is achieved by replacing one integratorand comb filter by an accumulate-and-dump block (Fig. 6.21).The frequency re-



Comb Filters

−1

−

z−1

−R

f s f /Rs

z−1z−1

Decimator

y[n/R]x[n]

Integrators

z

Figure 6.20.: Efficient implementation for second order downsamplingCIC filter(Hogenauer filter)

Comb Filter

f /Rsf s

z−1R

z−1

−z−1

RES

x[n] y[n/R]

Accumulate & DumpIntegrator

Figure 6.21.: Second order downsampling CIC filter with dump and reset

sponse of the downsampling CIC filters in Fig. 6.19 - 6.21 is identical to (6.3.3),but it is usually expressed as a function of the frequencyF , normalized w.r.t. thereduced sampling rate at the output (6.3.4):

|HCIC(F)| =∣∣∣∣∣sinπF

sinπFR

∣∣∣∣∣

N

≈ |RsincπF |N for F =f RfS

≪ 1 (6.3.4)

Some effects of multirate CIC filters can be seen from (6.3.4): The filter has aDC gain of G = RN, requiring an output word lengthWLout:

WLout = N⌈log2R⌉+WLin (6.3.5)

The sincN low-pass characteristic introduces adroop at the edge of the passbandFC (6.3.6).

|HCIC(Fc)||HCIC(0)| =

∣∣∣∣∣sinπFc

RsinπFcR

∣∣∣∣∣

N

≈ |sincπFc|N (6.3.6)

This droop is normally compensated in the subsequent filtering stage(s). In thiswork, compensation is performed off-chip to avoid additional hardware.

A more severe restriction isaliasing of signal components around multiples ofthe reduced sampling frequency, especially forΣ∆M bitstreams as in this applica-tion where the quantization noise is concentrated at high frequencies. The nulls



of the comb filter atF = k suppress multiples of the reduced sampling frequency,avoiding aliasing back to DC. The comb filter maxima are atF = k+ 1

2, thereforethe worst case alias suppression occurs at the passband edges fc,k = k fS/R± fcresp.Fc,k = k±FC with k = ±1,2, . . . (6.3.7) which are all mapped back toFc bydecimation (Fig. 6.22).

0 0.5 1 1.5 2 2.5 3 3.5 4−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Normalized Frequency F

20 lo

g | H

CIC

(F)

| [dB

]

Fc

Figure 6.22.: Transfer function of downsampling CIC filter withN = 2 andR= 4.Hatched regions are folded back toF = 0. . .0.25

∣∣HCIC(Fc,k)∣∣

|HCIC(Fc)|=


R

sinπFc

∣∣∣∣∣

N ∣∣∣∣∣sinπ(k±Fc)

sinπ(k±Fc)R

∣∣∣∣∣

N

=


R

sinπ(k±Fc)R

∣∣∣∣∣

N

(6.3.7)

≈∣∣∣∣

Fc

k±Fc

∣∣∣∣N

(6.3.8)

A higher decimation factor increases droop in the passband and aliasing for aconstant corner frequencyfc but reduces the requirements for subsequent filter-ing. Tab. 6.1 shows some typical cases. The configuration selected for this work,R= 32, N = 2 has been highlighted, the simulated output spectrum of theΣ∆FDwith the overlaid CIC frequency response is shown in Fig. 6.23.

As Σ∆M quantization increases towardsfS as well as the alias rejection of aCIC filter, the order of the CIC filter should be larger than theorder of theΣ∆-modulator. Fig. 6.24 gives a graphical representation of the quantization noise at



Order Rate Gain Passb. Droop (dB) Alias Rejection (dB)

N R (dB) Fc = 14

18

34

78

R2 − 1

4R2 − 1

8

1 256 48.2 -0.9 -0.22 9.5 16.9 50.3 56.3

2 16 48.2 -1.8 -0.45 19.0 33.7 52.3 64.4

2 32 60.2 -1.8 -0.45 19.1 33.8 64.4 76.4

3 16 72.2 -2.7 -0.67 28.5 50.6 78.5 96.6

3 32 90.3 -2.7 -0.67 28.6 50.7 96.6 114.7

Table 6.1.: Passband droop and alias rejection of CIC filters

103

104

105

106

107

−120

−100

−80

−60

−40

Frequency (Hz)

20 lo

g |S

| y

Samples: 145600

RBW = 1071.4 Hz (30.3 dB)

Figure 6.23.: Two-tone spectrum atΣ∆FD output with overlaid CIC frequency response(simulation)



the output of a CIC - filter versus the oversampling ratioOSR= fS/2 fc = R/2Fc

[Can86]. Quantization noise is shown for oversampled PCM (l = 0) andΣ∆M oforderl = 1 andl = 2, it is plotted relative to the level of Nyquist PCM with thesame quantization step size∆Q.

When the orderk of the CIC filter is larger by one than theΣ∆M (k = l +1), totaloutput noise is independent of decimationR for a givenOSR(horizontal lines).Lower decimation ratiosRdecrease the amount of aliasing, but the CIC filter alsohas a weaker low-pass characteristic. Starting from the intersection of thel -lineand theOSR, the output noise is found by following thek = l or k = l +1 line tothe value of the decimation ratio.

Oversampling Ratio

RM

SN

oise

[dB

]

Figure 6.24.:Σ∆M quantization noise after CIC filtering plotted against the oversamplingratio [Can86]

In this work, the first orderΣ∆FD (l = 1) delivers a bit stream with a samplingrate of 26 MHz. Only an order ofk = 2 was possible for the CIC filter due tosevere area restrictions.

As the signal bandwidth isfc = 200 kHz with special focus on the loop band-width of 0. . .100 kHz for measuring, a decimation factor ofR= 32 was chosen,giving an output sampling rate offS,R = 812.5 kHz. This low ratio between sig-nal bandwidth and sampling rate allowed an especially efficient implementationof the band-pass filters.



104

104

105

105

−120

−100

−30

−80

−20

−60

−10

−40

0

10

20

30

40

50

60

20 lo

g |S

| y20

log

|S

|

RBW = 1089.1 Hz (30.4 dB)

Samples: 4476f

Frequency (Hz)

Freq. Points: 18201

(a)

Freq. Points: 560Peak Value = 89.64 dB at 0 Hz

Samples: 145600

RBW = 1071.4 Hz (30.3 dB)

(b)

Figure 6.25.: Simulated two-tone spectrum atΣ∆FD output (a, zoomed in) and at theoutput of the downsampling CIC filter (b)



The spectrum at the output of the downsampling CIC filter (sampled at fS,R =812.5kHz) is shown in Fig. 6.25 together with the input spectrum,sampled atfS = 26MHz. As expected, the increasing droop of the CIC filter canbe seenabove 200 kHz and some folded back spurious lines. The frequency range ofinterest up to 200 kHz remains undisturbed.

6.3.4. Narrowband Filtering

As discussed in Sec. 6.3.2, spectral estimation of the decimated bitstream is per-formed with a tunable narrow band-pass filter where the center frequency is setwith few or even a single parameter to facilitate programming. Theabsolutebandwidth has to stay constant across the frequency range, requiring a specialfilter topology as most tunable filters have a constantrelativebandwidth referredto the center frequency. A similar concept has first been presented in [TR95a] forthe BIST of ADCs.

Undamped Resonator

fk k fz−1

z−1

y [n]2

y [n]1

−

w[n]

x [n]

Figure 6.26.: LDI based resonator

The tunable band-pass is implemented with the undamped LDI-based resonatorin Fig. 6.26 that has also been used in the multi-tone generator (Sec. 5.1.3). Itis placed in the resonator-in-a-loop structure in Fig. 6.27(Sec. 2.9.3) to obtaina defined filter characteristic. Its transfer function can bederived using Mason’srule:

H1(z) =z−1(1−z−1

)

1−(

2−k2f

)z−1 +z−2

Outputy1 (6.3.9)

H2(z) =kf z−1

(1−z−1

)

1−(

2−k2f

)z−1 +z−2

Outputy2 (6.3.10)



29 ·kf 1 40 200 512 715 1024

fr [kHz] 0.253 10.1 50.8 135.4 199.9 394.8

Table 6.2.: Resonance frequency forfS,R = 812.5 kHz

The poles of (6.3.9) and (6.3.10) are given by:

zp1,2 = 1−k2

f

2±

√(2−k2

f

)2−4

2= 1−

k2f

2± j√

k2f −k4

f /4 (6.3.11)

The resonator poles have a radius ofr = 1 (undamped oscillation), as a conse-quence the resonance frequencyΩr is the same as the pole angleθp:

Ωr = θp = arctan

√k2

f −k4f /4

1−k2f /2

= arctan

√k2

f −k4f /4

√1−k2

f +k4f /4

= arcsin√

k2f −k4

f /4 = 2arcsinkf /2≈ kf for kf < 0.1 (6.3.12)

using arcsinx= arctan x√1−x2

= 2arctan x

1+√

1−x2and arctanx= 2arctan x

1+√

1−x2.

The absolute resonance frequencyfr is calculated with the reduced samplingfrequencyfS,R = 812.5 kHz. Tab. 6.2 gives some example values.

fr =Ωr

2πfS,R =

fS,R

πarcsin

kf

2≈ kf fS,R

2π(6.3.13)

⇔ kf = 2sinπ frfS,R

≈ 2π frfS,R

(6.3.14)

Resonator-in-the-Loop

An additional feedback path stabilizes the undamped resonator in Fig. 6.26 byproviding a defined amount of dampingkBW. The resulting structure has an ap-proximately constant bandwidthB or quality factorQ depending on the positionof the feedback (Fig. 6.27). Its transfer function is derived from (6.3.9) resp.(6.3.10) [PM93]:

HBP,i(z) =YBP(z)X(z)

=kBWHi(z)

1+kBWHi(z)(6.3.15)



fk k fz−1

kbw

x[n] y [n]bp1z−1

y [n]bp2

−

−

Constant Q

Constant BW

−

Figure 6.27.: Resonator based filter with constantB or constantQ

At the resonance frequency,Hi(z) becomes infinity, the corresponding resonantgain of the band-passHBP,i(z) is unity for both resonator types. Forrp ≈ 1, thisalso corresponds to a constantpeak gainof ≈ 1.

For resonator 1, the band-pass transfer functionHBP,1(z) is given by (6.3.16).

HBP,1(z) =YBP1(z)

X(z)=

kBWH1(z)1+kBWH1(z)

=

kBWz−1(1−z−1)1−(

2−k2f

)z−1+z−2

1+kBWz−1(1−z−1)

1−(

2−k2f

)z−1+z−2

=kBWz−1

(1−z−1

)

1−(

2−kBW−k2f

)z−1 +(1−kBW)z−2

(6.3.16)

The center frequency of the band-pass isΩc ≈Ωr = θp ≈ kf (6.3.12); comparisonof (6.3.16) with (2.7.3) shows that the pole radius is independent of the poleangle:

rp =√

a2 =√

1−kBW ≈ 1− kBW

2⇔ kBW = 1− r2

p (6.3.17)

Approximations for bandwidth, quality factor and settlingtime of a high-Q sec-ond order resonator have been derived in (2.7.22) - (2.7.24), showing that BP1has aconstant absolute bandwidthover the tuning range. Therelative band-



0 1 2 3 4

x 105

−50

−40

−30

−20

−10

0

Frequency [Hz]

|H(f

)| (

dB)

Figure 6.28.: Transfer functions of resonator based filter with constant BW forkBW = 2−8 andkf = 2−9 ·100. . .1000

width decreases and theQ-factor increases for higher center frequencies (6.3.18):

BBP,1 ≈1− rp

πTs≈ kBW

2πTs

QBP,1 ≈θp

2(1− rp)≈ kf

kBW≈ 1

Brel(6.3.18)

τBP,1 ≈1

2πBBP,1=

TS

kBW

The peak gain of Fig. 6.27 increases slightly over the frequency band of inter-est due to the influence of the conjugate pole at−θp. It is eliminated by themodified structure Fig. 6.29 [TR93a] with an additional zeroat z= −1 (6.3.19)as described in Sec. 2.7.4. Fig. 6.28 shows the resulting transfer functions fordifferent center frequency settings.

HBP,1b(z) = HBP,1(z)1+z+1

2

=kBW

2

(1−z−1

)(1+z−1

)

1−(

2−kBW−k2f

)z−1 +(1−kBW)z−2

(6.3.19)

The resulting peak gain frequencies arefc,1(kf = 1) = 135.560 kHz andfc,2(kf =1+ 2−9) = 135.850 kHz, the frequency step is 290 Hz. The -3 dB bandwidth isB−3 = 505 Hz and the -60 dB bandwidth isB−60 = 284 kHz, giving a large shapefactor (= weak selectivity) ofSF= B−60/B−3 = 562 .



kbw

z−1

fk k fz−1

bp1,by [n]

−x[n]

− 1/2

Figure 6.29.: Resonator based bandpass with constant peak gain

At the same time, the -3 dB bandwidth is so narrow that a tone inthe middlebetween the maxima of two filter settings appears to have an amplitude thatis lower by ∆Hsc = 1.2 dB compared to a tone exactly at the center frequency(Fig. 6.31(a)). This effect is known as(peak) scalloping loss[Har78] from DFTanalysis, creating errors for the measurement of narrowband signals.

0.5 1 1.5 2

x 105

−2

−1.5

−1

−0.5

0

0.5

1

Frequency f [Hz]

|H(f

)| (

dB)

1.98 1.985 1.99 1.995 2

x 105

−1.6

−1.4

−1.2

−1

−0.8

−0.6

−0.4

−0.2

0Time: 199448.4375

Amplitude: −0.0016361

Frequency f [Hz]

|H(f

)| (

dB)

Figure 6.30.: Bandpass gain|HBP( f )| (a) and worst case scalloping loss∆Hsc (b) of 2nd

order resonator (kBW = 2−8, kf = 1)

Forth Order Band-Pass

The design tradeoffs between selectivity, i.e suppressionof out-of-band tones,and constant transmission in the passband are rather limited for a second orderresonator. A highQ-factor enhances the selectivity at small frequency offsets,but at larger offsets only the weak first order roll-off is effective. Cascading twoidentical second order resonators gives a forth order resonator with improved roll-off that also has constant bandwidth and a peak gain of 1. However, Fig. 6.31(c)



Filter |H (Ωc)| |Hrp| BN B−3 B−60 SF

N ∆kf ·29 (dB) (dB) (kHz) (kHz) (kHz)

2 0 0 — 0.794 0.505 135.9 269.1

4 0 0 — 0.398 0.325 16.1 49.5

4 1 −2.5 — 0.530 0.458 18.4 40.3

4 2 −7.3 0.08 0.908 0.822 24.3 29.6

4 3 −10.8 1.3 1.189 1.18 29.7 25.2

Table 6.3.: Bandpass properties atkf = 1 ( fc = 135.4 kHz)

shows that the peak scalloping loss is even worse in comparison to the secondorder resonator (∆Hsc = 2.5 dB).

One solution for reducing the variation∆Hsc of the measured peak amplitude is toincrease the bandwidth by using astaggered filter: Two second-order band-passsections are cascaded with slightly different center frequencies, giving a widerpassband and forth order transition regions.

Fig. 6.31(e) and 6.31(f) show a forth order band-pass where the coefficients de-terming the center frequency of the two section differ by∆kf = 2·2−9 or 584 Hz.This gives a reduced peak scalloping gain of∆Hsc = 0.5 dB and a selectivitySF = 29.6 that is improved by nearly an order of magnitude compared tothesecond order resonator.

However, this approach also has some drawbacks: The staggering reduces thepeak gain and hence the SNR of the filter. The relationship (6.3.13) betweenthe parameterkf and the center frequencyΩc is only approximately linear, thedifference in center frequencies that corresponds to∆kf = 2 ·2−9 increases withlarger values ofkf . As a consequence, the bandwidth and also the peak gain|H(Ωc)| of the staggered band-pass now depend on the center frequency Ωc.When∆kf ≥ 2 · 2−9, the resonator response has two distinct peaks and a mini-mum, giving a passband ripple|Hrp| that also depends onΩc.

Here, a staggered tuning of∆kf = 2 ·2−9 has been selected as a compromise be-tween low scalloping loss and tolerable parameter variations over the frequencyrange which is limited to approx. 200 kHz for the target application.

Tab. 6.3 and 6.4 compare the properties of different bandpass implementationsand their variation over the frequency range.



1.354 1.355 1.356 1.357 1.358 1.359 1.36 1.361

x 105

−3

−2.5

−2

−1.5

−1

−0.5

0

Frequency [Hz]

|H(f

)| (

dB)

(a)

0.5 1 1.5 2 2.5 3

x 105

−60

−50

−40

−30

−20

−10

0

Frequency [Hz]

|H(f

)| (

dB)

(b)

1.354 1.355 1.356 1.357 1.358 1.359 1.36

x 105

−3

−2.5

−2

−1.5

−1

−0.5

0

Frequency [Hz]

|H(f

)| (

dB)

(c)

1.3 1.35 1.4

x 105

−60

−50

−40

−30

−20

−10

0

Frequency [Hz]

|H(f

)| (

dB)

(d)

1.354 1.356 1.358 1.36 1.362 1.364

x 105

−10

−9.5

−9

−8.5

−8

−7.5

Frequency [Hz]

|H(f

)| (

dB)

(e)

1.25 1.3 1.35 1.4 1.45

x 105

−60

−50

−40

−30

−20

−10

Frequency [Hz]

|H(f

)| (

dB)

(f)

Figure 6.31.: -3 dB and -60 dB bandwidth of different band-pass filters with kBW = 2−8

atkf = 1: (a) and (b) second order, (c) and (d) forth order and (e) and (f)forth order with staggered tuning∆kf = 2·2−9



0.5 1 1.5 2

x 105

−10

−9

−8

−7

−6

−5

Frequency f [Hz]

|H(f

)| (

dB)

1.985 1.99 1.995 2

x 105

−9.4

−9.3

−9.2

−9.1

−9

−8.9

Frequency f [Hz]

|H(f

)| (

dB)

Figure 6.32.: Bandpass gain|HBP( f )| (a) and worst case scalloping loss∆Hsc (b) of 4th

order resonator (kBW = 2−8, kf = 1, ∆kf = 2·2−9)

Filter |HBP( fc)| (dB) |Hrp,max| ∆Hsc B−3 (kHz)

N ∆kf ·29 fc,min fc,max (dB) (dB) fc,min fc,max

2 0 0 0 — 1.7 0.505 0.505

4 0 0 0 — 3.3 0.325 0.325

4 1 −3.4 −1.9 — 1.2 0.426 0.521

4 2 −9.0 −6.0 0.47 0.5 0.710 0.981

4 3 −12.4 −9.3 2.2 0.5 1.021 1.394

Table 6.4.: Variation of bandpass properties overfc,min = 10 kHz. . . fc,max= 200 kHz

The equivalent noise bandwidthBn was calculated numerically using (6.3.20).Noise bandwidth variation over the frequency range was comparable toB−3, i.e.±16 % or±1.3 dB for ∆kf = 2−8.

Bn =1

H2( fc)

∫ ∞

0H2( f )d f (6.3.20)

Another option for reducing the variation of the measured peak amplitude wouldbe to apply "video filtering", i.e. calculating the average of several frequency binswhich is best performed off-chip. When the scaling factors are made dependenton the frequency bin, the influence of the non-equidistant frequency bins can alsobe compensated.



Settling Time

The response time of a filter is inversely proportional to itsbandwidth, whichputs a lower bound on its time resolution.

As shown, in Sec. 2.7.5, the settling time-constantτ can be estimated from thepole radius (2.7.24):

τ ≈ 12πB

=TS

1− rp

6.3.5. Envelope and Display Detection

Ideally, the estimation of the power spectral density requires averaging of thesquared band-pass output signal (6.3.21). When only low-bandwidth signalsshall be transferred to the ATE, these calculation have to beperformed on-chip.

Ps = limT→∞

12T

∫ T

−Ts2(t) dt = s2(t) (6.3.21)

However, the output of a narrow band-pass is nearly sinusoidal and the signalpower can be approximated by (6.3.22), calculating only theaverage of the ab-solute signal value on chip and performing squaring and scaling off-chip. Incontrast to analog circuits, perfect calculation of the absolute value requires verylittle hardware in digital signal processing.

|ssin(t)| = 2sπ

⇒ Ps,sin = s2(t) =s2

2=

π2

8|s(t)|2 for sinusoids (6.3.22)

For slowly varying signals, ideal averaging can be approximated by a movingaverage over a finite timeT:

Ps ≈ Ps(T) =1

2T

∫ T

−Ts2(t) dt (6.3.23)

This is analogous to simple analog envelope detection performed with a diodeand an RC low-pass filter. The choice of the cut-off frequencyis determined bytwo contradicting requirements, the settling time and the ripple attenuation. Botheffects should generate a total error of less than 0.5 dB or 6%:

• The settling timeTsettleof the filter to an accuracy of 0.25 dB (3%) shouldnot exceed 5 ms for an acceptable measurement time.

• The ripple of the demodulated, rectified, squared signal dueto the secondharmonic of the test tone should be less than 0.25 dB (3%).



Assuming a first order system with a time constant ofτ = 1/2π fc, settlingwithin 2% is achieved afterTSettle≈ 4τ, limiting the cutoff frequency tofc >2/πTSettle= 0.64/TSettle= 0.13 kHz.

The amplitude of the harmonics of a full-wave rectified sinusoid (only even har-monics), relative to the DC component are given by [BS81, p. 617]:

a2k

a0=

2(2k+1)(2k−1)

=415

for k = 1 (6.3.24)

The (relative) ripple of the squared sum of a DC signal with level A and a sinusoidwith amplitudec is approximated by

ε = 0.03> a20−min(a0 +csinωt)2 ≈ 2

ca0

⇒ ca0

< 0.015. (6.3.25)

This means, the attenuation of the moving average filter for the second harmonicneeds to be at least

HMA <ca0

a0

a2k= 0.056≡−25 dB. (6.3.26)

Averaging is performed by another downsampling CIC filter for minimum chiparea. ChoosingR= 256 andN = 1 yields a sampling frequency of 3.17 kHz atthe output. The -3 dB frequency of a first order CIC filter is atF ≈ 0.44, i.e. atf = 1.39 kHz.

The lowest frequency component that has to be regarded for aliasing is the secondharmonic of the lower edge of the frequency range (10 kHz). Alias suppressionat F = 6.5 ( f = 20.6 kHz) is 0.077 or 22.3 dB (6.3.7). This creates a worst caseerror of 0.35 dB, falling a bit short of the target of 0.25 dB. However, this errorquickly decreases for higher test-tone frequencies.

The averaged demodulated output value can be read via a threewire bus, videodetection and filtering etc. can be performed by software when needed.


In theory, there is no difference between theoryand practice. In practice, there is.

Yogi Berra 7Implementation and Measurement Results

The implementation of the SP-BIST concept on test chips in 130 nm CMOS tech-nology is described. Measurement results for unmodulated and modulated PLLsignals are given and a method is described to reduce the spurious lines createdby the first orderΣ∆FD.

7.1. Baseband Test-Tone Generation

The test-tone generator has been synthesized from VHDL, occupying an area ofca. 0.02 mm2.

7.1.1. Oscillation Frequency

The signal frequency is monotonous but slightly nonlinear with respect to the co-efficientsa,bi . Fig. 7.1 shows the oscillation frequency depending on coefficientb and the error caused by the approximate frequency formula (5.2.4). The exactoscillation frequency can easily be calculated on the ATE resp. controlling PCusing (5.2.1). The binary encoding of the coefficients isQU1.14 (Sec. 2.8). Thevaluea= 2−4 is fixed, possible values forb1 andb2 with the resulting frequencies

154 7. Implementation and Measurement Results

BinWord BinWord RWV Frequency

(dec.) (kHz)

Parameteraaa

010000000000 1024 2−4 n.a.

Parameterb1b1b1 (Tone 1)

000100000000 256 2−6 65

001000000000 512 2−5 91

010000000000 1024 2−4 129.3

100000000000 2048 2−3 183

Parameterb2b2b2 (Tone 2)

000000001111 15 9.16·10−4 15

000010011111 159 9.70·10−3 51

001001011111 607 3.74·10−2 100

010000001111 1039 6.34·10−2 130

011111111111 2047 1.25·10−1 183

Table 7.1.: Frequencies of programmable tones

are shown in Tab. 7.1, spanning a frequency range of 15kHz< fsig < 183 kHz fora sampling frequency offS = 26 MHz. b1 is the reference tone which can onlybe set in four coarse steps,b2 can be varied in 127 steps between 15 and 2047(the 4 LSBs are fixed to 1111). Tab. 7.6 in the appendix shows the programmingregister for the multi-tone generator.

7.1.2. Amplitude and Amplitude Variation over Frequency

The multi-tone digital oscillator described in [LR98] has been implemented ona DSP with 24 bit arithmetics and achieves a constant amplitude for all tones bypre-calculating and storing initial conditions for each tone. The minimum areaconstraint in this work mandates a simplified approach: The initial conditions forall tones are set toxa(0) = x0 andxb,1(0) = xb,2(0) = 0, allowing the simplifica-tion of (5.2.1) - (5.2.3):


7.1. Baseband Test-Tone Generation 155

0 0.02 0.04 0.06 0.08 0.1 0.12 0.140

50

100

150

200

Sig

nal f

requ

ency

f sig (

kHz)

Resonator coefficient b0 0.02 0.04 0.06 0.08 0.1 0.12 0.14

0

0.01

0.02

0.03

0.04

Rel

ativ

e ap

prox

imat

ion

erro

r (%

)

Figure 7.1.: Frequency of LDI oscillator

ωsig = fSarccos

(1− ab

2

)for 0 < ab≤ 2

φa = −arctan2sin(ωsigTs)

ab

xa =(1−ab)xa(0)

sin(ωsigTS+φa)

This simplification results in a amplitude variation ˆxa( f ) of less than 0.1% oversignal frequency, shown in Fig. 7.2. The error due to this amplitude variation ismuch less than other error sources and is removed by the calibration proceduredescribed in Sec. 7.5.6. The amplitude of both tones can be set in steps of 6 dB(Tab. 7.2).



0 0.02 0.04 0.06 0.08 0.1 0.12 0.14−0.1

−0.09

−0.08

−0.07

−0.06

−0.05

−0.04

−0.03

−0.02

−0.01

0

Rel

. Am

plitu

de E

rror

aer

r (%

)

Resonator coefficient b

Figure 7.2.: Amplitude error of LDI based oscillator

BinWord Amplitude Amplitude (dB)

000000100000000 2−6 -24 dB

000001000000000 2−5 -18 dB

000010000000000 2−4 -12 dB

000100000000000 2−3 -6 dB

Table 7.2.: (Ideal) amplitudes of programmable tones vs. initial conditionx(0)

7.2. Output Response Analysis

7.2.1. Sigma-Delta Frequency Discriminator

The sigma-delta frequency discriminator (Σ∆FD) in this work takes advantage ofthe high transit frequency of the 130 nm CMOS technology: It isdirectlyclockedwith the 4 GHz signal of the VCO for maximum simplicity. The schematic isshown in Fig. 7.3.


7.2. Output Response Analysis 157

~

~

~

Figure 7.3.: Schematic ofΣ∆FD

Multi-Modulus Divider

The multi-modulus divider is a critical part for the performance of theΣ∆FD asdivides the RF PLL signal by a ratio that changes every reference cycle with-out producing glitches or random delays, ruling out asynchronous counters ordividers. In synchronous counters,all flip-flops are clocked with the input fre-quency, which is hard to design for radio frequencies and consumes a lot ofpower.

2 / 3Fin Fout

M out M inP

2 / 3Fin Fout

M out M inP

2 / 3Fin Fout

M out M inP

2 / 3Fin Fout

M inP

P0

P1

Pn−2

Pn−1

outDIVRFin

Figure 7.4.: Multi-modulus divider made from a chain of 2/3 divider cells

Due to the high reference frequency of 26 MHz, the required division ratio onlyhas to span the range of 115. . .154 for a PLL frequency of 3. . .4 GHz. Thisis accomplished by the architecture in Fig. 7.4 [VFL+00], consisting of a chainof ÷2/3 cells (Fig. 7.5). This topology has the advantage that onlythe firstdivider has to be designed for the full frequency and that theswitching of divisionratios is self-synchronized with the divided output signal. A simple cascade of



dual-modulus divider cells would not work because a division ratio likeN = 129cannot be constructed from a product of 2’s and 3’s. The solution is addingoneextra cycle per output period if the modulus controlPi = 1. This is achieved withthe control input and output pinsMin andMout (Fig. 7.5). The modulus enableinput Min enables theP input pin, the modulus enable outputMout synchronizestheMin input and passes it on toMin of the previous divider stage. This “daisychain connection” ensures that each divider stage swallowsa maximum of onepulse per divide cycle (depending onPi), giving the targeted division ratio (7.2.1):

NMMD = 2n +Pn−1 ·2n−1 + . . .+P1 ·2+P0 (7.2.1)

D Q

Q

D−FF 1

2 / 3Fin Fout

M out M inP

1

&D−FF

DQ

Q2

inF

inM

Fout

&M

out

EN

1D

D2

Divider /2 with enable

critical path

Phase Shift

PM_in = 0 => /2 P = 0 => /2

M_in = 1 => P enabled P = 1 => /3

=>

Figure 7.5.: High-speed 2/3 divider cell with modulus enable

Fig. 7.5 shows an 2/3 divider cell with modulus enable input.High speed isachieved by shifting the P - NAND into D-FF2 (between the master and theslave stage) to shorten the critical path. Synchronizing the programming wordguarantees a fixed timing relationship between programmingword and dividedclock which allows switching the division ratio without glitches.

RF frequencies in the range of 4 GHz require special flip-flops, here, a dynamicflip-flop is used (Fig. 7.6), similar to the design presented in [YS89].


7.2. Output Response Analysis 159

2.4M

2M

2M

2M

2.2M

2.2M

1.6M

MM

2M

2M 2M 3M

1.2M

Figure 7.6.: Dynamic high-speed flip-flop

7.2.2. Spectral Analysis of Demodulated Bitstream

Downsampling

As described in Sec. 6.3.3, the first downsampling stage is a second order(N = 2) downsampling CIC filter with a decimation ratio ofR= 32 (Fig. 6.21).The DC-gain isHCIC1(0) = 322 = 1024≡ 30 dB, the word length at the in-put is WLCIC1,in = 1 (single-bitΣ∆M stream) and at the outputWLCIC1,out =N∗ log2(R)+WLCIC1,in = 11.

Band-Pass Filter

The tunable forth-order bandpass filter is based upon a resonator-in-the-looptopology, its center frequency can be tuned in the range of 0.3 . . . 400 kHz, theusable and important range for this application is limited to 200 kHz. At higherfrequencies, the scalloping loss and the bandwidth variation becomes too large(Sec. 6.3.4).

The reduced sampling rate offS,R = 812.5 kHz allows sharing of the area-intensive multiplier between blocks in the band-pass: The signal is passedthrough the resonator twice, the center frequency is slightly detuned for the sec-ond pass (staggered tuning). Both multipliers in the resonator have the same co-efficientkf (Fig. 6.29), easing multiplier sharing. The bandpass is implemented



with only one multiplier in an area of less than 0.03 mm2. An accumulator lengthof 21 bits and a tunable coefficient length of only 9 bits were sufficient to achievea SQNR of 90 dB. This and the fact that the resonance frequencyfr is set with asingle parameterkf are the main advantages of this filter.

An implementation error in the filter that was not detected during final simula-tions creates an overall transfer function (CIC-filter and bandpass) with a varia-tion of 5 dB over the frequency range. However, the option formeasuring thebaseband response that has been implemented for compensating the scallopingloss can also be used to eliminate the faulty frequency response (Sec. 7.5.6).

Envelope Detection

The envelope detector has been implemented as described in 6.3.5, averaging ofthe rectified signal is performed with a first order downsampling CIC filter witha decimation ratioR= 256. The output word is truncated to fit the result registerlengthWL= 16.

7.3. Area Estimation and Layout

Except for the multi-modulus divider (MMD), the whole SP-BIST was synthe-sized from VHDL code. The cells were placed and routed together with the otherlogic building blocks of the DUT. For this reason, only the layout of MMD canbe shown, the other cells are absorbed into the synthesized logic of the DUT.Figures for the area consumption (including routing) were taken from the reportfiles of the P & R software (Tab. 7.3).

The layout of the MMD is shown in Fig. 7.7, occupying an area ofonly 75µm x75µm = 0.0055mm2, half of which is consumed by decoupling capacitors andcould possibly be reduced.

Block Sine Gen Σ∆FD Filter Total

Area (mm2) 0.02 0.005 0.035 0.06

Table 7.3.: Silicon area of SP-BIST blocks

In comparison, the MADBIST in [TR95a, TR95b] uses an area of 3.9 mm2 in a0.8µm technology for a two-tone generator and a tunable band-pass alone (no


7.3. Area Estimation and Layout 161

downsampling, no envelope detector). This is equivalent toan area of approx.0.1 mm2 in the 130 nm technology of this work. Although MADBIST and SP-BIST cannot be compared directly (Sec. 4.3), it can be estimated that the areareduction was achieved by reduced coefficient and multiplier precision (24 bit in[TR95b]), enabled by a reduced sampling rate (multirate signal processing) andthe resulting relaxed filter requirements.

75 um

75 u

m

Divider CellsHigh−Speed50

um

Latches& Logic

Decoupling C’s

50 um

Figure 7.7.: Layout of MMD



7.4. Test Chips

Fig. 7.8 shows the circuit-under-test (CUT) together with the SP-BIST. The multi-tone sine generator digitally modulates the PLL, the RF output of theΣ∆PLL isdemodulated with theΣ∆FD.

f

TX Filter

d

dtSDM

fmod

PFDf

÷N ± m

φmod

f

t

Generator

Stimulus

−1+

yORA

−1+ySTIM

Channel Word

VCOLoop FilterReferenceFrequency

RF out

NSpectrum Analyzer

SP−BISTN.F

Pass / Fail

Spectrum

SDFD

Figure 7.8.: RF PLL under test with SP-BIST

The test-tone generator and the output response analyzer were integrated on twodifferent highly integrated RF transceiver ICs for GSM, EDGE and UMTS cel-lular standards manufactured by Infineon Technologies. As no interaction withRF paths was required, the circuits-under-test (receive and transmit PLLs) couldremain untouched. The most challenging part of the integration was merging thesynthesizable code into the complex digital state machine under the tight restric-tions of a worldwide distributed project with more than 100 members. Controland read-out of the BIST blocks are performed via the common digital interface.As details of the DUT may not be disclosed here, Fig. 7.9 only shows a blockdiagram of one of the transceiver ICs; the twoΣ∆PLLs with added SP-BISTfunctionality have been highlighted.

The first test-chip was a quad band GSM transceiver chip similar to Fig. 3.8 withan additional single-tone test-tone generator. Unfortunately, the test-tone genera-tor could not be properly tested as no spectrum analyzer withFM discriminatorcapabilities was available.


7.4. Test Chips 163

SP−BIST (RX)SP−BIST (TX)

Figure 7.9.: Block diagram of multimode RF transceiver

The second and third SP-BIST implementations were realizedon the multimodeRF transceiver shown in Fig. 7.9, containing two-tone stimulus generator and thefull spectral RF analysis block.

On the third test chip, the SNR of the filter was improved by increasing accumula-tor word length from 15 to 21 bits. A higher selectivity was achieved by a higherresonatorQ (kBW = 2−5 → 2−8) and by introducing the concept of staggeredtuning.



7.5. Measurement Results

Unless noted otherwise, all measurement plots in this section have been takenwith the on-chip spectrum analyzer, showing the PSDSy( f ) of the frequencydeviation. Center and tone frequencies were set with a PC viathe serial bus of theDUT, measurement data was read back from the chip via the samebus. All signalprocessing was performed on chip except optional averagingand calibration (seebelow), data was plotted with Matlab. For performance evaluation of the SP-BIST, the whole frequency range was swept through. Under real production testconditions, only some critical frequency points would be measured (3 ms perpoint) to reduce the test time.

7.5.1. Disturbances Caused by SP-BIST

(a) (b)

Figure 7.10.: Unmodulated PLL spectrum without (a) and with (b) activeΣ∆FD,measured with spectrum analyzer at TX output

The multi-tone generator is connected to the digitalΣ∆PLL modulation inputand is completely invisible when deactivated. The additional capacitive load thatalso the inactiveΣ∆FD presents to the VCO buffer could degrade the PLL per-formance, however, no degradation was measured in comparison to chip variantswithout SP-BIST (Fig. 7.10(a)). In active mode, spurs at multiples of the refer-ence frequency (26 MHz) appear in the output spectrum (Fig. 7.10(b)) which donot disturb the in-band measurements. If it is intended to run the SP-BIST blocksduring normalΣ∆PLL operation (e.g. for monitoring the PLL spectrum), a few


7.5. Measurement Results 165

more buffers have to be inserted between VCO buffer andΣ∆FD for additionalisolation.

7.5.2. Spectrum of Test-Tone Generator

The output of the stimulus generator can be fed directly intothe narrowband filter(see Fig. 7.8) for baseband performance verification of the tone generator and thenarrowband filter with envelope detector. Fig. 7.11 show theoverlaid results ofmeasurements with different tone frequencies, using different filter staggerings.Fig. 7.11 has been constructed from the maxima of individualmeasurements,although this gives a pessimistic view of the noise performance.

Instead of the expected droop in the frequency response due to the CIC filter,there is an unexpected increase over frequency. This effectcould be traced backto a faulty implementation of the tunable bandpass filter. AstheΣ∆FD has a con-stant frequency response over the range of interest, this error can be compensatedby a reference measurement or simulation that only has to be performed once.

The signal-to-noise ratio degrades at higher frequencies due the sigma-delta quan-tization noise of the multi-tone generator. The tunable filter has a dynamic rangeof approx. 90 dB as can be seen for frequencies below 50 kHz. This is consistentwith simulation results.

7.5.3. Measurement Accuracy

The reproducibility of SP-BIST measurements has been analyzed by repeatinga measurement 200 times and calculating the averagem and the standard devia-tion σ at the output of the envelope detector. The tone frequency was fixed atfm = 65 kHz for all measurements. The filter center frequencyfc was first set tothe tone frequency (fc = fm = 65 kHz) to assess the reproducibility of tone mea-surements and then at an unrelated frequencyfc = 104 kHz to assess the noiselevel (Tab. 7.4). The noise bandwidth isBn ≈ 900Hz≡ 29.5 dB.

First, the reproducibility of baseband measurements (i.e.without Σ∆PLL andΣ∆FD) was assessed. For this mode, noise can be attributed to the Σ∆M of thetone generator and to re-quantization in the filter. The quantity mS/mN is anindication for the SNR, although it should be noted that signal and noise havebeen measured at different frequencies. Unfortunately, there was not enoughtime for more in-depth measurements due to a job change.



0 0.5 1 1.5 2 2.5 3

x 105

0

10

20

30

40

50

60

70

80

90

Am

plitu

de(d

B)


(a) ∆kf = 0

0 0.5 1 1.5 2 2.5 3

x 105

0

10

20

30

40

50

60

70

80

90

Am

plitu

de(d

B)


(b) ∆kf = 2·2−9

Figure 7.11.: Spectrum of two-tone generator measured with different filter staggering



∆kf∆kf∆kf fc = fmfc = fmfc = fm fc = 104fc = 104fc = 104kHz mS/mNmS/mNmS/mN

·2−9·2−9·2−9 mSmSmS σSσSσS σS/mSσS/mSσS/mS mNmNmN σNσNσN σN/mNσN/mNσN/mN [dB]

Baseband 0 13250 42 0.3% 20 7 35% 56.4

1 9408 50 0.5% 10 6 60% 59.4

2 6428 19 0.3% 8 5 60% 58.1

3 4057 25 0.6% 5 4 80% 58.1

Full 0 27911 102 0.4% 95 49 52% 49

SP-BIST 1 19880 120 0.6% 82 45 55% 48

2 13548 54 0.4% 63 35 56% 47

3 8538 62 0.7% 46 26 56% 45

Table 7.4.: Reproducibility of SP-BIST tone (fc = 65 kHz) and noise (fc = 104 kHz)measurements for a tone frequencyfm = 65 kHz

In the second step, the full loop including upconversion in the Σ∆PLL and fre-quency discrimination in theΣ∆FD was measured. The SNR degradation of≈ 11 dB compared to baseband measurements is mainly caused by the Σ∆FDquantization noise and spurs. The RF response has been optimized to make fulluse of the dynamic range of the SP-BIST. The baseband response is lower by6.5 dB which can be compensated easily on the ATE or a lab PC. Hence, no on-chip gain equalization between theΣ∆M bitstreams of test-tone generator andΣ∆FD has been implemented.

The results show excellent reproducibility of the tone measurements (0.5%≡0.04 dB).

7.5.4. Measurement of Unmodulated Spectrum

Next, an unmodulated PLL signal was fed into theΣ∆FD. Strong spurious tones,produced by the first orderΣ∆FD can be seen in the demodulated spectrum(Fig. 7.12(a) and 7.12(b)). The position of these idle tonesis determined bythe fractional part of the PLL frequency as explained in Sec.6.2.2. The nearestinteger frequency isfI = 146·26 MHz= 3822 MHz, the fractional partf f rac =3812.348 MHz− fI = −9.652 MHz≈ 0.371·26 MHz.

Averaging improves the SNR butΣ∆FD tones are not attenuated. Averaging the



0 0.5 1 1.5 2 2.5 3 3.5 4

x 105

0

10

20

30

40

50

60

70

80

20 lo

g |S

|


y

f = 3812.3487 MHzVCO

(a)

0 0.5 1 1.5 2 2.5 3 3.5 4

x 105

0

10

20

30

40

50

60

70

80

20 lo

g |S

|


y

f = 3812.3387 MHzVCO

(b)

Figure 7.12.: Unmodulated PLL spectrum withΣ∆FD spurious tones at different carrierfrequencies (∆ f0 = 10 kHz)



spectrum atK several slightly different carrier frequencies reduces the magnitudeof the Σ∆FD spurs by 20logK dB as theΣ∆FD spurs now appear at differentoffsets. Thisfrequency sweep averagingis feasible as the fractional-N PLL takesonly a fewµs to lock to the new frequency.

As the spurious tones are deterministic, these frequenciescan be "blanked" out.By selecting only data points that differ less than e.g. 8 dB between measure-ments, different scale of y-axis), the SFDR can be improved by approximately30 dB [MW07]. However, thisselective frequency averaginghas to be appliedwith care as some kinds of unwanted PLL sidebands also dependon the carrierfrequency and may be suppressed as well. The effect of both methods can beseen in Fig. 7.13 for the case of a single-tone modulation.

7.5.5. Measurement of Modulated Spectrum

Fig. 5.11 shows the PLLphasespectrum resulting from single-tone modulationwith fre f = 26 MHz, fm = 67 kHz at a carrier frequencyf0 = 3.812 GHz. The

frequency modulation index isβ f = 2.1 and the peak frequency deviation is∆ f =142 kHz.

This single-tone modulation is used to calibrate the gain ofthe spectral analyzer:An RF PSD ofSy = 3.72·10−5 ≡−85.6 dB is calculated, the displayed value is83 dB, indicating a gain of 168 dB. The displayed noise level is around +32 dBwith a noise bandwidthBN = 27 dB, yielding a noise PSD ofSy( fm = 67kHz) =32−27−168 dB = -163 dB. This corresponds toSφ = Sy +20log fm = −163+97= −66 dB. At around 200 kHz, the noise has a constant value of 40 dB.

The quantization error of a single tone modulation is still strongly correlatedwith the signal, leading to strong spurious tones as well (Fig. 7.13(a)). Applyingselective frequency averaging improves the result (Fig. 7.13(b)) with the samedrawbacks as described above.

Two-tone FM produces sufficient randomization to eliminatemost idle tones asshown in Fig. 7.14. Again, frequency selective averaging improves the displayof measurement results (Fig. 7.14). This figure shows a two-tone spectrum mea-sured on-chip with too weak attenuation of the out-of-band tone, indicating afaulty loop transfer characteristic. With two-tone modulation, the spurious freedynamic range (SFDR) is approx. 45 dB.



0 0.5 1 1.5 2 2.5 3 3.5 4

x 105

0

10

20

30

40

50

60

70

80

90

20 lo

g |S

|

y


VCOf = 3812.3387 MHz

(a)

0 0.5 1 1.5 2 2.5 3 3.5 4

x 105

0

10

20

30

40

50

60

70

80

90

20 lo

g |S

|

y


VCOf = 3812.3387 MHz

(b)

Figure 7.13.: Single-tone (67 kHz) modulated PLL spectrum with averaging (a) andselective frequency averaging (b)(K = 4, ∆ f = 10 kHz)



0 0.5 1 1.5 2 2.5 3 3.5 4

x 105

0

10

20

30

40

50

60

70

80

90

20 lo

g |S

|


Loop Characteristic

Error

VCOf = 3812.338 MHz

f

Target

Figure 7.14.: Two-tone modulated PLL spectrum with frequency sweepaveraging,showing error in loop characteristic

∆HORA( fm) = Sy,ORA,RF( fm)−Sy,ORA,RF(64kHz)

∆HPLL( fm) = Sy,ORA,RF( fm)−Sy,BB,RF( fm)−6.5dB

Sy( fm) = Sy,ORA,RF( fm)−A0−∆HORA( fm)

Sφ ( fm) = Sy( fm)+20log f0/ fm

Sy,N( fm) = Sy,ORA,RF( fm)−A0−∆HORA( fm)−BN( fm)

Sφ ,N( fm) = Sy,N( fm)+20log f0/ fm

L ( fm) = Sφ ,N( fm)−3dB

Box 7.1: Formulas for calculation of frequency response and phasenoise



0 0.5 1 1.5 2 2.5 3

x 105

0

10

20

30

40

50

60

70

80

90

Am

plitu

de(d

B)


(a) BB-ORA

0 0.5 1 1.5 2 2.5 3

x 105

0

10

20

30

40

50

60

70

80

90

Am

plitu

de(d

B)


(b) RF-ORA

Figure 7.15.: Comparison of baseband and RF output response analysis



kf ·29kf ·29kf ·29 251 285 397 476 545 600 647

fmfmfm (kHz) 64 73 103 125 145 162 177

f0/ fmf0/ fmf0/ fm (dB) 95.5 94.4 91.4 89.7 88.4 87.4 86.7

A0A0A0 (dB) 161.5 (BB) resp. 168 (RF)

∆HCIC( fm)∆HCIC( fm)∆HCIC( fm) (dB) 0 −0.2 −1.2 −2.1 −3.1 −4.1 −5.1

∆HBP( fm)∆HBP( fm)∆HBP( fm) (dB) 0 +1.2 +4.3 +5.8 +7.8 +8.6 +10.4

∆HORA( fm)∆HORA( fm)∆HORA( fm) (dB) 0 +1.0 +3.1 +3.7 +4.7 +4.5 +5.3

Hy,ORA,BBHy,ORA,BBHy,ORA,BB (dB) 76.2 77.2 79.3 79.9 80.9 80.7 81.5

Tones

Hy,ORA,RFHy,ORA,RFHy,ORA,RF (dB) 82.6 83.3 83.0 81.6 79.8 77.4 75.4

∆HPLL( fm)∆HPLL( fm)∆HPLL( fm) (dB) −0.1 −0.4 −2.8 −4.8 −7.6 −9.8 −12.6

Sy( fm)Sy( fm)Sy( fm) (dB) −85.4 −85.7 −88.1 −90.1 −92.9 −95.1 −99.2

Sφ ( fm)Sφ ( fm)Sφ ( fm) (dB) +10.1 +8.7 +3.3 −0.4 −4.5 −7.7 −12.5

Noise

Sy,ORA,RFSy,ORA,RFSy,ORA,RF (dB) 25 28 32 35 36 37 38

BNBNBN (dB) 29 29 29 29 30 30 30

Sy,N( fm)Sy,N( fm)Sy,N( fm) (dB) −172 −170 −168 −166 −167 −166 −165

Sφ ,N( fm)Sφ ,N( fm)Sφ ,N( fm) (dB) −77 −76 −77 −76 −78 −78 −79

L ( fm)L ( fm)L ( fm) (dB) −80 −79 −80 −79 −81 −81 −82

Table 7.5.: Output frequency response measurements (∆kf = 2−8) at f0 = 3.812 GHz



7.5.6. Measurement of Frequency Response with Calibration

Due to the implementation fault of the bandpass filter and itsscalloping lossthat creates a ripple of 0.5 dB, a calibration run is requiredto obtain precise RFmeasurements. Other systematic error sources like the droop of the test-toneamplitude (< 0.2%≡ 0.02 dB) are eliminated by this procedure as well. For thiscalibration, a test mode is selected where the output of the test-tone generator isconnected directly to the output response analyzer (Fig. 7.8). The measured baseband test tone amplitudesHy,ORA,BB are stored and subtracted from the measuredRF amplitudesHy,ORA,RF at the same frequencies later on.

Fig. 7.15 shows the spectra of baseband and RF measurements,Tab. 7.5 the mea-surement results before and after calibration and Box 7.1 the equations that havebeen used to calculate the numbers.

Measurements atfm = 64 kHz have been taken as the reference values in Tab. 7.5,A0 = A( fm = 64kHz). For PLL frequency response measurements, the nominalvalueHy,ORA,RF−Hy,ORA,BB = 6.5 dB has been used as the reference value wherethe 6.5 dB are the gain difference between baseband and RF response analysis(Sec. 7.5.3).

7.6. Programming Examples

A few practical production measurement scenarios are presented in the following:

Frequency response measurement

The general procedure for a frequency response measurementis:

(1) Turn on PLL-under-test and enable test-tone modulation. Turn on refer-ence clock for SP-BIST and the VCO buffer providing theΣ∆FD with theRF input signal. These registers are outside the SP-BIST andnot describedhere.

(2) Turn onΣ∆FD and select RF (Σ∆PLL) or baseband (test-tone generator)input withFrequency Discriminator Register.

(3) Select carrier frequency ofΣ∆PLL. This register is also outside the SP-BIST.


7.6. Programming Examples 175

(4) Select frequencies and amplitudes for the two test-tones and enable test-tone generation withMulti-Tone Stimulus Register.

(5) Select center frequency and staggering of bandpass filter with Band-PassFilter Register.

(6) Wait for 3 ms.

(7) Read outResult Register.

(8) Repeat steps 4 - 7 for every frequency point.

On the ATE, the coefficients for the test-tones and the centerfrequencies have tobe calculated (or read from a look-up table). The result wordcan be averaged toimprove the SNR, if desired also at different carrier frequencies of theΣ∆PLL(selective frequency averaging) (step 3). Finally, the error introduced by thefrequency response of the SP-BIST has to be compensated by subtracting thebaseband response (Sec. 7.5.6). The baseband response is fully deterministicand can be either pre-computed or measured once and then be stored in a table.

Measurement of phase noise, spurious sidebands or modulation mas k

(1) Turn on PLL-under-test and disable all modulation sources or select mod-ulation with Gaussian filtered PRBS source to measure modulation mask.Turn on reference clock for SP-BIST and the VCO buffer providing theΣ∆FD with the RF input signal. These registers are outside the SP-BISTand not described here.

(2) Turn onΣ∆FD and select RF (Σ∆PLL) input withFrequency Discrimina-tor Register.

(3) Select carrier frequency ofΣ∆PLL. This register is also outside the SP-BIST.

(4) Disable test-tone generation withMulti-Tone Stimulus Register.

(5) Select center frequency and staggering of bandpass filter with Band-PassFilter Register.

(6) Wait for 3 ms.

(7) Read outResult Register.

(8) Repeat steps 4 - 7 for every frequency point.



In addition to the ATE procedures described in the last section, the compensatedoutput value also has to be translated from frequency deviation to phase noiseusing the resolution frequency and the ratio of modulation frequency and carrierfrequency.

7.6.1. Programming Registers

Tab. 7.6 shows the SP-BIST parameters that can be controlledvia the commonserial control and data bus of the DUT:

The Multi-Tone Stimulus Register enables the test tones and controls theiramplitudes and frequencies. Alternatively, the stimulus generator can deliver apseudo-random binary sequence (PRBS). The settings of the band-pass are con-trolled by theBand-Pass Filter Register: f c0 . . . f c9 set the center frequency ofthe band-pass withkf = fc/29 andd f0 andd f1 set the bandwidth via the amountof staggering between the two band-pass sections. Most bitsof theFrequencyDiscriminator Register have been implemented for debugging and performanceoptimization purposes. However, no significant performance improvements oftheΣ∆FD could be measured, as the drawbacks of the first orderΣ∆M structurecreates the main disturbances. The averaged magnitude of the band-pass outputis read back from theResult Registervia the same bus.


7.6.P

rogramm

ingE

xamples

177

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

Multi-Tone Stimulus Register (WRITE)

PRBS Amplitudes Frequency Tone 2 F. Tone 1 Enable

prbs m21 m20 m21 m20 b26 b25 b24 b23 b22 b21 b20 b11 b10 en1 en0

Band-Pass Filter Register (WRITE)

Order Notch Bandwidth Center Frequency

ord ntch n.c. d f1 d f0 n.c. f c9 f c8 f c7 f c6 f c5 f c4 f c3 f c2 f c1 f c0

Frequency Discriminator Register (WRITE)

Man Channel Demodulator Mode Dither EN

man ch5 ch4 ch3 ch2 ch1 ch0 sel1 sel0 ddis dinv dsgn di2 di1 di0 en

Result Register (READ)

r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0

Table 7.6.: Programming registers

Spe

ctralP

LL

Built-In

Se

lf-Testfo

rIn

tegra

ted

Ce

llula

rTra

nsm

itters

The best way to predict the future is to invent it.

Alan Kay 8Conclusion and Future Work

8.1. Comparison to Goals

A Spectral BIST conceptcapable of extracting spectral parameters of RF PLLshas been developed that allows aautonomous block level test. The SP-BIST isstarted and controlled via three 16 bit write-registers (Tab. 7.6 in Sec. 7.6.1), theresult, i.e. the amplitude of the selected frequency band, is read back from theforth 16 bit register. This procedure requiresno external measurement equip-ment and no high-speed ATE support; it can be run in parallel to other tests aslong as the normal functionality of theΣ∆PLLs is not needed. Thetest resultsin the frequency domaincan be directly compared to the PLL specifications.

The SP-BIST consists of two distinct digital blocks, a stimulus generator andan output response analyzer and compactor.Multi-tone stimuli for efficientanalysis of the PLL frequency response and loop bandwidth are generated with alow-passΣ∆-modulated oscillator. This aspect was adopted from the MADBISTmixed-signal test concept for ADCs and DACs (Sec. 4.3). In contrast to thelatter, test tones are applied directly to the digital frequency modulation input oftheΣ∆PLL, avoiding intermediate D-to-A conversion.

RF demodulation and digitization is performed with a fully digital Sigma-Delta frequency discriminator (Σ∆FD) and decimated in a multi-rate filter. The

180 8. Conclusion and Future Work

actual filtering is again similar to the MADBIST concept, however, in this work,the simple second order resonator has been replaced by a forth order band-passwith staggered tuning that combines a high selectivity witha small scallopingloss. The latter translates to reduced sensitivity againstdetuning of tone and cen-ter frequency, allowing a relatively coarse tuning of stimulus generator and band-pass filter with reduced coefficient word length. An additional envelope detectorallows the static readout of the filter output via aminimal test interface. Thisenables simple testing of RF PLLs also on wafer level, increasing fault coveragefor known-good-dies.

PLL bandwidth is directly influenced by loop filter components and indirectly bythe open loop gain, which in turn is influenced by many analog parameters. It isan essential PLL parameter, influencing spurs, phase noise and modulation per-formance. Testing bandwidth, in-band phase noise and spurious level at selectedfrequencies can eliminate most ATE tests.

The reduction in coefficient length can be exploited for an overall size reductionas both stimulus generator and band-pass filter are based upon digital losslessresonators, a topology that has nearly fallen into oblivion but is optimally suitedfor this application: It is robust against coefficient truncation and quantizationeffects, giving very compact implementations, and the center resp. oscillationfrequency is tuned with a single coefficient. Minimum area was also achievedby multi-rate signal processing andoptimized test partitioning: Peak filter gaindepends somewhat on the frequency and there is a slight non-linearity in the fre-quency vs. the control word. Correction involves some trigonometric functionsand / or calibration which are easily calculated on a PC or ATEbut not in hard-ware.

A very efficient simulation and modeling strategyfor RF circuits with largedigital content had to be developed to simulate the interaction of the completeΣ∆PLL and SP-BIST including settling and phase noise performance with a stan-dard VHDL simulator. One key point missing in prior works wasthe precise mod-eling of the combination of phase detector / charge pump and sampled loop filtermodel without beat frequency effects: Compensating the timing error due to thesampled filter model by scaling the amplitude of the filter input allowed correctsimulation of e.g. theΣ∆FD performance and loop filter reference feedthrough at-106 dBc without slowing down the simulator.

Synthesizable Design:All blocks of the SP-BIST except for theΣ∆FD havebeen described in VHDL, synthesized from library cells and placed and routedusing the standard design flow. As a consequence, the BIST blocks merge seam-lessly with the other logic cells of the SOC, minimizing the design effort andmaximizing the portability to different processes. TheΣ∆FD is a fully digital


8.1. Comparison to Goals 181

block as well, but it has to be designed and laid out carefullyby hand as it oper-ates at the full RF speed of 4 GHz. This is especially true for the multi-modulusdivider (MMD) as the core component of theΣ∆FD however, the additionaldesign effort is minimal, as the MMD can be copied from theΣ∆PLL withoutchanges.

Performance: A phase noise floor of the SP-BIST of -80 dBc/Hz and a SFDR ofapproximately 45 dB have been achieved, mainly limited by the spurious tonesof the first orderΣ∆FD which have been underestimated in the beginning. Fre-quency response measurements can be performed with an accuracy of±0.05 dB.This is achieved by calibrating the measurements against the baseband response(Sec. 7.5.6), eliminating the ripple of the band-pass filterof ±0.5 dB and othersystematic error sources.

Area and Test Time Reduction:The additional silicon area for the SP-BIST isless than0.06 mm222, requiring a test time reduction of 100 . . . 250 ms for break-even. Although current test strategies for embedded PLLs only allow indirectmeasurement of PLL bandwidth and cannot be compared directly to the SP-BIST,a test-time reduction in the range of 100 . . . 150 ms can be estimated, compen-sating the additional area. The improved test coverage for RF tests performeddirectly on the wafer also adds to the return-on-invest.

Summary

The goal of implementing an autonomous robust Spectral PLL BIST with mini-mum area has been achieved for performing frequency response measurementsin the RF domain with high precision. This test covers many parametric faultsthat influence the bandwidth like loop filter time constants,gain of VCO, phasedetector and charge pump.

However, it was seen that spurious sidebands of the first order Σ∆FD degrademeasurements too much for a full verification of PLL sidebands, in-band noiseand modulation mask against cellular standards specifications. This limits thepractical use of the current implementation to PLL bandwidth measurements andsome functional tests. Still, the presented concept is another step towards RFSOCs that are fully testable on digital testers. Its practical usability could beimproved tremendously by a few minor changes described in the next section.


182 8. Conclusion and Future Work

8.2. Future Work

Replacing theΣ∆FD with a second orderΣ∆FD should give enough performanceboost for full autonomous verification of in-band PLL phase noise and modula-tion mask, saving several 100 ms test time per PLL. This requires the design ofan analog charge pump and comparator which have to be optimized carefully toachieve a robust yet compact design.

While the performance of the other blocks is sufficient for thefirst orderΣ∆FDthe band-pass filter should be designed with somewhat longercoefficients to al-low more precise tuning of the center frequency. The order ofthe first downsam-pling CIC filter should be increased, its decimation ratio decreased for a wideroperating frequency range and less aliasing. These improvements can be imple-mented at the cost of a very moderate area increase.

Speed-up of the test itself could be achieved by simultaneous multi-tone anal-ysis using several resonators in parallel at the cost of additional chip area[PM91]. The BIST approach could be easily extended to aSpectral Built-InSelf-Calibration(SP-BISC) by e.g. tuning the loop filter or the VCO bias pointfor optimum power consumption and phase noise performance.

If necessary, silicon area of the SP-BIST could be further reduced by perform-ing stimulus generation and / or spectral analysis off-chipe.g. in an FPGA ina combined BIST/BOST approach. However, this would mean sacrificing theconcept of a fully autonomous BIST which means a higher development for testprogram and DUT test board; self-test and self-calibrationof the finished appli-cation would no longer be possible.

Test support for the measurement of out-of-band PLL noise would be a major steptowards fully digital test of RF SOCs: For GSM applications,spurious emissionsat offsets above 20 MHz have to be below -129 dBc/Hz for the TX band and evenbelow -165 dBc(Hz) for the RX band (Fig. 3.9). Guaranteeing these numbersin production test currently requires expensive RF ATE and long measurementtimes, achieving this performance with DfT / BIST circuitrywill be a anotherchallenging research task.

For technology nodes below 130 nm, the majority of PLLs will be all-digital, i.e.the VCO is replaced by a digitally controlled oscillator andthe phase detectorby a time-to-digital converter (TDC). These architecturesoffer new fully digitalself-test opportunities by processing the digital output of the TDC, enabling band-width and in-band noise measurements in conjunction with the digital test-tonegenerator and the multi-rate tunable narrowband filter described in this work.


For every complex problem, there is a solutionthat is simple, neat, and wrong.

H. L. Mencken AVHDL Behavioral Models

A.1. Loop Filter

R3

R1

R2

C2 C3C1

to VCO

I

CP

CP

Loop Filter

Figure A.1.: Non-Integrating loop filter with charge pump

The CTs-domain transfer function of the third order non-integrating loop filterin Fig. A.1) is given by (A.1.1):

184 A. VHDL Behavioral Models

H(s) =1

k′33s3 +k′32s

2 +k′31s+1with k′33 = R1R2R3C1C2C3, (A.1.1)

k′32 = C1C2R1R2 +C1C3R1R2 +C1C3R1R3 +C2C3R1R3 +C2C3R2R3

and k′31 = R1C2 +R2C2 +R1C3 +R2C3 +R3C3 +R1C1

It is translated to thez-domain using bilinear transform (A.1.2):

H(z) = K3b33z−2 +b32z−2 +b31z−1 +1a33z−3 +a32z−2 +a31z−1 +1

(A.1.2)

with K3 =1

k33+k32+k31+1,

k33 = k′33

(2TS

)3

, k32 = k′32

(2TS

)2

, k31 = k′312TS

a33 = K3 (−k33+k32−k31+1) , a32 = 3K3 (k33−k32−k31+3) ,

a31 = K3 (−3k33−k32+k31+3) and b33 = 1, b32 = b31 = 3

The sensitivity of the resulting direct form filter to coefficient truncation andquantization errors is not a problem as the VHDL model utilizes floating pointarithmetics. The following listing shows the basic implementation of the DT loopfilter model (A.1.2) in VHDL:

cons tan t TS : r e a l := r e a l ( TS_2 / f s )∗ 5 .0 e−16;−− 1 /2 sampl ing i n t e r v a l

cons tan t TSS : r e a l := TS∗ TS ; −− TS ∗∗ 2cons tan t TSSS : r e a l := TS∗ TS ∗ TS ; −− TS ∗∗ 3−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− t h i r d o rde r f i l t e r c o n s t a n t s−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−cons tan t k33 : r e a l := C1 ∗ C2 ∗ C3 ∗ R1 ∗ R2 ∗ R3 / TSSS ;cons tan t k32 : r e a l := ( C1∗C2∗R1∗R2+C1∗C3∗R1∗R2+C1∗C3∗R1∗R3

+ C2∗C3∗R1∗R3 + C2∗C3∗R2∗R3 ) / TSS ;cons tan t k31 : r e a l := ( R1∗C2+R2∗C2+R1∗C3+R2∗C3+R3∗C3+R1∗C1 )

/ TS ;cons tan t K3 : r e a l := 1 .0 / ( k33 + k32 + k31 + 1 . 0 ) ;

cons tan t a33 : r e a l := ( −k33 + k32 − k31 + 1 . 0 ) ∗ K3 ;cons tan t a32 : r e a l := ( 3 .0 ∗ k33 − k32 − k31 + 3 . 0 ) ∗ K3 ;cons tan t a31 : r e a l := (−3.0 ∗ k33 − k32 + k31 + 3 . 0 ) ∗ K3 ;

cons tan t b33 : r e a l := 1 . 0 ;


A.1. Loop Filter 185

cons tan t b32 : r e a l := 3 . 0 ;cons tan t b31 : r e a l := 3 . 0 ;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

LF : process( s _ c l k )begin

i f s_c lk ’ ev en t then

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Th i rd Order F i l t e r−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

mem3 <= mem2 ;mem2 <= mem1 ;mem1 <= CPval ∗ K3 − a31 ∗ mem1− a32 ∗ mem2− a33 ∗ mem3 ;v tune <= CPval ∗ K3 − a31 ∗ mem1− a32 ∗ mem2− a33 ∗ mem3

+ b31 ∗ mem1 + b32 ∗ mem2 + b33 ∗ mem3 ;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

end i f ; −− e v e n tend process LF ;

The filter calculation is performed in the processLF each time the filter clocksignals_clk changes (s_clk’event ), i.e. twice per clock period. This clockis defined in another autonomous process (not shown here) with an arbitrary fre-quency that should be 10x ... 20x higher than the maximum input frequency toachieve a reasonable accuracy of the filter characteristic without slowing downsimulation too much.

CPval is the state of the filter input, delivered by the charge-pump(currentmultiplied with the input resistor of the filter), it is calculated in yet anotherprocess (also not shown).mem1etc. correspond to the registers (z−1 in the blockdiagrams).

The beat frequency effect between the phase detector switching and the filterclock is eliminated by the method described in section 4.5.2in processLF_frwhere the timing error between the last switching event of the phase detector /charge pump and the next sampling clock event is translated into a fractional filterinput, i.e. the limited timing resolution of the sampled filter is exchanged for itsnearly analog amplitude resolution. In processLF_fr , the time between the lastswitching of the phase detector / charge pump and the next sampling clock eventis tracked and related to the sampling period (“fractional”period). The inputvalue for the current filter cycle is then scaled with this value.

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− Loop f i l t e r model w i t h c o r r e c t i o n o f samp l ing e r r o r−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−LF_fr : process( s_c lk , CP_i )

v a r i a b l e TS_f rac_v : r e a l ; −− f r a c t i o n a l t ime s t e p :



−− e v e n t d e l t a t ime−− r e l . t o samp l ing p e r i o d

v a r i a b l e T _ l a s t _ v : t ime ; −− t ime o f l a s t c a l c u l a t i o nv a r i a b l e f r a c f l a g : boo lean ;−− f r a c t i o n a l c y c l e ?v a r i a b l e f r a c f l a g _ d : boo lean ;−− prev . f r a c t i o n a l c y c l e ?

begini f s_c lk ’ ev en t or CP_i ’ ev en t then

i f ( now − T _ l a s t _ v < TS_2t ) then−− " f r a c t i o n a l " c y c l e : t ime s i n c e l a s t e v e n t−− i s l e s s than TS :Ts_ f rac_v := r e a l ( ( now− T _ l a s t _ v ) / f s ) / r e a l ( ( TS_2t ) / f s ) ;f r a c f l a g := t r u e ;

i f CP_i = ’0 ’ then −− CP j u s t s w i t c h e d o f fCPval <= Ts_ f rac_v ∗ CP_DC_c ;

e l s e −− CP j u s t s w i t c h e d onCPval <= ( 1 . 0 − Ts_ f rac_v ) ∗ CP_DC_c ;

end i f ; −− CP_ie l s e−− normal c y c l e

i f CP_i = ’1 ’ thenCPval <= CP_DC_c ;

e l s eCPval <= 0 . 0 ;

end i f ; −− CP_if r a c f l a g _ d := f r a c f l a g ; −− s t o r e l a s t f r a c f l a gf r a c f l a g := f a l s e ; −− r e s e t f r a c f l a g

end i f ; −− t i m e s t e p

i f not f r a c f l a g _ d then

T _ l a s t _ v := NOW;−− don ’ t s t o r e t i m e s t e p i f t h e l a s t one was a f r a c t i o n a l−− one − o t h e r w i s e t h i s c y c l e would be c a l c u l a t e d t w i c e

. . .

end i f ; −− i f no t f r a c f l a gend i f ; −− e v e n t

end process LF_fr ;

A.2. Voltage Controlled Oscillator

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− B e h a v i o r a l VCO model ( e x c e r p t )−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

. . .begin −− p r o c e s s FREQ_GEN

vco_out <= ’0 ’ ;p e r i o d _ t <= 300 ps ;p e r i o d _ e r r _ v := 0 . 0 ;


A.3. Random Number Generator 187

VCOLoop : loop

vco_out <= t r anspo r t ’1 ’ a f t e r VCODelay ,’0 ’ a f t e r p e r i o d _ t / 2 + VCODelay ;

wai t f o r p e r i o d _ t ;

p e r i o d _ v := 1 .0 / ( ( f_0 + kvco∗ v t u n e _ i ) ∗ 1 .0 e−15)+ p e r i o d _ e r r _ v ;

p e r i o d _ t <= ( p e r i o d _ v ) ∗ f s ; −− p e r i o d i n f s

−− c a l c u l a t e t r u n c a t i o n e r r o r :p e r i o d _ e r r _ v := p e r i o d _ v− r e a l ( ( p e r i o d _ v ∗ f s ) / f s ) ;−− c a l c u l a t e d e v i a t i o n from t a r g e t f r e q u e n c y :

d e l t a _ f <= 1 .0 e15 / p e r i o d _ i d _ v − f _ t a r g ;

end loop VCOLoop ;end process FREQ_GEN;

vco_o <= vco_out ;

A.3. Random Number Generator

A random number source with Gaussian distribution is neededto model randomprocesses in VHDL. A simple modulus arithmetic algorithm [Jai91, p. 443],suitable for 32 bit integer arithmetic, produces a uniformly distributed pseudo-random sequence with a length of 231−2:

x[n] = 75 ·x[n−1] mod(231−1) (A.3.1)

Two uncorrelated uniform processesx1(n),x2(n) are transformed into two uncor-related Gaussian processesxn,1[n],xn,2[n] using the approach described in [PM92,p. 944]. First, one of the processes is transformed into a random processxR,1(n)with Rayleigh distribution:

xR,1[n] =

√2log

11−x1[n]

(A.3.2)

FromxR,1[n] andx2[n], two processes with Gaussian (normal) distribution (m= 0,σ = 1) can be derived:

xn,1[n] = xR,1[n]cos(2πx2[n]) (A.3.3)

xn,2[n] = xR,1[n]sin(2πx2[n]) (A.3.4)



The average value and standard deviation ofxn,1[n],xn,2[n] are easily adapted byadding an offsetm resp. scaling with a factorσ .


Bibliography

[ABM +09] A. Asquini, A. Bounceur, S. Mir, F. Badets, J.-L. Carbonero, andL. Bouzaida,DfT technique for RF PLLs using built-in monitors,Int’l. Conf. on Design & Technology of Integrated Systems inNanoscale Era (DTIS), 2009, pp. 210–215.

[AC04] S. Akbay and A. Chatterjee,Feature extraction based built-in al-ternate test of RF components using a noise reference, Proc. IEEEVLSI Test Symp. (VTS), 2004, pp. 273–278.

[Agi06] Agilent, Spectrum analysis basics, Application Note 150, Aug.2006, Application Note 150.

[AK97] K. Arabi and B. Kaminska,Testing analog and mixed-signalintegrated circuits using oscillation-test method, IEEE Trans.Computer-Aided Design of Integrated Circuits and Systems16(1997), no. 7, 745–753.

[AS07] S. Abdennadher and S. Shaikh,Practices in mixed-signal and RFIC testing, IEEE Des. Test. Comput.24 (2007), no. 4, 332–339.

[Bax99] W. Bax,Modulation and frequency synthesis for wireless digitalradio, Ph.D. thesis, Ottawa-Carleton Institute of Electrical Engi-neering, Department of Electronics, Carleton University,Ottawa,Canada, Oct. 1999.

[BC94] R. Beards and M. Copeland,An oversampling Delta-Sigma fre-quency discriminator, IEEE Trans. Circuits Syst. II41 (1994),no. 1, 26–32.

[BCR96] W. Bax, M. Copeland, and T. Riley,A single-loop second-order∆Σ frequency discriminator, IEEE-CAS Region 8 Workshop onAnalog and Mixed IC Design, 1996, pp. 26–31.

[BCW05] I. Bayraktaroglu, O. Caty, and Y. Wong,Highly configurable pro-grammable built-in self test architecture for high-speed memories,Proc. IEEE VLSI Test Symp. (VTS), 2005, pp. 21–26.

189

190 Bibliography

[Ber05] L. Berlin, The man behind the microchip: Robert noyce and theinvention of silicon valley, Oxford University Press, 2005.

[Bes98] R. Best,Theorie und Anwendungen des Phase-Locked Loop, ATVerlag, Aarau / Stuttgart, 1998.

[BHH+06] P.-H. Bonnaud, M. Hammes, A. Hanke, J. Kissing, R. Koch,E. Labarre, and C. Schwoerer,A fully integrated SoC for GSM/G-PRS in 0.13µm CMOS, IEEE Int’l. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, 2006.

[BLBR04] M. Burbidge, A. Lechner, G. Bell, and A. Richardson, Motivationstowards BIST and DfT for embedded charge-pump phase-lockedloop frequency synthesisers, IEE Proc.-Circuits Devices Syst.,151(2004), no. 4, 337–348.

[BS81] Bronstein and Semendjajew,Taschenbuch der Mathematik, 21sted., Verlag Harri Deutsch, Thun, 1981.

[Can86] J. C. Candy,Decimation for sigma delta modulation, IEEE Trans.Commun.34 (1986), no. 1, 72–76.

[CB81] J. C. Candy and O. J. Benjamin,The structure of quantiza-tion noise from Sigma-Delta modulation, IEEE Trans. Commun.COM-29 (1981), no. 1, 1316–1323.

[Cha03] M. Chandramouli,How to implement deterministic logic built-inself test (BIST), Compiler, Synopsys Online Magazine2 (2003),no. 1.

[CKHS04] T. Cho, D. Kang, C.-H. Heng, and B. S. Song,A 2.4-GHz dual-mode 0.18-µm CMOS transceiver for Bluetooth and 802.11b,IEEE J. Solid-State Circuits39 (2004), no. 11, 1916–1926.

[CKTM02] P. Callahan, E. Kimball, V. Telang, and M. Milisavljevic, How sys-tems level considerations impact cost effective Gigabit EthernetPHYs, Tech. report, EETimes, July 2002.

[CLM+07] M. Cimino, H. Lapuyade, M. D. Matos, T. Taris, Y. Deval, and J.-B. Bégueret,A sub 1V CMOS LNA dedicated to 802.11b/g appli-cations with self-test & high reliability capabilities., IEEE RadioFrequency Integrated Circuits (RFIC) Symp. Dig. of Papers,2007,pp. 343–346.

[CMJ+03] B. Casper, A. Martin, J. Jaussi, J. Kennedy, and R. Mooney, An


Bibliography 191

8-Gb/s simultaneous bidirectional link with on-die waveform cap-ture, IEEE J. Solid-State Circuits38 (2003), no. 12, 2111–2120.

[CNN06] CNN, Chicken and egg debate unscrambled, http://www.cnn.

com/2006/TECH/science/05/26/chicken.egg , May 2006.

[CR04] A. Chan and G. Roberts,A jitter characterization system usinga component-invariant vernier delay line, Very Large Scale Inte-gration (VLSI) Systems, IEEE Transactions on12 (2004), no. 1,79–95.

[CT92] J. C. Candy and G. C. Temes (eds.),Oversampling Delta-Sigmadata converters, IEEE Press, 1992.

[CT06] M. Christensen and F. J. Taylor,Fixed-point-IIR-filter challenges,EDN (2006), 111–122.

[DDHSW01] N. Da Dalt, M. Harteneck, C. Sandner, and A. Wiesbauer,Numer-ical modeling of PLL jitter and the impact of its non-white spec-trum on the SNR of sampled signals, Proc. IEEE Southwest Symp.on Mixed-Signal Design (SSMSD), 2001, pp. 38–44.

[Dor92] R. C. Dorf,Modern control theory, 6th ed., Addison-Wesley Pub-lishing, Reading, Mass., 1992.

[DR99] B. Dufort and G. Roberts,On-chip analog signal generation formixed-signal built-in self-test, IEEE J. Solid-State Circuits34(1999), no. 3, 318–330.

[EBSB07] O. Eliezer, I. Bashir, R. B. Staszewski, and P. T. Balsara,Built-inself testing of a DRP-based GSM transmitter, IEEE Radio Fre-quency Integrated Circuits (RFIC) Symp. Dig. of Papers, 2007,pp. 339–342.

[Fet86] A. Fettweis,Wave digital filters: Theory and practice, Proc. of theIEEE74 (1986), no. 2, 270–327.

[Fet97] A. Fettweis,Alfred Fettweis, Electrical Engineer, an oral historyconducted in 1997 by Frederik Nebeker, IEEE History Center, Rut-gers University, New Brunswick, NJ, USA., 1997.

[Fet05] E. S. Fetzer,Method and circuit for measuring on-chip, cycle-to-cycle clock jitter, Patent US6841985, US Patent 6841985, Jan. 112005, Hewlett-Packard.

[FWM03] J. Ferrario, R. Wolf, and S. Moss,Architecting millisecond test


http://www.cnn.com/2006/TECH/science/05 /26/chicken.egg

http://www.cnn.com/2006/TECH/science/05 /26/chicken.egg

192 Bibliography

solutions for wireless phone RFIC’s, Proc. IEEE Int’l. Test Conf.(ITC), vol. 1, 2003, pp. 1325–1332.

[Gal93] I. Galton,Granular quantization noise in the first-order Delta-Sigma modulator, IEEE Trans. Inform. Theory39 (1993), no. 6,1944–1956.

[Gar79] F. M. Gardener,Phaselock techniques, John Wiley and Sons, NewYork, 1979, The PLL bible, but no CP’s.

[GKM+03] E. Götz, H. Kröbel, G. Märzinger, B. Memmler, C. Münker,B. Neurauter, D. Römer, J. Rubach, W. Schelmbauer, M. Scholz,M. Simon, U. Steinacker, and C. Stöger,A quad-band lowpower single chip direct conversion CMOS transceiver withΣ∆-modulation loop for GSM, Proc. European Solid-State CircuitsConf. (ESSCIRC) (Portugal), Sep. 2003, pp. 217–220.

[GMT83] R. Gregorian, K. Martin, and G. Temes,Switched-capacitor cir-cuit design, Proc. of the IEEE71 (1983), no. 8, 941–966.

[Gop05] A. Gopalan,Built-in self-test of RF front-end circuitry, Ph.D. the-sis, Rochester Institute of Technology, 2005.

[GPG01] V. Glöckel, M. Pronath, and H. Gräb,Deterministischerparametrischer Testentwurf für analoge integrierte Schaltungenmit Testbeobachtungen unter Anwendung von Ergebnissen ausdem Toleranzentwurf, Proc. of the ITG / GMM Workshop "Test-methods and Reliability of Circuits and Systems", vol. 13, Feb.2001.

[GSHA01] A. Giani, S. Sheng, M. Hsiao, and V. D. Agrawal,Efficient spec-tral techniques for sequential ATPG, Proc. Design, Automationand Test in Europe (DATE) Conf., 2001, pp. 204–208.

[Har78] F. Harris,On the use of windows for harmonic analysis with thediscrete Fourier transform, Proc. of the IEEE66 (1978), no. 1,51–83.

[HBKZ84] B. Hosticka, W. Brockherde, U. Kleine, and G. Zimmer, Switched-capacitor FSK modulator and demodulator in CMOS technology,IEEE J. Solid-State Circuits19 (1984), no. 3, 389–396.

[Hog81] E. Hogenauer,An economical class of digital filters for decima-tion and interpolation, IEEE Trans. Acoust., Speech, Signal Pro-cessing29 (1981), no. 2, 155–162.


Bibliography 193

[HR98] E. Hawrysh and G. Roberts,An integration of memory-based ana-log signal generation into current DFT architectures, IEEE Trans.Instrum. Meas.47 (1998), no. 3, 748–759.

[HS08] J.-C. Hsu and C. Su,BIST for measuring clock jitter of charge-pump phase-locked loops, IEEE Trans. Instrum. Meas.57 (2008),no. 2, 276–285.

[IEE08] IEEE STD 1139-2008 – standard definitions of physical quantitiesfor fundamental frequency and time metrology—random instabili-ties, 2008.

[Int05] International Roadmap Roadmap for Semiconductors2005 Edi-tion, Section: Test and test equipment, http://www.itrs.net, 2005.

[Jai91] R. Jain,The art of computer systems performance analysis, JohnWiley and Sons, 1991.

[Joi08] Joint Committee for Guides in Metrology,International vocab-ulary of metrology – Basic and general concepts and associ-ated terms (VIM), 3rd ed., Bureau International des Poids etMesures,www.bipm.org/utils/common/documents/jcgm/

JCGM_200_2008.pdf , 2008.

[Kal04] J. Kalisz,Review of methods for time interval measurements withpicosecond resolution, Metrologia41 (2004), no. 1, 17–32.

[KBK07] W. Khalil, B. Bakkaloglu, and S. Kiaei,A self-calibrated on-chipphase-noise measurement circuit with -75 dbc single-tone sensitiv-ity at 100 khz offset, IEEE J. Solid-State Circuits42(2007), no. 12,2758–2765.

[KDCM04] R. Kheriji, V. Danelon, J. Carbonero, and S. Mir,Optimising testsets for RF components with a defect-oriented approach, Proc.Symp. on Integrated Circuits and Systems Design (SBCCI), 2004,pp. 400–403.

[KDZ+05] S. Khorram, H. Darabi, Z. Zhou, Q. Li, B. Marholev, J. Chiu,J. Castaneda, H.-M. Chien, S. Anand, S. Wu, M.-A. Pan,R. Roofougaran, H. J. Kim, P. Lettieri, B. Ibrahim, J. Rael, L. Tran,E. Geronaga, H. Yeh, T. Frost, J. Trachewsky, and A. Rofougaran,A fully integrated SOC for 802.11b in 0.18-µm CMOS, IEEE J.Solid-State Circuits40 (2005), no. 12, 2492–2501.

[Kes05] W. Kester (ed.),Data conversion handbook, Newnes, 2005,


www.bipm.org/utils/common/documents/jcgm/JCGM_200_2008.pdf

www.bipm.org/utils/common/documents/jcgm/JCGM_200_2008.pdf

194 Bibliography

http://www.analog.com/library/analogDialogue/

archives/ 39-06/data_conversion_handbook.html.

[Kin73] N. G. Kingsbury,Second-order recursive filter elements for polesnear the unit circle and the real axis, Electronics Letters8 (1973),no. 6, 271–273.

[KK06] K.-D. Kammeyer and K. Kroschel,Digitale signalverarbeitung,Teubner Verlag, Wiesbaden , Germany, 2006.

[KMZ79] B. Konemann, J. Mucha, and G. Zwiehoff,Built-in logic block ob-servation technique, Proc. IEEE Int’l. Test Conf. (ITC), Oct. 1979,pp. 37–41.

[KSR00] S. Kim, M. Soma, and D. Risbud,An effective defect-orientedBIST architecture for high-speed phase-locked loops, Proc. IEEEVLSI Test Symp. (VTS), no. 18, 2000, pp. 231–236.

[Kun05] K. Kundert, Modeling jitter in PLL-based frequency syn-thesizers, http://www.designers-guide.org/Analysis/

PLLjitter.pdf, Sep. 2005.

[Lay05] J. Layole,Modelling and simulation of a PLL with jitter sourcesusing SystemC, Master’s thesis, Institute for Technical Electronics,Munich University of Technology, 2005.

[Lee98] T. H. Lee,The design of CMOS radio-frequency integrated cir-cuits, Cambridge University Press, Cambridge, UK, 1998.

[LH00] T. Lee and A. Hajimiri,Oscillator phase noise: a tutorial, IEEE J.Solid-State Circuits35 (2000), no. 3, 326–336.

[Li04] H. Li, BIST (Built-In Self-Test) strategy for mixed-signal inte-grated circuits, Ph.D. thesis, Technische Fakultät der UniversitätErlangen-Nürnberg, Erlangen, 2004, Prof. Dr. Robert Weigel.

[Lil05] J. Lillington, Wideband spectrum analysis using advanced DSPtechniques, Electronics World111(2005), no. 1828, 18–24.

[LMP96] M. Lubaszewski, S. Mir, and L. Pulz,ABILBO: Analog BuILt-inBlock Observer, IEEE/ACM Int’l. Conf. on Computer-Aided De-sign (ICCAD) Dig. Tech. Papers, 1996, pp. 600–603.

[LR98] A. Lu and G. Roberts,An oversampling-based analog multitonesignal generator, IEEE Trans. Circuits Syst. II45 (1998), no. 3,391–394.


http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html

http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html

http://www.designers-guide.org/Analysis /PLLjitter.pdf

http://www.designers-guide.org/Analysis /PLLjitter.pdf

Bibliography 195

[LRJ94] A. Lu, G. Roberts, and D. Johns,A high-quality analog oscilla-tor using oversampling D/A conversion techniques, IEEE Trans.Circuits Syst. II41 (1994), no. 7, 437–444.

[LRP+04] S. Levantino, L. Romanó, S. Pellerano, C. Samori, and A. L. La-caita, Phase noise in digital frequency dividers, IEEE J. Solid-State Circuits39 (2004), 775–784.

[Lük85] H.-D. Lüke,Signalübertragung, 3rd ed., Springer Verlag, Berlin,1985, General Communication Theory, Fourier Transformation,PM / FM modulation.

[Lyo06] R. Lyons, IIR filter question, http://www.dsprelated.com/showmessage/55463/1.php, April 2006, Newsgroup discus-sion.

[Mär00] G. Märzinger,Neuartige digitale Modulationsarchitektur mit ho-her spektraler Effizienz für Mobilfunkanwendungen, Ph.D. thesis,Johannes Kepler Universität Linz, 2000.

[MCAS05] A. Medury, I. Carlson, A. Alvandpour, and J. Stensby, Structuralfault diagnosis in charge-pump based phase-locked loops, Proc.Int’l. Conf. on VLSI Design (VLSID), 2005, pp. 842–845.

[Mey07] U. Meyer-Baese,Digital Signal Processing with Field Pro-grammable Gate Arrays, 3 ed., Springer, Berlin, 2007.

[Mil98] L. Milor, A tutorial introduction to research on analog and mixed-signal circuit testing, IEEE Trans. Circuits Syst. II45 (1998),no. 10, 1389–1407.

[MKNM05] C. Münker, B.-U. Klepser, B. Neurauter, and C. Mayer, Digital RFCMOS transceivers for GPRS and EDGE, IEEE Radio FrequencyIntegrated Circuits (RFIC) Symp. Dig. of Papers, 2005, pp. 265–268.

[MLS+04] K. Muhammad, D. Leipold, B. Staszewski, Y.-C. Ho, C. Hung,K. Maggio, C. Fernando, T. Jung, J. Wallberg, J.-S. Koh, S. John,I. Deng, O. Moreira, R. Staszewski, R. Katz, and O. Friedman,Adiscrete-time Bluetooth receiver in a 0.13µm digital CMOS pro-cess, IEEE Int’l. Solid-State Circuits Conf. (ISSCC) Dig. Tech.Papers, vol. 1, 2004, pp. 268–269.

[MMNV04] C. Münker, G. Märzinger, B. Neurauter, and R. Vuketich, Phasen-regelkreis und Verfahren zur Phasenkorrektur eines frequenzs-teuerbaren Oszillators, DPMA patent, DE102004014204, 2004.


http://www.dsprelated.com/showmessage/55463/1.php

http://www.dsprelated.com/showmessage/55463/1.php

196 Bibliography

[MNM +05] C. Mayer, B. Neurauter, G. Märzinger, C. Münker, and R. Hage-lauer, A robust GSM / EDGE transmitter using polar modula-tion techniques, Proc. European Microwave Week (EuMW) (Paris,France), vol. 35, October 2005.

[Moo03] G. Moore,No exponential is forever: But "forever" can be de-layed!, IEEE Int’l. Solid-State Circuits Conf. (ISSCC) Dig. Tech.Papers, vol. 1, 2003, pp. 20–23.

[MS78] K. Martin and A. Sedra,Design of signal flow graph (SFG) activefilters, IEEE Trans. Circuits Syst.25 (1978), no. 4, 185–195.

[MS86] K. Martin and M. Sun,Adaptive filters suitable for real-time spec-tral analysis, IEEE J. Solid-State Circuits21 (1986), no. 1, 108–119.

[MS02a] D. McMahill and C. Sodini,A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK au-tomatically calibratedΣ−∆ frequency synthesizer, IEEE J. Solid-State Circuits37 (2002), no. 1, 18–26.

[MS02b] C. Münker and M. Scholz,Phasenregelkreis mit Pulsgeneratorund Verfahren zum Betrieb des Phasenregelkreises, DPMA andWIPO patent application, DE10255099, 2002.

[MS03] , Phasenregelanordnung, DPMA patent application,DE10308643A1, Feb. 27 2003.

[MS07] , Detection arrangement, counter unit, phase locked loop,detection method and method for generating an oscillator signal,US patent application, US020080191921A1, Feb. 27 2007.

[MSMG02] C. Münker, M. Scholz, G. Märzinger, and E. Götz,Schal-tungsanordnung zur Phasenregelung und Verfahren zum Betriebder Schaltungsanordnung, DPMA patent, DE10255145B4, Nov.11 2002.

[Mün04] C. Münker,Fast simulation of complex RF mixed-signal systemsusing standard VHDL, Workshop "Mixed-Signal Design Method-ology & Environment" at the RFIC2004 (Fort Worth, USA), Jun.2004.

[Mün05] , A compact multi-tone test generator for RF ICs using aSigma-Delta PLL, GMM Proceedings "Analog ’05 - Entwicklungvon Analogschaltungen mit CAE Methoden" [Analog design us-ing CAE methods], vol. 46, VDE Verlag, 2005, pp. 289–292.


Bibliography 197

[MW06] C. Münker and R. Weigel,RF built-in self-test for integratedcellular transmitters, GMM Proceedings "Analog ’06 - Entwick-lung von Analogschaltungen mit CAE Methoden" [Analog designusing CAE methods] (Dresden, Germany), no. 196, Sep. 2006,pp. 209 – 214.

[MW07] , Spectral PLL built-in self-test for integrated cellulartransceivers, Proc. European Solid-State Circuits Conf. (ESS-CIRC) (Munich, Germany), Sep. 2007, pp. 476–479.

[Ohl91] M. J. Ohletz, Hybrid built-in self-test (HBIST) for mixedanalog/digital integrated circuits, Proc. European Test Conf.(ETC), 1991, pp. 307–316.

[Pec86] G. Peceli,A common structure for recursive discrete transforms,IEEE Trans. Circuits Syst.33 (1986), no. 10, 1035–1036.

[Pec88] , Sensitivity properties of resonator-based digital filters,IEEE Trans. Circuits Syst.35 (1988), no. 9, 1195 – 1197.

[Pec89] , Resonator-based digital filters, IEEE Trans. CircuitsSyst.36 (1989), no. 1, 156–159.

[Per97] M. H. Perrott,Techniques for high data rate modulation and lowpower operation of fractional-N frequency synthesizers, Ph.D. the-sis, Massachusetts Institute of Technology, 1997.

[Pla00] M. Planat (ed.),Noise, oscillators and algebraic randomness, Lec-ture Notes in Physics, Springer Berlin / Heidelberg, 2000, FromNoise in Communication Systems to Number Theory, Lectures ofa School Held in Chapelle des Bois, France, April 5–10, 1999.

[PM91] M. Padmanabhan and K. Martin,Resonator-based filter-banksfor frequency-domain applications, IEEE Trans. Circuits Syst.38(1991), no. 10, 1145–1159.

[PM92] J. G. Proakis and D. G. Manolakis,Digital signal processing:Principles, algorithms, and applications, 2nd ed., Macmillan Pub-lishing Company, New York, 1992.

[PM93] M. Padmanabhan and K. Martin,Filter banks for time-recursiveimplementation of transforms, IEEE Trans. Circuits Syst. II40(1993), no. 1, 41–50.

[PN03] Z. Plíva and O. Novák,Scan based circuits with low power con-sumption, Proc. Design and Diagnostics of Electronic Systems


198 Bibliography

and Circuits (DDESC) Workshop (Poznan, Poland), Apr. 2003,pp. 267–232.

[PTS97] M. Perrott, I. Tewksbury, T.L., and C. Sodini,A 27-mW CMOSfractional-N synthesizer using digital compensation for 2.5-Mb/sGFSK modulation, IEEE J. Solid-State Circuits32 (1997), no. 12,2048–2060.

[RA00] J. Rael and A. Abidi,Physical processes of phase noise in differen-tial LC oscillators, Proc. IEEE Custom Integrated Circuits Conf.(CICC), 2000, pp. 569–572.

[RAB97] M. Renovell, F. Azais, and Y. Bertrand,On-chip analog out-put response compaction, Proc. European Design and Test Conf.(ED&TC), 1997, pp. 568–572.

[Ros92] E. Rosenfeld,A method of jitter measurement, Proc. IEEE Int’l.Test Conf. (ITC), 1992, pp. 788–794.

[RS01] M. Ramezani and C. Salama,An improved bang-bang phase de-tector for clock and data recovery applications, Proc. IEEE Int’l.Symp. on Circuits and Systems (ISCAS), vol. 1, 2001, pp. 715–718.

[Sch] B. Schottstaedt,An introduction to FM, http://ccrma.

stanford.edu/software/snd/snd/fm.html.

[SCP+99] S. Sengupta, S. S. Chakravarty, P. Parvathala, R. Galivanche,G. Kosonocky, M. Rodgers, and T. Mak,Defect-based test: A keyenabler for successful migration to structural test, Intel Technol-ogy Journal3 (1999), no. 1, 1–14.

[SFB05] R. Staszewski, C. Fernando, and P. Balsara,Event-driven simula-tion and modeling of phase noise of an RF oscillator, IEEE Trans.Circuits Syst. I52 (2005), no. 4, 723–733.

[SH04] J. Segura and C. F. Hawkins,CMOS electronics: How it works,how it fails, John Wiley and Sons, Inc., 2004.

[SK93] M. Slamani and B. Kaminska,T-BIST: A built-in self-test foranalog circuits based on parameter translation, Proc. Asian TestSymp. (ATS), 1993, pp. 172–177.

[SK97] G. Stoyanov and M. Kawamata,Variable digital filters, J. SignalProcessing1 (1997), no. 4, 275–289.


http://ccrma.stanford.edu/software/snd/snd/fm.html

http://ccrma.stanford.edu/software/snd/snd/fm.html

Bibliography 199

[Smi05] J. O. Smith, Introduction to digital filters, http://ccrma.

stanford.edu/~jos/filters05/, Sep. 2005, Draft.

[Smi07] , Spectral audio signal processing, http://ccrma.

stanford.edu/~jos/sasp/, Mar. 2007, Draft.

[SML+04] R. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. Wallberg, C. Fernando, K. Maggio, R. Staszewski,T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo,V. Mayega, R. Katz, O. Friedman, O. Eliezer, E. de Obaldia, andP. Balsara,All-digital TX frequency synthesizer and discrete-timereceiver for Bluetooth radio in 130-nm CMOS, IEEE J. Solid-StateCircuits39 (2004), no. 12, 2278–2291.

[SOE01] S. Sattler, D. Oberle, and J. Eckmüller,PLL built-in self-test jit-ter measurement integration into 0.18µ CMOS technology, Proc.Test Methods and Reliability of Circuits and Systems Workshop(Miesbach, Germany), Feb. 2001, pp. 43–47.

[SP09] M. Straayer and M. Perrott,A multi-path gated ring oscillatorTDC with first-order noise shaping, Solid-State Circuits, IEEEJournal of44 (2009), no. 4, 1089–1098.

[SR99] S. Sunter and A. Roy,BIST for phase-locked loops in digital ap-plications, Proc. IEEE Int’l. Test Conf. (ITC), 1999, pp. 532–540.

[SR02] S. K. Sunter and A. P. J. Roy,Method and circuit for built in selftest of phase locked loops, Tech. report, US Patent 6396889, May28 2002.

[SR07] , Circuit and method for measuring jitter of high speedsignals, Tech. report, US Patent 7158899, Jan. 2 2007.

[ST76] M. Swamy and K. Thyagarajan,Digital bandpass and bandstopfilters with variable center frequency and bandwidth, Proc. of theIEEE64 (1976), no. 11, 1632–1634.

[Ste94] K. Steiglitz,A note on constant-gain digital resonators, ComputerMusic Journal18 (1994), 8–10.

[SW98] Y.-R. Sheh and C.-W. Wu,Control and observation structures foranalog circuits, IEEE Des. Test. Comput.15 (1998), no. 2, 56–64.

[Ter05] M. Terrovitis,Simulating the phase noise contribution of the di-vider in a phase lock loop, Tech. report, Designers’ Guide Commu-


http://ccrma.stanford.edu/~jos/filters05/

http://ccrma.stanford.edu/~jos/filters05/

http://ccrma.stanford.edu/~jos/sasp/

http://ccrma.stanford.edu/~jos/sasp/

200 Bibliography

nity, www.designers-guide.org/Analysis/PLLjitter.pdf, September2005.

[TGS+09] A. Tchegho, H. Gräb, U. Schlichtmann, H. Mattes, and S. Sat-tler, Analyse und Untersuchung der Quantisierungseffekte beimGoertzel-Filter, Adv. Radio Sci.7 (2009), 73–81.

[TR86] L. Turner and B. Ramesh,Low sensitivity digital LDI ladder filterswith elliptic magnitude response, IEEE Trans. Circuits Syst.33(1986), no. 7, 697–706.

[TR93a] M. Toner and G. Roberts,A BIST scheme for an SNR test ofa Sigma-Delta ADC, Proc. IEEE Int’l. Test Conf. (ITC), 1993,pp. 805–814.

[TR93b] , Towards built-in self-test for SNR testing of a mixed-signal IC, Proc. IEEE Int’l. Symp. on Circuits and Systems (IS-CAS), 1993, pp. 1599–1602 vol.3.

[TR95a] , A BIST scheme for a SNR, gain tracking, and frequencyresponse test of a Sigma-Delta ADC, IEEE Trans. Circuits Syst. II42 (1995), no. 1, 1–15.

[TR95b] , On the practical implementation of mixed analog-digitalBIST, Proc. IEEE Custom Integrated Circuits Conf. (CICC), 1995,pp. 525–528.

[TR96] , A frequency response, harmonic distortion, and inter-modulation distortion test for BIST of a Sigma-Delta ADC, IEEETrans. Circuits Syst. II43 (1996), no. 8, 608–613.

[Tum06] R. R. Tummala,Moore’s law meets its match, IEEE Spectr.6(2006), 38–43.

[VB03] P. N. Variyam and H. Balachandran,All digital built-in self-testcircuit for phase-locked loops, Patent, US Patent 6661266, Dec. 92003.

[VDP30] B. Van Der Pol,Frequency modulation, Proc. of the IRE18(1930),no. 7, 1194–1205.

[vdP94] R. van der Plassche,Integrated analog-to-digital and digital-to-analog converters, Kluwer Academic, Boston, 1994.

[VFL+00] C. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli,and Z. Wang,A family of low-power truly modular programmable


Bibliography 201

dividers in standard 0.35-µm CMOS technology, IEEE J. Solid-State Circuits35 (2000), no. 7, 1039–1045.

[VGKB+07] A. Valdes-Garcia, W. Khalil, B. Bakkaloglu, J. Silva-Martinez,and E. Sanchez-Sinencio,Built-in self test of RF transceiver SoCs:from signal chain to RF synthesizers, IEEE Radio Frequency Inte-grated Circuits (RFIC) Symp. Dig. of Papers, 2007, pp. 335–338.

[Vid05] J. Vidkjaer, Class Notes Course 31415 RF-Communication Cir-cuits, Technical University of Denmark, 2005.

[Wel67] P. Welch,The use of fast Fourier transform for the estimation ofpower spectra: A method based on time averaging over short,modified periodograms, IEEE Trans. Audio Electroacoust.15(1967), no. 2, 70–73.

[Wey90] C.-L. Wey,Built-in self-test (BIST) structure for analog circuitfault diagnosis, IEEE Trans. Instrum. Meas.39 (1990), no. 3, 517–521.

[Won00] M.-T. Wong,On the issues of oscillation test methodology, IEEETrans. Instrum. Meas.49 (2000), no. 2, 240–245.

[Wur93] L. Wurtz, Built-in self-test structure for mixed-mode circuits,IEEE Trans. Instrum. Meas.42 (1993), no. 1, 25–29.

[YL07] G. Yu and P. Li,A methodology for systematic built-in self-test ofphase-locked loops targeting at parametric failures, Proc. IEEEInt’l. Test Conf. (ITC), 2007, pp. 1–10.

[YS89] J. Yuan and C. Svensson,High-speed CMOS circuit technique,IEEE J. Solid-State Circuits24 (1989), no. 1, 62–70.

[ZB95] U. Zölzer and T. Boltze,Parametric digital filter structures, Proc.99th Audio Engineering Society (AES) Convention, Sep. 1995.

[Zie96] C. Zierhofer,A multiplier-free digital sinusoid generator based onSigma-Delta modulation, IEEE Trans. Circuits Syst. II43 (1996),no. 5, 387–396.

[Zöl05] U. Zölzer, Digitale Audiosignalverarbeitung, 3rd ed., Teubner,Wiesbaden, Germany, 2005.


202 Bibliography


List of Figures

1.1. Overview over DfT techniques . . . . . . . . . . . . . . . . . . 51.2. Scan structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.3. Scan flip-flop with test-logic overhead . . . . . . . . . . . . . . 91.4. Principle of digital BIST . . . . . . . . . . . . . . . . . . . . . 141.5. PLL BIST for measuring cycle-to-cycle jitter . . . . . . . .. . 171.6. On-chip phase noise measurement circuit . . . . . . . . . . . .18

2.1. Spectra of narrowband and wideband sinusoidal FM . . . . .. . 282.2. One-sided and two-sided spectra . . . . . . . . . . . . . . . . . 292.3. Phasors for small-angle PM/FM . . . . . . . . . . . . . . . . . 302.4. PSD of phase deviation and frequency deviation . . . . . . .. . 332.5. Basic slices of the signalxN . . . . . . . . . . . . . . . . . . . . 362.6. Overlapping windowed slices of the signalxN . . . . . . . . . . 372.7. Displayed PSD of noise signal . . . . . . . . . . . . . . . . . . 382.8. Derivation of phase fluctuations from the VCO periods . .. . . 382.9. Spectral density of quantization noise . . . . . . . . . . . . .. 412.10. Subsampling and frequency translation . . . . . . . . . . . .. . 432.11. Delta modulation and demodulation . . . . . . . . . . . . . . . 442.12. (Sigma)-Delta modulation signal forms . . . . . . . . . . . .. 442.13. Sigma-Delta modulation and demodulation . . . . . . . . . .. 442.14. Sigma-Delta modulation (efficient implementation) .. . . . . . 452.15. Digital sigma-delta modulator . . . . . . . . . . . . . . . . . . 452.16. Model for quantization noise inΣ∆M bit stream . . . . . . . . . 462.17. Signal and noise transfer functions in first orderΣ∆M . . . . . . 472.18. Nyquist rate, oversampling andΣ∆M converters . . . . . . . . . 482.19. SDM noise for DC inputs . . . . . . . . . . . . . . . . . . . . . 492.20. Second order multi-loop SDM . . . . . . . . . . . . . . . . . . 502.21. Second order multi-loopΣ∆M with a1 = a2 = 1 . . . . . . . . . 502.22. Equivalent second order single-loop SDM . . . . . . . . . . .. 502.23. Quantization noise model for second order multi-loopSDM . . 512.24. Second order digitalΣ∆M with multistage noise shaping . . . . 512.25. Stability region of a second order system . . . . . . . . . . .. . 532.26. Poles’ and zeros’ contribution . . . . . . . . . . . . . . . . . . 54

203

204 List of Figures

2.27. Calculation of distance from pole . . . . . . . . . . . . . . . . .552.28. Frequency response of the two-pole resonator . . . . . . .. . . 562.29. Frequency response of the two-pole resonator . . . . . . .. . . 572.30. Constant peak gain resonator . . . . . . . . . . . . . . . . . . . 582.31. Frequency response of the constant peak-gain biquad .. . . . . 592.32. Band-pass filter specifications . . . . . . . . . . . . . . . . . . 592.33. Estimation of resonator bandwidth . . . . . . . . . . . . . . . .602.34. Direct form resonator . . . . . . . . . . . . . . . . . . . . . . . 612.35. LDI based resonator . . . . . . . . . . . . . . . . . . . . . . . . 622.36. Coupled-form resonator . . . . . . . . . . . . . . . . . . . . . . 622.37. Fixed-point number representation . . . . . . . . . . . . . . .. 632.38. Types of digital filters . . . . . . . . . . . . . . . . . . . . . . . 652.39. Type II direct form filter . . . . . . . . . . . . . . . . . . . . . 662.40. Doubly terminated fourth order ladder LC band-pass filter . . . 672.41. Second order LC band-pass with SFG and DT simulation . .. . 682.42. Resonator based filter bank . . . . . . . . . . . . . . . . . . . . 702.43. Singly terminated LC ladder filter bank . . . . . . . . . . . . .71

3.1. Phase noise and spurious sidebands on the VCO output . . .. . 743.2. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . 753.3. PLL block diagram - control theory point of view . . . . . . .. 753.4. Closed loop gain|T( jω)| and noise bandwidthBn . . . . . . . . 783.5. Principle ofΣ∆-modulated PLL with predistortion . . . . . . . . 793.6. Simulation of PLL lock-in with built-in self-calibration . . . . . 803.7. RMS phase error as a function of the open loop bandwidth .. . 813.8. Block diagram of quad band GSM transceiver . . . . . . . . . . 823.9. Power spectral density mask for GSM 900 and DCS 1800 . . . .833.10. RMS phase error as a function of the open loop gain error. . . . 84

4.1. Spectral PLL BIST Concept . . . . . . . . . . . . . . . . . . . 884.2. Principle of PLL bandwidth measurement . . . . . . . . . . . . 894.3. MADBIST vs. SP-BIST . . . . . . . . . . . . . . . . . . . . . 914.4. Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . 924.5. Block diagram of Fractional-N PLL . . . . . . . . . . . . . . . 954.6. Simulation setup for CUT and SP-BIST . . . . . . . . . . . . . 964.7. PLL simulation error due to sampled filter model . . . . . . .. 964.8. Principle of fractional compensation . . . . . . . . . . . . . .. 974.9. Simulation of unmodulatedΣ∆PLL tuning voltage . . . . . . . . 1014.10. Simulation ofΣ∆PLL spectrum . . . . . . . . . . . . . . . . . . 102

5.1. Implementations for undamped digital resonators . . . .. . . . 105


List of Figures 205

5.2. Oscillator based on analog integrators . . . . . . . . . . . . .. 1065.3. Principle of LDI based oscillator . . . . . . . . . . . . . . . . . 1075.4. SDM attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . 1095.5. LDI oscillator usingΣ∆M attenuator . . . . . . . . . . . . . . . 1105.6. Two-tone LDI oscillator usingΣ∆M attenuator . . . . . . . . . . 1115.7. Spectrum of two-tone signal (parallel output) . . . . . . .. . . 1115.8. Spectrum of two-tone signal (SDM bit stream) . . . . . . . . .. 1125.9. Fractional-N modulator with test tone generation . . . .. . . . 1145.10. Simulated phase spectrum of two-tone modulated PLL . .. . . 1155.11. Single-tone modulation (measured with spectrum analyzer) . . . 116

6.1. Principle of analog swept spectrum analyzer . . . . . . . . .. . 1186.2. Swept-tuned spectrum analysis . . . . . . . . . . . . . . . . . . 1196.3. Envelope detector . . . . . . . . . . . . . . . . . . . . . . . . . 1196.4. Phase detector based phase noise measurement . . . . . . . .. 1206.5. Frequency discriminator based phase noise measurement . . . . 1216.6. Comparison ofΣ∆M andΣ∆FD . . . . . . . . . . . . . . . . . 1236.7. Principle ofΣ∆FD (b), derived fromΣ∆-Frac-N-PLL (a) . . . . 1246.8. Signals in first orderΣ∆FD: Transient view . . . . . . . . . . . 1256.9. Signals in first orderΣ∆FD: Phase view . . . . . . . . . . . . . 1266.10. Multi-modulus divider . . . . . . . . . . . . . . . . . . . . . . 1276.11. Linearized model for multi-modulus divider phase . . .. . . . . 1286.12. 1st orderΣ∆FD model . . . . . . . . . . . . . . . . . . . . . . 1306.13. Two-tone spectrum atΣ∆FD output . . . . . . . . . . . . . . . 1316.14. Two-tone spectrum atΣ∆FD output (zoomed in) . . . . . . . . . 1316.15. 2nd orderΣ∆FD (simplified) . . . . . . . . . . . . . . . . . . . 1326.16. Swept filter spectrum analyzer . . . . . . . . . . . . . . . . . . 1336.17. Principle of on-chip spectral PLL analysis . . . . . . . . .. . . 1356.18. Block diagram of spectral estimation . . . . . . . . . . . . . .. 1366.19. 2nd order CIC as anti-aliasing filter . . . . . . . . . . . . . . . . 1376.20. Hogenauer filter . . . . . . . . . . . . . . . . . . . . . . . . . . 1386.21. Second order downsampling CIC filter with dump and reset . . . 1386.22. Transfer function and aliasing of downsampling CIC filter . . . 1396.23. Two-tone spectrum atΣ∆FD output . . . . . . . . . . . . . . . 1406.24.Σ∆Mquantization noise after CIC filtering . . . . . . . . . . . . 1416.25. SimulatedΣ∆FD output spectrum with CIC filtering . . . . . . . 1426.26. LDI based resonator . . . . . . . . . . . . . . . . . . . . . . . . 1436.27. Resonator based filter with constantB or constantQ . . . . . . . 1456.28. Transfer functions of resonator based filter with constant BW . . 1466.29. Resonator based bandpass with constant peak gain . . . .. . . 1476.30. Bandpass gain and scalloping loss of 2nd order resonator . . . . 147


206 List of Figures

6.31. -3 dB and -60 dB bandwidth of different band-pass filters . . . . 1496.32. Bandpass gain and scalloping loss of 4th order resonator . . . . 150

7.1. Frequency of LDI oscillator . . . . . . . . . . . . . . . . . . . . 1557.2. Amplitude error of LDI based oscillator . . . . . . . . . . . . .1567.3. Schematic ofΣ∆FD . . . . . . . . . . . . . . . . . . . . . . . . 1577.4. Multi-modulus divider made from a chain of 2/3 divider cells . . 1577.5. High-speed 2/3 divider cell with modulus enable . . . . . .. . 1587.6. Dynamic high-speed flip-flop . . . . . . . . . . . . . . . . . . . 1597.7. Layout of MMD . . . . . . . . . . . . . . . . . . . . . . . . . . 1617.8. RF PLL under test with SP-BIST . . . . . . . . . . . . . . . . . 1627.9. Block diagram of multimode RF transceiver . . . . . . . . . . .1637.10. Unmodulated PLL spectrum with and without activeΣ∆FD . . . 1647.11. Spectrum of two-tone generator (different filter staggering) . . . 1667.12. Unmodulated PLL spectrum withΣ∆FD spurious tones . . . . . 1687.13. Single-tone modulated PLL spectrum . . . . . . . . . . . . . . 1707.14. Two-tone modulated PLL spectrum (frequency sweep avg.) . . . 1717.15. Comparison of baseband and RF output response analysis . . . . 172

A.1. Non-Integrating loop filter with charge pump . . . . . . . . .. 183


List of Tables

2.1. Examples for binary encoding . . . . . . . . . . . . . . . . . . 642.2. Qualitative comparison of digital filter families . . . .. . . . . 72

5.1. SNR of two-tone generator depending on bandwidthBW . . . . 113

6.1. Passband droop and alias rejection of CIC filters . . . . . .. . . 1406.2. Resonance frequency forfS,R = 812.5 kHz . . . . . . . . . . . . 1446.3. Bandpass properties atkf = 1 ( fc = 135.4 kHz) . . . . . . . . . 1486.4. Variation of bandpass properties over 10 . . . 200 kHz . . .. . . 150

7.1. Frequencies of programmable tones . . . . . . . . . . . . . . . 1547.2. Amplitudes of programmable tones . . . . . . . . . . . . . . . . 1567.3. Silicon area of SP-BIST blocks . . . . . . . . . . . . . . . . . . 1607.4. Reproducibility of SP-BIST measurements . . . . . . . . . . .. 1677.5. Output frequency response measurements . . . . . . . . . . . .1737.6. Programming registers . . . . . . . . . . . . . . . . . . . . . . 177

207

208 List of Tables


Index

Symbols

Σ∆PLL . . . . .seePLL, Sigma-Deltamodulated

A

accuracy . . . . . . . . . . . . . . . . . . . . . . 22ACF. .seeauto-correlation functionanalog scan chain. . . . . . . . . . . . . .10ATE . . . . . . . . . . . . . . . . . . . . . . . . . . . 3auto-correlation function . . . . 17, 36automated test equipmemtseeATE

B

backward Euler integrator . . . . . 105bandwidth

half-power . . . . . . . . . . . . . . . 60modulation . . . . . . . . . . . . . . . 25normalized . . . . . . . . . . . . . . . 60relative . . . . . . . . . . . . . . . . . . 60

bias . . . . . . . . . . . . . . . . . . . . . . . . . . 22BILBO . . . . seebuilt-in logic block

observerbiquad . . . . . . . . . . . . . . . . . . . . . . . . 57biquadratic transfer function . . . . 57BISC . . seebuilt-in self-calibrationBIST . . . . . . . . .seebuilt-in self-testbit-error rate . . . . . . . . . . . . . . . . . . 18BOST . . . . . . .seebuilt-off self-testbuilt-in logic block observer . . . . 14built-in self-calibration . . . . . . 3, 79built-in self-test . . . . . . 2, 13, 20, 79

analog . . . . . . . . . . . . . . . . . . . 14hybrid . . . . . . . . . . . . . . . . . . . 15logic . . . . . . . . . . . . . . . . . . . . .13memory . . . . . . . . . . . . . . . . . .14mixed analog-digital . . . . . . 15oscillation . . . . . . . . . . . . . . . . 14spectral PLL . . . . . . . . . . . . . 90

built-off self-test . . . . . . . . . . . 13, 20

C

cascaded integrator-comb filter 136center frequency. . . . . . . . . . . . . . .55CIC filter . . . . . . . . . . . .seecascaded

integrator-comb filtercircuit under test . . . . . . . . . . . . . . .11clock-and-data recovery . . . . . . . . 17cumulative distribution function .17CUT . . . . . . . . .seecircuit under test

D

damping . . . . . . . . . . . . . . . . . . . . . . 77DDS. . . .seedirect digital synthesisdecimation . . . . . . . . . . . . . . . . . . . .42defect . . . . . . . . . . . . . . . . . . . . . . . . . 7

bridging . . . . . . . . . . . . . . . . . . .8Design-for-Test . . . . . . . . . . . . . . 2, 6device under test . . . . . . . . . . . . . . .11DfT . . . . . . . . . .seeDesign-for-Testdirect digital synthesis . . . . . . . . 104DOT . . . . . .seetest, defect-orienteddownsampling . . . . . . . 42, 122, 136DUT. . . . . . . . .seedevice under test

209

210 Index

F

failure . . . . . . . . . . . . . . . . . . . . . . . . . 7fault . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

catastrophic . . . . . . . . . . . . . . . 9hard . . . . . . . . . . . . . . . . . . . . . . 9parametric . . . . . . . . . . . . . . . 10soft . . . . . . . . . . . . . . . . . . . . . . 10stuck-at . . . . . . . . . . . . . . . . . . . 8stuck-open . . . . . . . . . . . . . . . . 8

fault model . . . . . . . . . . . . . . . . . . . . .7feature extraction . . . . . . . . . . . . . . 11filter

cascaded . . . . . . . . . . . . . . . . . 66non-recursive . . . . . . . . . . . .135parallel . . . . . . . . . . . . . . . . . . 67recursive . . . . . . . . . . . . . . . . 135SOS) . . . . . . . . . . . . . . . . . . . . 66wave digital . . . . . . . . . . . . . . 69

filter bank . . . . . . . . . . . . . . . . . . . . 70forward Euler integrator . . . . . . .105Fourier transform. . . . . . . . . . . . . . 36frequency

carrier . . . . . . . . . . . . . . . . . . . 23instantaneous . . . . . . . . . . . . . 24modulation . . . . . . . . . . . . . . . 28nominal . . . . . . . . . . . . . . . . . . 23offset . . . . . . . . . . . . . . . . . . . . 28resonance . . . . . . . . . . . . . . . 144

frequency deviation . . . . . . . . . . . . 24peak . . . . . . . . . . . . . . . . . . . . . 25relative . . . . . . . . . . . . . . . . . . 24

frequency discriminatorsigma-delta . . . . . . . . . . . . . 156

frequency instability . . . . . . . . . . . 32frequency modulation gain . . . . . 24

G

Goertzel algorithm . . . . . . . . . . . 134

I

idle tones. . . . . . . . . . . . . . . . .49, 167

L

LFSR . . . . . . . . .seelinear-feedbackshift-register

linear-feedback shift-register . . . 13loop back test . . . . . . . . . . . . . . . . . 11loop gain transit frequency . . . . . 77lossless digital resonator . . . . . . . 62

M

MADBIST. . . .seebuilt-in self-test,mixed analog-digital, 90

message signal . . . . . . . . . . . . . . . . 24modulation index

frequency . . . . . . . . . . . . . . . . 25modulation signal . . . . . . . . . . . . . 24Moore’s law . . . . . . . . . . . . . . . . . . . 2multiple-input signature register 14

N

narrowband approximation . . . . . 27natural frequency . . . . . . . . . . . . . . 77network

prototype . . . . . . . . . . . . . . . . 68reference . . . . . . . . . . . . . . . . . 68

noise bandwidth . . . . . . . . . . 78, 150

O

ORA. .seeoutput response analysisoutput response analysis. . . . . . . .13

P

periodogram . . . . . . . . . . . . . . . . . . 36averaged . . . . . . . . . . . . . . . . . 36

phase


Index 211

instantaneous . . . . . . . . . . . . . 24nominal . . . . . . . . . . . . . . . . . . 23

phase deviation . . . . . . . . . . . . . . 23 f.phase instability . . . . . . . . . . . . . . . 32phase modulation gain . . . . . . . . . 24phase noise . . . . . . . . . . . . . . . . . . . 32phase-locked loop . . . . . . . .seePLLPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Sigma-Delta modulated . . . . . 3pole angle . . . . . . . . . . . . . . . . . . . . 53pole radius . . . . . . . . . . . . . . . . . . . . 53power spectral density . . . . . . . . . 36PRBS. . .seepseudo-random binary

sequenceprecision . . . . . . . . . . . . . . . . . . . . . 22probability density function. . . . .17pseudo-random binary sequence 14

Q

quality factor . . . . . . . . . . . . . . . . . .60

R

resolution . . . . . . . . . . . . . . . . . . . . .22resolution bandwidth . . . . . . . . . . 83resonance frequency . . . . . . . . . . . 55

S

sampling rateeffective . . . . . . . . . . . . . . . . 110

scalloping loss . . . . . . . . . . . . . . . 147scan chain

analog . . . . . . . . . . . . . . . . . . . 10SDFD .seefrequency discriminator,

sigma-deltaSDM . seeSigma Delta Modulationselectivity . . . . . . . . . . . . . . . . . . . . 58shape factor . . . . . . . . . . . . . . . . . . . 58sigma delta frequency discrimina-

tion . . . . . . . . . . . . . . . . 122

sigma delta modulation . . . . . . . 123signal-flow graph . . . . . . . . . . . . . . 69signature . . . . . . . . . . . . . . . . . . . . 13 f.small angle approximation. . . . . .27SPOT . . . . . . .seetest, specification

orientedsubsampling . . . . . . . . . . . . . . 42, 122system

LTI . . . . . . . . . . . . . . . . . . . . . . 22shift-invariant . . . . . . . . . . . . 22

T

testalternate. . . . . . . . . . . . . . . . . .11defect-oriented. . . . . . . . . . . . .4functional . . . . . . . . . . . . . . . . . 4RF structural . . . . . . . . . . . . . 10specification oriented . . . . . . . 4structural . . . . . . . . . . . . . . . . . . 4translation . . . . . . . . . . . . . . . . 11

test insertion . . . . . . . . . . . . . . . . . . 19test vector . . . . . . . . . . . . . . . . . . . . . .7test-pattern generation . . . . . . . . . 13time-to-digital converter . . . . . . 123TPG . . . .seetest-pattern generationtranfer function

noise . . . . . . . . . . . . . . . . . . . . 47signal . . . . . . . . . . . . . . . . . . . . 47

U

uncertainty . . . . . . . . . . . . . . . . . . . 22undersampling . . . . . . . . . . . . . . . . 42

W

wave variable . . . . . . . . . . . . . . . . . 69


Spectral PLL Built-In Self-Test for Integrated Cellular ... · Spectral PLL Built-In Self-Test for...

Documents

Transcript of Spectral PLL Built-In Self-Test for Integrated Cellular ... · Spectral PLL Built-In Self-Test for...