Von neumann architecture

The Von Neumann ArchitectureThe Von Neumann Architecture

Von NeumannVon NeumannArchitectureArchitecture

Designing ComputersDesigning Computers

• All computers more or less based on the same All computers more or less based on the same basic design, the basic design, the Von Neumann ArchitectureVon Neumann Architecture!!

2SYED ZARYAB HUSSAIN Computer Architectures & Fetch-Execute Cycle

Computer Architectures & Fetch-Execute Cycle


• Model for designing and building computers, Model for designing and building computers, based on the following three characteristics:based on the following three characteristics:

1)1) The computer consists of four main sub-systems:The computer consists of four main sub-systems:• MemoryMemory• ALU (Arithmetic/Logic Unit)ALU (Arithmetic/Logic Unit)• Control UnitControl Unit• Input/Output System (I/O)Input/Output System (I/O)

1)1) Program is stored in memory during execution.Program is stored in memory during execution.

2)2) Program instructions are executed sequentially.Program instructions are executed sequentially.

3SYED ZARYAB HUSSAIN



Memory

Processor (CPU)

Input-OutputControl Unit

ALUStore data and programStore data and program

Execute programExecute program

Do arithmetic/logic operationsDo arithmetic/logic operationsrequested by programrequested by program

Communicate withCommunicate with"outside world", e.g. "outside world", e.g. • ScreenScreen• KeyboardKeyboard• Storage devices Storage devices • ......

Bus



Memory SubsystemMemory Subsystem• Memory, also called Memory, also called RAMRAM ( (RRandom andom AAccess ccess MMemory), emory),

– Consists of many memory cells (storage units) of a fixed size. Consists of many memory cells (storage units) of a fixed size. Each cell has an address associated with it: 0, 1, …Each cell has an address associated with it: 0, 1, …

– All accesses to memory are to a specified address.All accesses to memory are to a specified address.A cell is the minimum unit of access (fetch/store a complete A cell is the minimum unit of access (fetch/store a complete cell).cell).

– The time it takes to fetch/store a cell is the same for all cells.The time it takes to fetch/store a cell is the same for all cells.

• When the computer is running, bothWhen the computer is running, both– ProgramProgram– Data (variables)Data (variables)

are stored in the memory.are stored in the memory. 5SYED ZARYAB HUSSAIN


RAMRAM• Need to distinguish between Need to distinguish between

– the the addressaddress of a memory cell and of a memory cell and the the contentcontent of a memory cell of a memory cell

• Memory width (Memory width (WW):):– How many bits is each memory How many bits is each memory

cell, typically one cell, typically one bytebyte (=8 bits) (=8 bits)

• Address width (Address width (NN):):– How many bits used to represent How many bits used to represent

each address, determines the each address, determines the maximum memory size = maximum memory size = address address spacespace

– If address width is If address width is NN-bits, then -bits, then address space is address space is 22NN (0,1,...,2 (0,1,...,2NN-1)-1)

...

00

11

22

22NN-1-1

1 bit1 bit

WW

00000000000000010000000000000001

NN

22NN



Memory Size / SpeedMemory Size / Speed

• Typical memory in a personal computer (PC):Typical memory in a personal computer (PC):– 64MB - 256MB64MB - 256MB

• Memory sizes:Memory sizes:– Kilobyte Kilobyte (KB)(KB) = 2= 210 10 = = 1,024 bytes ~ 1 thousand 1,024 bytes ~ 1 thousand– Megabyte(MB)Megabyte(MB) = 2= 22020 = = 1,048,576 bytes ~ 1 million 1,048,576 bytes ~ 1 million– GigabyteGigabyte (GB)(GB) = 2= 23030 = = 1,073,741,824 bytes ~ 1 billion 1,073,741,824 bytes ~ 1 billion

• Memory Access Time (read from/ write to memory)Memory Access Time (read from/ write to memory)– 50-75 nanoseconds (1 nsec. = 0.000000001 sec.)50-75 nanoseconds (1 nsec. = 0.000000001 sec.)

• RAM isRAM is– volatile (can only store when power is on)volatile (can only store when power is on)– relatively expensiverelatively expensive



Operations on Memory Operations on Memory • Fetch (address):Fetch (address):

– Fetch a copy of the content of memory cell with the specified Fetch a copy of the content of memory cell with the specified address.address.

– Non-destructive, copies value in memory cell.Non-destructive, copies value in memory cell.

• Store (address, value):Store (address, value):– Store the specified value into the memory cell specified by address.Store the specified value into the memory cell specified by address.– Destructive, overwrites the previous value of the memory cell.Destructive, overwrites the previous value of the memory cell.

• The memory system is interfaced via:The memory system is interfaced via:– Memory Address Register (MAR)Memory Address Register (MAR)– Memory Data Register (MDR)Memory Data Register (MDR)– Fetch/Store signalFetch/Store signal



Structure of the Memory SubsystemStructure of the Memory Subsystem

• Fetch(address)Fetch(address)– Load address into MAR.Load address into MAR.– Decode the address in MAR.Decode the address in MAR.– Copy the content of memory cell with Copy the content of memory cell with

specified address into MDR.specified address into MDR.

• Store(address, value)Store(address, value)– Load the address into MAR.Load the address into MAR.– Load the value into MDR.Load the value into MDR.– Decode the address in MARDecode the address in MAR– Copy the content of MDR into memory Copy the content of MDR into memory

cell with the specified address.cell with the specified address.

MAR MDR

...

Memorydecodercircuit

Fetch/Storecontroller

F/S



Input/Output SubsystemInput/Output Subsystem• Handles devices that allow the computer system to:Handles devices that allow the computer system to:

– Communicate and interact with the outside worldCommunicate and interact with the outside world• Screen, keyboard, printer, ...Screen, keyboard, printer, ...

– Store information (mass-storage) Store information (mass-storage) • Hard-drives, floppies, CD, tapes, …Hard-drives, floppies, CD, tapes, …

• Mass-Storage Device Access Methods:Mass-Storage Device Access Methods:– Direct Access Storage Devices (DASDs)Direct Access Storage Devices (DASDs)

• Hard-drives, floppy-disks, CD-ROMs, ...Hard-drives, floppy-disks, CD-ROMs, ...

– Sequential Access Storage Devices (SASDs)Sequential Access Storage Devices (SASDs)• Tapes (for example, used as backup devices)Tapes (for example, used as backup devices)



I/O ControllersI/O Controllers

• Speed of I/O devices is slow compared to RAMSpeed of I/O devices is slow compared to RAM– RAM ~ 50 nsec.RAM ~ 50 nsec.– Hard-Drive ~ 10msec. = (10,000,000 nsec)Hard-Drive ~ 10msec. = (10,000,000 nsec)

• Solution: Solution: – I/O Controller, a special purpose processor:I/O Controller, a special purpose processor:

• Has a small memory buffer, and a control logic to control I/O Has a small memory buffer, and a control logic to control I/O device (e.g. move disk arm).device (e.g. move disk arm).

• Sends an interrupt signal to CPU when done read/write.Sends an interrupt signal to CPU when done read/write.– Data transferred between RAM and memory buffer.Data transferred between RAM and memory buffer.– Processor free to do something else while I/O controller Processor free to do something else while I/O controller

reads/writes data from/to device into I/O buffer.reads/writes data from/to device into I/O buffer.



I/O controller

Structure of the I/O SubsystemStructure of the I/O Subsystem

I/O Buffer

Control/Logic

I/O device

Data from/to memoryInterrupt signal (to processor)



The ALU SubsystemThe ALU Subsystem

• The ALU (Arithmetic/Logic Unit) performsThe ALU (Arithmetic/Logic Unit) performs– mathematical operations (+, -, x, /, …)mathematical operations (+, -, x, /, …)– logic operations (=, <, >, and, or, not, ...)logic operations (=, <, >, and, or, not, ...)

• In today's computers integrated into the CPUIn today's computers integrated into the CPU• Consists of:Consists of:

– Circuits to do the arithmetic/logic operations. Circuits to do the arithmetic/logic operations. – Registers (fast storage units) to store intermediate Registers (fast storage units) to store intermediate

computational results.computational results.– Bus that connects the two.Bus that connects the two.



Structure of the ALUStructure of the ALU• Registers:Registers:

– Very fast local memory cells, that Very fast local memory cells, that store operands of operations and store operands of operations and intermediate results.intermediate results.

– CCRCCR (condition code register), a (condition code register), a special purpose register that stores special purpose register that stores the result of <, = , > operationsthe result of <, = , > operations

• ALU circuitry:ALU circuitry:– Contains an array of circuits to do Contains an array of circuits to do

mathematical/logic operations.mathematical/logic operations.

• Bus:Bus:– Data path interconnecting the Data path interconnecting the

registers to the ALU circuitry.registers to the ALU circuitry.

ALU circuitry

GT EQ LT

R0

R1

R2

Rn



The Control UnitThe Control Unit• Program is stored in memory Program is stored in memory

– as machine language instructions, in binaryas machine language instructions, in binary

• The task of the The task of the control unitcontrol unit is to execute programs is to execute programs by repeatedly:by repeatedly:– FetchFetch from memory the next instruction to be executed. from memory the next instruction to be executed.– DecodeDecode it, that is, determine what is to be done. it, that is, determine what is to be done.– ExecuteExecute it by issuing the appropriate signals to the it by issuing the appropriate signals to the

ALU, memory, and I/O subsystems.ALU, memory, and I/O subsystems.– Continues until the HALT instructionContinues until the HALT instruction



Machine Language InstructionsMachine Language Instructions

• A machine language instruction consists of:A machine language instruction consists of:– Operation codeOperation code, telling which operation to perform, telling which operation to perform– Address field(s)Address field(s), telling the memory addresses of the , telling the memory addresses of the

values on which the operation works.values on which the operation works.

• Example: ADD X, Y Example: ADD X, Y (Add content of memory locations X (Add content of memory locations X and Y, and store back in memory location Y).and Y, and store back in memory location Y).

• Assume: opcode for ADD is 9, and addresses X=99, Y=100Assume: opcode for ADD is 9, and addresses X=99, Y=100

00001001 0000000001100011 0000000001100100

Opcode (8 bits)Opcode (8 bits) Address 1 (16 bits)Address 1 (16 bits) Address 2 (16 bits)Address 2 (16 bits)



Instruction Set DesignInstruction Set Design

• Two different approaches:Two different approaches:– Reduced Instruction Set Computers (RISC)Reduced Instruction Set Computers (RISC)

• Instruction set as small and simple as possible.Instruction set as small and simple as possible.• Minimizes amount of circuitry --> faster computersMinimizes amount of circuitry --> faster computers

– Complex Instruction Set Computers (CISC)Complex Instruction Set Computers (CISC)• More instructions, many very complexMore instructions, many very complex• Each instruction can do more work, but require more Each instruction can do more work, but require more

circuitry.circuitry.



Typical Machine InstructionsTypical Machine Instructions

• Notation:Notation:– We use X, Y, Z to denote RAM cellsWe use X, Y, Z to denote RAM cells– Assume only one register R (for simplicity)Assume only one register R (for simplicity)– Use English-like descriptions (should be binary)Use English-like descriptions (should be binary)

• Data Transfer InstructionsData Transfer Instructions– LOAD LOAD X X Load content of memory location X to RLoad content of memory location X to R

– STORE XSTORE X Load content of R to memory location XLoad content of R to memory location X

– MOVE MOVE X, YX, Y Copy content of memory location X to loc. YCopy content of memory location X to loc. Y(not absolutely necessary)(not absolutely necessary)



Machine Instructions (cont.) Machine Instructions (cont.) • ArithmeticArithmetic

– ADD X, Y, ZADD X, Y, Z CON(Z) = CON(X) + CON(Y)CON(Z) = CON(X) + CON(Y)– ADD X, YADD X, Y CON(Y) = CON(X) + CON(Y)CON(Y) = CON(X) + CON(Y)– ADD XADD X R = CON(X) + RR = CON(X) + R– similar instructions for other operators, e.g. SUBTR,OR, ...similar instructions for other operators, e.g. SUBTR,OR, ...

• CompareCompare– COMPARE X, YCOMPARE X, Y

Compare the content of memory cell X to the content of memory Compare the content of memory cell X to the content of memory cell Y and set the condition codes (CCR) accordingly.cell Y and set the condition codes (CCR) accordingly.

– E.g. E.g. If CON(X) = R then set EQ=1, GT=0, LT=0If CON(X) = R then set EQ=1, GT=0, LT=0



Machine Instructions (cont.)Machine Instructions (cont.)

• BranchBranch– JUMP XJUMP X Load next instruction from memory loc. XLoad next instruction from memory loc. X

– JUMPGT XJUMPGT X Load next instruction from memory loc. X Load next instruction from memory loc. X only if GT flag in CCR is set, otherwise load only if GT flag in CCR is set, otherwise load statement from next sequence loc. as statement from next sequence loc. as usual.usual.

• JUMPEQ, JUMPLT, JUMPGE, JUMPLE,JUMPNEQJUMPEQ, JUMPLT, JUMPGE, JUMPLE,JUMPNEQ

• ControlControl– HALTHALT Stop program execution.Stop program execution.



ExampleExample

• Pseudo-code: Pseudo-code: Set A to B + CSet A to B + C• Assuming variable:Assuming variable:

– A stored in memory cell 100, B stored in memory cell A stored in memory cell 100, B stored in memory cell 150, C stored in memory cell 151150, C stored in memory cell 151

• Machine language (really in binary)Machine language (really in binary)– LOAD 150LOAD 150– ADDADD 151151– STORE 100STORE 100– oror– (ADD(ADD 150, 151, 100)150, 151, 100)



Structure of the Control UnitStructure of the Control Unit• PC (Program Counter):PC (Program Counter):

– stores the address of next instruction to fetchstores the address of next instruction to fetch• IR (Instruction Register):IR (Instruction Register):

– stores the instruction fetched from memorystores the instruction fetched from memory• Instruction Decoder:Instruction Decoder:

– Decodes instruction and activates necessary circuitryDecodes instruction and activates necessary circuitry

Instruction Decoder

IR

+1

PC



von Neumannvon Neumann

ArchitectureArchitecture

von Neumannvon Neumann

ArchitectureArchitecture



How does this all work together?How does this all work together?

• Program Execution:Program Execution:– PC is set to the address where the first program PC is set to the address where the first program

instruction is stored in memory.instruction is stored in memory.– Repeat until HALT instruction or fatal errorRepeat until HALT instruction or fatal error

Fetch instructionFetch instruction

Decode instructionDecode instruction

Execute instructionExecute instruction

End of loopEnd of loop



Program Execution (cont.)Program Execution (cont.)

• Fetch phaseFetch phase– PC --> MARPC --> MAR (put address in PC into MAR)(put address in PC into MAR)– Fetch signalFetch signal (signal memory to fetch value into MDR)(signal memory to fetch value into MDR)– MDR --> IRMDR --> IR (move value to Instruction Register)(move value to Instruction Register)– PC + 1 --> PC PC + 1 --> PC (Increase address in program counter)(Increase address in program counter)

• Decode PhaseDecode Phase– IR -> Instruction decoder IR -> Instruction decoder (decode instruction in IR)(decode instruction in IR)– Instruction decoder will then generate the signals to Instruction decoder will then generate the signals to

activate the circuitry to carry out the instructionactivate the circuitry to carry out the instruction25SYED ZARYAB HUSSAIN


Program Execution (cont.)Program Execution (cont.)

• Execute Phase Execute Phase – Differs from one instruction to the next.Differs from one instruction to the next.

• Example:Example:– LOAD X (load value in addr. X into register)LOAD X (load value in addr. X into register)

• IR_address -> MARIR_address -> MAR• Fetch signalFetch signal• MDR --> RMDR --> R

– ADD X ADD X • left as an exerciseleft as an exercise



Instruction Set for Our Von Neumann MachineInstruction Set for Our Von Neumann MachineOpcodeOpcode OperationOperation MeaningMeaning

0000 LOAD X CON(X) --> R0001 STORE X R --> CON(X)0010 CLEAR X 0 --> CON(X)0011 ADD X R + CON(X) --> R0100 INCREMENT X CON(X) + 1 --> CON(X)0101 SUBTRACT X R - CON(X) --> R0101 DECREMENT X CON(X) - 1 --> CON(X)

0111COMPARE X If CON(X) > R then GT = 1 else 0

If CON(X) = R then EQ = 1 else 0If CON(X) < R then LT = 1 else 0

1000 JUMP X Get next instruction from memory location X1001 JUMPGT X Get next instruction from memory loc. X if GT=1... JUMPxx X xx = LT / EQ / NEQ1101 IN X Input an integer value and store in X1110 OUT X Output, in decimal notation, content of mem. loc. X1111 HALT Stop program execution


Von neumann architecture

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