BRD-PCIem-15-IO USER’S MANUAL

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P.IVA 10190271006 Sede: Via Rocca di Papa, 21 00179 Roma

BRD-PCIem-15-IO User’s Manual

Numero Revisione Pagina

100801UM B.1 1

Mod. 7.3/8 Rev. 1 del 11/01/2011

Questo documento è di proprietà GEB Enterprise S.r.l. Il suo contenuto, intero o in parte, non può essere copiato, utilizzato o divulgato a terzi senza autorizzazione scritta della GEB Enterprise S.r.l. General Electronics Business S.r.l.

GEB Enterprise S.r.l. General Electronics Business, Via Rocca di Papa, 21 00179 Roma. Italia.

BRD-PCIem-15-IO

USER’S MANUAL

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Revisions History

Rev. Date Description

A 02/04/2012 Draft V.D.

B 17/10/2012 Emission, aligned spec. revision to pcb revision, added connectors and cables specifications

L.G.

B.1 03/07/2015 Added EP4CGX30 Fpga L.G

Data Emissione

03/07/2015 Resp. PRG

03/07/2015 Resp. RSQ

03/07/2015

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CONTENTS

1. INTRODUCTION ------------------------------------------------------------------------------------------------------------------ 4

1.1 TECHNICAL FEATURES -------------------------------------------------------------------------------------------------------- 4

1.2 VOLTAGE LEVELS AND WORKING TEMPERATURES --------------------------------------------------------------- 5

2. GETTING STARTED ------------------------------------------------------------------------------------------------------------- 6

3. BLOCK DIAGRAM --------------------------------------------------------------------------------------------------------------- 7

4. CYCLONE IV FPGA -------------------------------------------------------------------------------------------------------------- 7

5. CLOCKING AND RESET ------------------------------------------------------------------------------------------------------- 8

6. I/O CONNECTIONS -------------------------------------------------------------------------------------------------------------- 8

6.1 PCI EXPRESS CONNECTOR --------------------------------------------------------------------------------------------------------- 9

6.2 J1 CONNECTOR --------------------------------------------------------------------------------------------------------------------- 10

6.3 J2 CONNECTOR --------------------------------------------------------------------------------------------------------------------- 11

7. PCI EXPRESS DEMO PIO REFERENCE DESIGN --------------------------------------------------------------------- 12

7.1 RESOURCE ORGANIZATION AND PIN MAPPING --------------------------------------------------------------------------------- 12

7.2 SOFTWARE ACCESS ---------------------------------------------------------------------------------------------------------------- 14

7.3 GEB ENTERPRISE DEMO APPLICATION ----------------------------------------------------------------------------------------- 15

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1. INTRODUCTION

The BRD-PCIem-15-IO is a Cyclone IV development board for PCI-Express applications, providing 52 general purpose I/Os in a small form factor.

All FPGA power management, distribution and decoupling, fine pitch BGA package connection, multilayer PCB manufacturing, double side PCB mounting and testing requirements are met by PCIe Mini board.

Figure 1: BRD-PCIem-15-IO board top view.

One programming interface port, on the board support in-system programming (ISP), and using Altera Byte Blaster and JTAG programming and testing, is available as well.

The hardware design can be easily implemented using SOPC builder Altera tools, VHDL language, or a combination of them. Jungo WinDriver tool fully supports Altera PCIe easy driver development under various Operating Systems such as Microsoft Windows, Linux, or specific RT/OS.

The 50 mills header connectors allows to easily interface user boards by using a flat cable.

1.1 TECHNICAL FEATURES

• Altera Cyclone IV FPGA, EP4CGX15F14C7N (14,400 LE, 540Kbits Ram, 3 PLLs) or EP4CGX30BF14C6N (29440LE, 1080Kbits RAM, 4xPLLs, 80xMultiplyer)

• Altera EPCS16 16 Mbits configuration device, with ISP (In System Programming) using Altera USB Blaster

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• Single 3.3V power supply voltage via PCI Express

• 52 general purpose I/O pins, 3.3V LVTTL compliant, each one having independent sense, drive, bi-directional, and tri-state capabilities

• Two I/O connectors, 34+26 pins, dual rows, 50 mills header connectors (Samtec FTS series)

• JTAG/IEEE 1149.1 boundary-scan standard full-compatibility

• 25 MHz on-board oscillator

• Power on monitor and reset circuitry

• PCIe Mini connector

• PCI Express Mini Card Electromechanical Specification Revision 1.2 compliance (30mm x 51mm x 4,85mm, Double-sided)

• Optional 2 MBytes add-on module

• Peripheral to host wake-up support

1.2 VOLTAGE LEVELS AND WORKING TEMPERATURES

The following table reports power supply and temperature values of the BRD-PCIem-15-IO board:

Table 1: Voltage levels and working temperatures.

Digital I/O Vol=0.4V max., Voh=2.4V min., Vil=0.8V max., Vih=2.0V min.

Power supply (current) 3.3V+/- 5% (0.25A Typical, 0.6A Max)1

Operating Temperature Range 0°C/+70°C Commercial Temp. Range, -40°C/+85°C Industrial Temp. Range2

Storage Temperature Range -40/+150°C

1 The current value depends from the configuration file loaded inside FPGA. The typical values was measured on typical application (100MHz system clock, 50% resource usage, 20% I/O switching at 10MHz). Maximum value was estimated using Altera tolls in many large and fast design. The maximum current values allowed depends also from the thermal resistance of the package and from the operating temperature.

2 The operative temperatures assumes an FPGA Tja=15°C. Tja depends from FPGA power dissipation. Available on request.

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2. GETTING STARTED

Plug the BRD-PCIem-15-IO board in a Mini PCIe slot on the motherboard, but be sure to power down the motherboard before performing this operation. A PCIe application is already programmed in the configuration device (refer to section 7 for further details), another customer specific application can be programmed as well. After powering up the PC, the board should be recognized as a PCI Express device and registered.

To program the EPCS16 configuration device on the BRD-PCIem-15-IO board, a JTAG indirect programming file (JIC) has to be used. The SOF file can be converted into a JIC file in the “File -> Convert programming file” menu in Quartus II.

Connect the Altera USB Blaster USB port to the PC, and the programming connector to the J2 connector of the programming adapter (GEB Enterprise BRD-MBBA-1), making sure that pin 1 of the J2 connector matches with pin 1 of the programming connector of the Altera USB Blaster. Then connect the P2 connector of the BRD-MBBA-1 to the P3 connector of the BRD-PCIem-15-IO board: refer to Figure 2 to locate the P3 connector pin 1 on the board, and be sure it is connected to the BRD-MBBA-1 P2 connector pin 1.

Figure 2: P3 connector location and pin 1.

Once all the connections are performed, the application can be programmed by means of the Quartus II Programmer: open the application, click on “Hardware Setup…” and be sure that the Altera USB Blaster programmer is selected. Then click on the “Auto Detect”

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button and wait the software to recognize the Cyclone IV FPGA. If not, check all the connections once again and retry.

When the FPGA is recognized, click on the “Add File…” button and select the JIC file. In the end, click on the “Start” button and wait for the programming to be completed.

3. BLOCK DIAGRAM

The following figure shows the block diagram of the BRD-PCIem-15-IO board:

Figure 3: Block diagram of the BRD-PCIem-15-IO board.

The diagram shows how the board provides an amount of 52 at 3V3 LVTTL digital I/Os by means of two Samtec connectors, one of which can be used to add 2 Mbytes of SRAM by means of an optional memory module by GEB Enterprise (refer to section 6.3 for further details).

4. Cyclone IV FPGA

The following table reports the technical features of Cyclone IV FPGA, EP4CGX15F14C7N and EP4CGX30BF14C6N, that can be hosted on the BRD-PCIem-15-IO board:

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Table 2: Technical features of the hosted Cyclone IV FPGA.

Fpga Type EP4CGX15 EP4CGX30

Logic Elements 14,400 29,440

M9K RAM blocks 60 120

Total RAM Bits 540 Kbits 1080 Kbits

PLLs 3 4

Multipliers Blocks - 80

Maximum user I/O pins 72 72

Package BGA169 BGA169

Speed Grades -6, -7, -8 -6, -7, -8

Fewe Support NONE

5. CLOCKING AND RESET

The BRD-PCIem-15-IO board provides a free running 25 MHz oscillator, which drives the FPGA directly. Moreover, an input user provided clock and a PLL output clock signals are available to the user via the J1 connector: refer to section 6.2 for further details.

A low-active reset signal is connected to the INIT_DONE pin of the FPGA (configured as output open drain), and it is normally high due to a pull-up. The user can provide an extra low-active reset signal via the J1 connector, as shown in section 6.2.

Table 3 summarizes the clocking and reset scheme just described.

Table 3: On-board clock and reset signals summary.

Signal name Description FPGA location

REF_CLK On-board oscillator 25 MHz clock signal A10

FPGA_RSTn FPGA low-active reset signal G13

6. I/O CONNECTIONS

In addition to the PCI Express connector, the BRD-PCIem-15-IO development board provides two general purpose I/O connectors for user purposes, like for example LEDs, switches, ASSPs, and so on.

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6.1 PCI Express connector

The following table shows the connection between the Cyclone IV FPGA and the PCI Express P1 connector:

Table 4: PCI Express connector pin function and mapping.

Function FPGA Pin number Pin number FPGA Function

PCI_WAKE - 1 2 - +3_3V

3 4 - GND

5 6

CLKREQN - 7 8

GND - 9 10

PCI_REFCLKN J7 11 12

PCI_REFCLKP J6 13 14

GND - 15 16

17 18 - GND

19 20

GND - 21 22 H13 L_RESET#

PCI_TX0N G1 23 24

PCI_TX0P G2 25 26 - GND

GND - 27 28

GND - 29 30

PCI_RX0N J1 31 32

PCI_RX0P J2 33 34 - GND

GND - 35 36

37 38

39 40 - GND

41 42

43 44

45 46 - LED_WPAN

47 48

49 50 - GND

51 52 - +3V3

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6.2 J1 connector

Figure 4 shows the J1 connector with pin numbers and signals:

Figure 4: J1 connector.

As it can be seen, 20 general purpose I/O pins are provided on the J1 connector. Moreover, a GND signal and 5 further specific signals are provided. These signals are described in Table 5:

Table 5: J1 connector specific signals description.

Signal name Description

PCI_WAKE PCIe link reactivation signal (WAKE#)

OSC On-board oscillator 25 MHz clock signal

CLKOUT User provided clock signal

CLKIN Dedicated PLL output signal

RSTn User provided low-active reset signal

The following table shows the mapping between the FPGA pin locations and the J1 connector pins number and function:

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Table 6: J1 connector pins function and mapping.


GND - 1 2 - PCI_WAKE

OSC - 3 4 PIN_F13 CLKOUT

CLKIN PIN_A8 5 6 PIN_E13 RSTn

IO18 PIN_B6 7 8 PIN_C11 IO19

IO16 PIN_C8 9 10 PIN_B8 IO17

IO14 PIN_G9 11 12 PIN_G10 IO15

IO12 PIN_F10 13 14 PIN_F11 IO13

IO10 PIN_K8 15 16 PIN_L4 IO11

IO8 PIN_N4 17 18 PIN_M4 IO9

IO6 PIN_L5 19 20 PIN_N5 IO7

IO4 PIN_A7 21 22 PIN_N6 IO5

IO2 PIN_N8 23 24 PIN_L7 IO3

IO0 PIN_N9 25 26 PIN_M9 IO1

6.3 J2 connector

Figure 5 shows the J2 connector with pin numbers and signals:

Figure 5: J2 connector.

As shown in the figure above, in addition to 32 general purpose I/O signals, a GND and a +3V3 signals are provided.

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The J2 connector can be also used to fit the optional GEB Enterprise PCIe-RAM board to provide the board with extra memory (2 Mbytes of SRAM).

Table 7 shows the mapping between the FPGA pin locations and the J2 connector pins number and function:

Table 7: J2 connector pin function and mapping.


IO51 PIN_A12 1 2 - +3V3

IO49 PIN_A13 3 4 PIN_B11 IO50

IO47 PIN_B13 5 6 PIN_D10 IO48

IO45 PIN_C12 7 8 PIN_A6 IO46

IO43 PIN_C13 9 10 PIN_ D11 IO44

IO41 PIN_D12 11 12 PIN_E10 IO42

IO39 PIN_D13 13 14 PIN_C6 IO40

IO37 PIN_H12 15 16 PIN_F9 IO38

IO35 PIN_J13 17 18 PIN_K9 IO36

IO33 PIN_K13 19 20 PIN_L9 IO34

IO31 PIN_K12 21 22 PIN_H10 IO32

IO29 PIN_L13 23 24 PIN_K10 IO30

IO27 PIN_M13 25 26 PIN_K11 IO28

IO25 PIN_N13 27 28 PIN_L11 IO26

IO23 PIN_N12 29 30 PIN_M11 IO24

IO21 PIN_N11 31 32 PIN_L12 IO22

IO20 PIN_N10 33 34 - GND

7. PCI EXPRESS DEMO PIO REFERENCE DESIGN

The BRD-PCIem-15-IO board is provided with a sample reference design which is already programmed into the configuration device, and a simple user interface software, which can be used to easily approach to PCI Express standard.

7.1 Resource organization and pin mapping

The reference design makes 7 PIOs available to the user to be configured singularly (via PCI Express) as input or output for each bit. The first 6 PIOs are 8 bits while the 7th is 4

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bits wide, for a total amount of 52 I/Os. Table 8 shows how resources are organized onto the board:

Table 8: PIO Reference Design resource organization and pin mapping.

BAR0

0x0000

PIO_0

7 6 5 4 3 2 1 0

PIN_N5 PIN_L5 PIN_N6 PIN_A7 PIN_L7 PIN_N8 PIN_M9 PIN_N9

J1_20 J1_19 J1_22 J1_21 J1_24 J1_23 J1_26 J1_25

0x0100

PIO_1

7 6 5 4 3 2 1 0

PIN_G10 PIN_G9 PIN_F11 PIN_F10 PIN_L4 PIN_K8 PIN_M4 PIN_N4

J1_12 J1_11 J1_14 J1_13 J1_16 J1_15 J1_18 J1_17

0x0200

PIO_2

7 6 5 4 3 2 1 0

PIN_N12 PIN_L12 PIN_N11 PIN_N10 PIN_C11 PIN_B6 PIN_B8 PIN_C8

J2_29 J2_32 J2_31 J2_33 J1_8 J1_7 J1_10 J1_9

0x0300

PIO_3

7 6 5 4 3 2 1 0

PIN_K12 PIN_K10 PIN_L13 PIN_K11 PIN_M13 PIN_L11 PIN_N13 PIN_M11

J2_21 J2_24 J2_23 J2_26 J2_25 J2_28 J2_27 J2_30

0x0400

PIO_4

7 6 5 4 3 2 1 0

PIN_D13 PIN_F9 PIN_H12 PIN_K9 PIN_J13 PIN_L9 PIN_K13 PIN_H10

J2_13 J2_16 J2_15 J2_18 J2_17 J2_20 J2_19 J2_22

0x0500

PIO_5

7 6 5 4 3 2 1 0

PIN_B13 PIN_A6 PIN_C12 PIN_D11 PIN_C13 PIN_D12 PIN_E10 PIN_C6

J2_5 J2_8 J2_7 J2_10 J2_9 J2_11 J2_12 J2_14

0x0600

PIO_6

3 2 1 0

PIN_A12 PIN_B11 PIN_A13 PIN_D10

J2_1 J2_4 J2_3 J2_6

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As it can be seen, all PIOs are mapped into BAR0, and their offsets within the BAR are spaced by 256 memory locations, from 0x0000 to 0x0600. The table also shows, for each I/O bit, its mapping on FPGA pins and on J1 and J2 connectors.

7.2 Software access

User software can access the PIOs by specifying the BAR and the base address offsets. In addition to these info, the user also has to provide the offset within the particular PIO memory range.

The PIO Reference Design by GEB Enterprise makes use of the Altera PIO Core, whose particular register map is documented into the “Embedded Peripherals IP User Guide”, which is available in the documentation section of the Altera website. Altera PIO Core functional description and software programming model can be found in this document, too.

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7.3 GEB Enterprise demo application

GEB Enterprise provides a simple demo application with which it is possible to configure the PIOs pins, and to read their current values if inputs, or write them if outputs.

When the demo is run, it tries to locate the BRD-PCIem-15-IO board on the PCI Express bus: if it can’t, an error message is returned. User has to be sure to plug the board into the motherboard and to register it before using it.

If the card is located, the demo tries to open it (that is to acquire its resources). It can happen that another application is using the board when trying to run the demo: in this case another error message is shown, asking to check whether the card is already used.

Figure 6 shows the GUI of this application when it succeeds in locating and opening the board:

Figure 6: Demo application GUI

In the top left, there’s a control with which it is possible to select the particular PIO to configure. Just below, the text box shows the current value of the data register of the selected PIO. The value can be refreshed by clicking on the “Read” button, or can be changed and then written into the register by the “Write” button.

Furthermore, each bit can be configured as input or output, starting from the ON or OFF position of the switches: when configured as input, the corresponding LED above shows the bit value of the last read; when output, the LED can be clicked to set the corresponding bit to 1 when it is turned on, 0 when off. It is possible to notice that, each time a switch or a LED is clicked, the software automatically reads the new value of the data register and updates the GUI properly.

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In the end, at the bottom center, the “Exit” button allows the user to release the board resources and exit the application.

Table 9: Connectors specifications

Ref. Des

Connector Part Number Mates With Author

J1 Samtec FTS-113-01-F-DV-P

• Farnell 1930691

1


• Farnell 1931097

1


• Faenell 1930694 Samtec FFSD-13-D-XX.XX-01-D

• Silvestar

2


• Farnel 1931100 Samtec FFSD-17-D-XX.XX-01-D

• Silvestar

2

Notes:

1. Referred to 100801A2/A4 PCI Express Mini I/O Board (Standard: I/O connectors Match Samtech FFSD series)

2. Referred to 100801A1/A3 PCI Express Mini I/O Board (Non Standard I/O connectors Match Samtech CLP series)

BRD-PCIem-15-IO USER’S MANUAL

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