Low Power Design for Integrated Energy Harvesting...

Low Power Design for Integrated EnergyHarvesting Systems

Von der Fakultät für Elektrotechnik und Informationstechnik derRheinisch-Westfälischen Technischen Hochschule Aachen zur

Erlangung des akademischen Grades eines Doktors derIngenieurwissenschaften genehmigte Dissertation

vorgelegt von

M.Sc.Durgham Al-Shebanee

aus Muthanna, Irak

BerichterProf. Dr.-Ing. Stefan Heinen

Prof. Dr. sc. techn. Renato Negra

Tag der mündlichen Prüfung: 08.07.2016

Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfügbar.

Acknowledgment

I would like to express my sincere gratitude to my advisor Prof. Dr.-Ing. StefanHeinen to give me the opportunity to do this research. I want to thank him forhis continuous support and guidance for more than four years ago in achievingthe design of energy harvesting systems from the beginning until the final phases.I have gained from Prof. Heinen the required experience to design various CMOSintegrated circuits in different levels. Achieving this thesis was only possible dueto his advice and instructions.I would like to thank Dr.-Ing. Ralf Wunderlich for his continuous follow upto my work and his valuable guidance in many details regarding my research.Especially, with regard to the design of low input voltage boost converter.I would like to thank Prof. Dr. sc. techn. Renato Negra for valuable feedbackand helpful discussions.I want to thank Markus Scholl and Ye Zhang for their efforts to carry out the finaltechnical steps required to submit the tape-out of (RWTO) for manufacturing.Thanks for Rene’ Spenke, Patrick Vliex and Julian Scheier who participate inthe work through their bachelor and master projects.I would like to thank recent and former office mates: Soheil Aghaie, Björn Thiel,Aytac Atac, Lei Liao to make the work atmosphere really friendly.Thanks for Iyappan Subbiah and Ahmed Aref for their proofreading and cor-recting my thesis.I would like to express my sincere appreciation to all my colleagues in theinstitute of integrated analog circuits and RF systems. I have got from thema peerless support during the last years. I want to thank them for their sin-cerity to cooperate with me. They made my experiment in Germany is wonderful.

Special thanks to my wife Shamim for her sacrifice during the past years. Peerlesseffort, patience, love and believing in me, this is the least that I can describewhat she did for me.

Thanks to my kids Ruqia and Hayder.

Thanks to my parents and brothers.

Thanks to my friends.

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To my my parents, Ayad Al-Shebanee and Layla YousifTo my wife, ShamimTo my Kids, Ruqia and Hayder

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Contents

List of Figures xi

List of Tables xv

List of Listings xvii

List of Abbreviations xvii

List of Symbols xix

1 Introduction 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Aim of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Fundamentals of Conversion Circuits in Energy Harvesting Systems 52.1 General Architecture of Harvesting System . . . . . . . . . . . . 52.2 Methods of Energy Harvesters . . . . . . . . . . . . . . . . . . . . 5

2.2.1 RF Energy Harvesting . . . . . . . . . . . . . . . . . . . 62.2.2 Thermal Energy Harvesting . . . . . . . . . . . . . . . . 112.2.3 Piezoelectric Energy Harvesting . . . . . . . . . . . . . . . 132.2.4 Solar Energy Harvesting . . . . . . . . . . . . . . . . . . . 16

2.3 Low Voltage Low Power CMOS Circuits . . . . . . . . . . . . . . 172.3.1 Electrical Characteristics of CMOS Transistor in Sub-

threshold Region . . . . . . . . . . . . . . . . . . . . . . . 172.3.2 Low Voltage Current Reference Circuit . . . . . . . . . . 192.3.3 Reference Voltage Circuit with Low Supply Voltage . . . 232.3.4 Low Voltage Amplifier Circuits . . . . . . . . . . . . . . . 25

2.4 Power Managements Circuit . . . . . . . . . . . . . . . . . . . . . 272.4.1 Rectifier conversion Circuits . . . . . . . . . . . . . . . . 272.4.2 DC-DC Up-Conversion Circuits . . . . . . . . . . . . . . 352.4.3 Power Losses in Conversion Circuits . . . . . . . . . . . . 41

2.5 The Proposed System Aspects . . . . . . . . . . . . . . . . . . . 432.5.1 Harvested Power Conditions and Targeted Energy Sources 432.5.2 Sensitivity Enhancement . . . . . . . . . . . . . . . . . . . 44

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3 RF Energy Harvesting System using Low-Power Charge Pump 473.1 Circuit Model of RF Energy Harvester . . . . . . . . . . . . . . 473.2 Passive Amplification of Input RF Voltage . . . . . . . . . . . . . 48

3.2.1 High Radiation Resistance . . . . . . . . . . . . . . . . . . 483.2.2 Input Impedance With High Quality . . . . . . . . . . . 49

3.3 Proposed CMOS RF Energy Harvesting System . . . . . . . . . . 513.4 Low Power RF Rectifier . . . . . . . . . . . . . . . . . . . . . . . 53

3.4.1 Design of Differential Cross-Coupled RF Rectifier . . . . . 543.5 Low-Power Charge Pump . . . . . . . . . . . . . . . . . . . . . . 56

3.5.1 Design of Cross-Coupled Charge Pump . . . . . . . . . . 563.5.2 Driving Clock Generator . . . . . . . . . . . . . . . . . . 59

3.6 System Implementation . . . . . . . . . . . . . . . . . . . . . . . 613.7 Experimental Results Using RF Power Source . . . . . . . . . . 64

3.7.1 Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . 643.7.2 Measurement Results of Charge Pump . . . . . . . . . . . 643.7.3 Sensitivity Measurements of RF Energy Harvester . . . . 65

3.8 Design of PCB Antenna for RF energy harvesting . . . . . . . . . 693.8.1 Antenna Characteristics . . . . . . . . . . . . . . . . . . . 693.8.2 Antenna Types . . . . . . . . . . . . . . . . . . . . . . . . 713.8.3 Dipole Antenna Implementation . . . . . . . . . . . . . . 73

3.9 Experimental Results Using The Dipole Antenna . . . . . . . . . 743.9.1 Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . 773.9.2 Measurements of The S11 Parameters . . . . . . . . . . . 773.9.3 Sensitivity Measurement Using Dipole Antenna . . . . . . 77

4 Low Input Voltage Boost Converter For Thermal Energy Harvesting 814.1 Thermoelectric Generator . . . . . . . . . . . . . . . . . . . . . . 81

4.1.1 Thermal and Electrical Model of the TEG . . . . . . . . . 824.1.2 Choosing TEG Module For Thermal Energy Harvesting . 83

4.2 Proposed DC-DC UP-Converter for Thermal Energy Harvester . 844.2.1 Transformer Reuse Self Start-Up Technique . . . . . . . . 86

4.3 Design of Self Start-UP Oscillator . . . . . . . . . . . . . . . . . 874.3.1 Self Start-Up Techniques . . . . . . . . . . . . . . . . . . 874.3.2 LC Based Start-Up Oscillator . . . . . . . . . . . . . . . 884.3.3 Transformer Based Start-Up Oscillator . . . . . . . . . . 894.3.4 Negative Voltage Rectifier . . . . . . . . . . . . . . . . . 92

4.4 Design of Low Power Inductor Based Boost Circuit . . . . . . . 944.4.1 Ring Oscillator Circuit . . . . . . . . . . . . . . . . . . . . 944.4.2 Pulse Signal Generation . . . . . . . . . . . . . . . . . . . 95

4.5 Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974.5.1 Low Power Comparator Circuit . . . . . . . . . . . . . . 974.5.2 Driving Multiplexer Circuit . . . . . . . . . . . . . . . . . 101

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4.5.3 Simulation Results of The Control Circuit . . . . . . . . . 1024.6 System Implementation . . . . . . . . . . . . . . . . . . . . . . . 1034.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.7.1 Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . 1084.7.2 Measurements of Minimum Start-Up Input Voltage . . . . 1094.7.3 Measurements of The Converter In The Inductor-Based

Boost phase . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5 Conclusions and Outlook 1135.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

[]

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List of Figures

2.1 Energy harvesting system. . . . . . . . . . . . . . . . . . . . . . . 62.2 RF power sources are everywhere. . . . . . . . . . . . . . . . . . 72.3 Floor plan (first floor) of the laboratory building showing the

locations of measurements of WLAN signal path loss. . . . . . . 92.4 Example of desktop scanning window by inSSIDer software [2]. . 92.5 Path losses of RF signal of WLAN router RF in open space. . . . 102.6 Path losses of RF signal of WLAN router RF across two walls. . 102.7 Thermal energy sources with thermoelectric generator TEG. . . . 122.8 The output electrical power of typical TEG with size of 30mm2. 132.9 Vibrational energy harvesting systems. . . . . . . . . . . . . . . . 152.10 Structure of photovoltaic arrays. . . . . . . . . . . . . . . . . . . 172.11 Structure of an N-channel CMOS transistor. . . . . . . . . . . . . 182.12 Basic supply independent current reference circuit. . . . . . . . . 202.13 Cascode current mirror with chain of transistors proposed instead

of Rseries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.14 Simulation results of Iout with supply voltage using NMOS tran-

sistors chain instead of large Rseries. . . . . . . . . . . . . . . . . 222.15 Low power circuit suggested to reduce the temperature influence

on Iout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.16 The impact of the suggested temperature adaptive current com-

pensating circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . 242.17 Reference voltage generation using the suggested current biasing

circuit in sec. 2.3.2. . . . . . . . . . . . . . . . . . . . . . . . . . 252.18 Low-power voltage reference circuit using NMOS with low Vgs. . 262.19 Reference voltage generation using reverse biased NMOS transis-

tors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.20 Implementations of inverter amplifier with low supply voltage. . 282.21 PMOS differential pair amplifier. . . . . . . . . . . . . . . . . . . 282.22 Voltage doubler circuit. . . . . . . . . . . . . . . . . . . . . . . . 292.23 Dickson RF voltage multiplier. . . . . . . . . . . . . . . . . . . . 302.24 Greinacher charge pump. . . . . . . . . . . . . . . . . . . . . . . 302.25 Output voltage and efficiency of single stage rectifier using HSMS2860

diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.26 Three-levels threshold voltage compensation method. . . . . . . . 322.27 Adaptive threshold-voltage compensation method. . . . . . . . . 33

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2.28 Elimination of the forward voltage Vth using cross connectiontechnique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.29 Multistage differential input cross connected rectifier. . . . . . . . 342.30 Basic structure of single stage charge pump circuit. . . . . . . . . 352.31 Multistage dickson charge circuit. . . . . . . . . . . . . . . . . . . 362.32 Three-stage charge pump with static switch biasing. . . . . . . . 372.33 Two-stage charge pump with dynamic switch biasing. . . . . . . 382.34 Multistage cross coupled charge pump. . . . . . . . . . . . . . . . 392.35 Magnetic-based DC-DC up-conversion circuit principle . . . . . . 402.36 Inductor voltage waveform during the switching time Ts. . . . . . 412.37 Magnetic based boost converter circuit and its parasitic elements. 422.38 Cycled power management strategy by micro-controller in low

power WSN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.1 Circuit model of RF energy harvesting system. . . . . . . . . . . 483.2 VA vs the radiation resistance for (Rr = Rrec). . . . . . . . . . . 493.3 Impact of high Xin on Vrec. . . . . . . . . . . . . . . . . . . . . . 503.4 Variation in voltage gain with frequency for fc = 850 MHz. . . . 513.5 The proposed CMOS integrated RF energy harvesting system. . 523.6 Equivalent circuits of pad and package connections including

parasitic components. . . . . . . . . . . . . . . . . . . . . . . . . 543.7 Total power efficiency vs received power at a frequency of 850MHz

and typical 50W RF power source. . . . . . . . . . . . . . . . . . 553.8 Output DC voltage at maximum output power vs received power

at a frequency of 850MHz and typical 50W RF power source. . . 563.9 Cross-coupled charge pump using reverse bulk biasing. . . . . . . 583.10 Reference voltage Vref1 vs Vrec,DC . . . . . . . . . . . . . . . . . . 603.11 Block diagram of the charge pump based DC-DC up-converter. . 613.12 Clock signal with peak-peak equal to Vrec,DC . . . . . . . . . . . . 623.13 Oscillation frequency stabilization with Vrec,DC . . . . . . . . . . . 623.14 Chip micro graph of the RF energy harvesting system within

a tape-out using UMC 0.13 um technology and total area of(1.6x1.6)mm2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.15 Layout of the proposed energy harvesting. . . . . . . . . . . . . 633.16 Matching network based on the charge-pump model coupled to

rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.17 Sensitivity measurements using RF4 PCB and RF source. . . . 663.18 Charge pump and sensitivity measurement setup. . . . . . . . . 673.19 Measurements of the output voltage and drawn current of the

charge pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.20 Measurement of S11 parameter using of Board1 with the extracted

matching network (Section. 3.7.1). . . . . . . . . . . . . . . . . . 68

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3.21 System sensitivity measurement with center frequency of 850MHz. 683.22 Measurements of frequency influence on the sensitivity. . . . . . . 693.23 Comparison of radiation pattern between isotropic emitter and

directional antenna. . . . . . . . . . . . . . . . . . . . . . . . . . 703.24 Typical structure of PCB patch antenna. . . . . . . . . . . . . . 723.25 PCB square loop antenna. . . . . . . . . . . . . . . . . . . . . . 723.26 Dipole antenna realizations. . . . . . . . . . . . . . . . . . . . . 733.27 Design of PCB dipole antenna. . . . . . . . . . . . . . . . . . . . 753.28 Main board measurement Board2 of RF energy harvesting system. 763.29 Dipole Antenna realization using FR4 substrate. . . . . . . . . . 763.30 Simulated and measured S11 parameter of dipole antenna. . . . 773.31 Measurements of RF energy harvester in Board2 at 1m distance

from the transmitter. . . . . . . . . . . . . . . . . . . . . . . . . 783.32 Measurements of RF energy harvester at a distance of 1m from

the transmitter and (Pt = 6.5 dBm). . . . . . . . . . . . . . . . . 793.33 Measurements of RF energy harvester using Board2 at 9.2m

distance from the transmitter. . . . . . . . . . . . . . . . . . . . 79

4.1 The Seebeck effect principle. . . . . . . . . . . . . . . . . . . . . 814.2 Thermal and electrical modeling of the thermal energy harvester. 834.3 The power delivered from the TEG to the load as a functions to

the input resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 854.4 The available DC voltage from the TEG to the load as a functions

to the input resistance. . . . . . . . . . . . . . . . . . . . . . . . 854.5 System operation phases. . . . . . . . . . . . . . . . . . . . . . . 874.6 Cross-coupled LC tank based self start up oscillator. . . . . . . . 884.7 Cross-coupled oscillator loaded with voltage multiplier circuit. . 904.8 Transformer based self start up oscillator. . . . . . . . . . . . . . 914.9 Simulation results of the self start up oscillator with Voc = 10 mV. 934.10 Negative voltage rectifier using PMOS transistors. . . . . . . . . 934.11 Driving circuit of the inductor based boost. . . . . . . . . . . . . 954.12 Clock signal generator circuit. . . . . . . . . . . . . . . . . . . . 964.13 Simulation results of the biased oscillator circuit for supply voltage

change with time. . . . . . . . . . . . . . . . . . . . . . . . . . . 964.14 Simulation results of the fs for supply voltage change with time. 974.15 Pulse signal generator circuit. . . . . . . . . . . . . . . . . . . . 984.16 The output signal of the high pass filter for an input clock signal

of 10 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.17 The pulse signal generated for input clock signal of 10 kHz. . . . 994.18 Bulk input differential amplifier given in [27]. . . . . . . . . . . . 1004.19 Amplifier circuit with differential signals generation circuits. . . 1014.20 Output stage of the comparator. . . . . . . . . . . . . . . . . . . 102

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4.21 The suggested multiplexer circuit to drive the switch Sboost. . . 1034.22 Block diagram of the proposed boost converter circuit. . . . . . 1044.23 The output voltage for an open circuit voltage of 30mV. . . . . 1044.24 The differential input signals to the amplifier circuit. . . . . . . 1054.25 The output signal of the differential amplifier circuit. . . . . . . 1054.26 The output signals of the comparator circuit. . . . . . . . . . . . 1054.27 The negative DC voltage generated from the negative voltage

rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064.28 The output signal of the driving multiplexer circuit. . . . . . . . 1064.29 Micro-graph of multiple block chip with a total area of 1.6 ×

1.6mm2 containing the boost converter system. . . . . . . . . . . 1074.30 Layout of the proposed low input-voltage boost circuit. . . . . . 1084.31 Test board of the CMOS boost converter. . . . . . . . . . . . . . 1094.32 The measurement test bench of the low input-voltage boost con-

verter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104.33 Measurement of start-up voltage of the converter connected to

the TEG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114.34 Measurements of output voltage of the converter. . . . . . . . . . 1114.35 Measurements results of output power and efficiency. . . . . . . . 112

5.1 Suggested RF energy harvesting system for future works. . . . . 117

xiv

List of Tables

2.1 Losses of walls inside buildings. . . . . . . . . . . . . . . . . . . . 82.2 Input frequency and acceleration of some common vibration

sources [33]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3 Producible power with various optical energy conditions [28, p.274]. 162.4 Conversion efficiency of photovoltaic junction according to the

used technology [28, p.275]. . . . . . . . . . . . . . . . . . . . . . 18

3.1 Additional RF multiplying stages vs charge pump . . . . . . . . 533.2 Characteristics of the substrate used for antenna fabrication. . . 74

4.1 Commercial Off-The-Shelf TEG modules with part numbers andmanufacturers [34]. . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.2 Characteristics of the current sense transformer used for the boostconverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.1 Performance comparison to the state-of-the-art of RF energyharvesting systems. . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.2 Performance comparison to the state-of-the-art of low input volt-age boost circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 116

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List of Abbreviations

AC Alternating Current

AC-DC AC to DC conversion

CMOS Complementary Metal-Oxide-Semiconductor

DC Direct Current

DC-DC DC to DC conversion

EM Electro-Magnetic

GSM Global System for Mobile Communications

IC Integrated Circuit

MIM Metal-Insulator-Metal

MPPT Maximum Power Point Tracking

MOSFET Metal Oxide Semicoductorc (MOS) Feild Effect Transistor (FET)

NMOS N-type Metal Oxide Semicoductorc (MOS) Feild Effect Transistor(FET)

PCB Printed Circuit Board

PMOS P-type Metal Oxide Semicoductorc (MOS) Feild Effect Transistor(FET)

RF Radio Frequency

RF-EH RF Energy Harvester

µC Microcontroller

(TE) Thermal Energy

TE-H Thermal Energy Harvesting

TEG Thermo-Eelectric Generator

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WLAN Wireless Local Area Network

WSN Wireless Sensor Network

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List of Symbols

Parameters

kf Number of penetrated floorskw Number of wall typeskwi Number for walls of ith typeLwi [dB] The loss for walls of ith typeLf [dB] The loss between adjacent floorsLo,dB [dB] The free space path loss at reference distance of 1mf [Hz] The frequency of the RF signalsc The speed of light4T [C] The temperature difference4TTEG [C] The actual temperature difference across the

TEG moduleTh [C] The temperature of the hot side of the TEG

moduleTc [C] The temperature of the cold side of the TEG

modulePTEG [W] The DC available power from the TEG moduley(t) The displacement of the system housing in vibrational

systemm The mass of the suspended seismic body in vibrational

systemY The displacement magnitude of input vibrations in

vibrational systemζe The electrical damping ratio in vibrational systemζm The mechanical damping ratio in vibrational systemω The input frequency in vibrational systemωn The natural frequency of spring mass systema The acceleration magnitude of input vibrations in

vibrational systemn The nonideality factor in CMOS transistorsVT The thermal voltageIo The residual drain current in saturation for Vg = Vs = 0Vth [V] The threshold voltage

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Parameters

Vtho [V] The threshold voltage when Vsb = 0γ The body effect coefficientΦ The Fermi potentialId [A] The drain currentµn [ cm2

V s ] The electron mobilityIout [A] The output current in current reference circuitIref [A] The reference current in current reference circuitVref [V] The reference voltage in voltage reference circuitIbias [A] The biasing currentgm The transconductance of the CMOS transistorsλCMOS Channel length modulationPin [W,dBm] Input powerILeakage [A] Leakage current in CMOS transistorsIdo [A] The drain current when (Vgs − Vth) = 0fs [Hz] The switching frequency of the boost converterVNdrop [V] The voltage drop across the NMOS transistorVPdrop [V] The voltage drop across the PMOS transistorN The number of stages in the charge pumpPdyn [W] The dynamic lossesPres,dc [W] The conduction losses due to the IL,averagePres,ac [W] The conduction losses due to the ∆ILηPCE [%] The power conversion efficiencyPoutDC [W] The DC output powerTs [s] The time period of the switching signal in the

boost converterZA Antenna impedanceRloss [W] Loss resistance of the antennaRr [W] Radiation resistance of the antennaXA Imaginary part of the antenna impedanceZin Input impedanceRin [W] Real part of the input impedanceXin Imaginary part of the input impedancePav Available power from the antennaXmatch The matching inductance componentAvmatch The gain in RF voltage by resonance

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Parameters

Q The quality factorfc [Hz] The center frequency of bandwidth of RF signalsIin,rms [A] The R.M.S. value of the input current to the

boost converterWp PMOS transistor widthWn NMOS transistor widthIload [A] The output load currentRvoltmeter [W] The voltmeter impedanceRs,meas [W] The series resistance in measurements of RF energy

harvesterRseries [W] The series resistance in reference circuitsS The radiation densityr [m] The distance from transmitter to the harvesterPEIRP The Effective Isotropic Radiation RF PowerGi The antenna gainPt [dBm] The transmitter RF powerD The antenna directivityηantenna The antenna efficiencyAe The effective aperture of antennaε The dielectric constant of the PCB substrateεeff The effective dielectric constant of the PCB

substrateWdipole The width of the copper trackdsubstrate The thickness of the PCB substrateLdipole The length of the dipole antennaαS [ V

K ] Seebeck coefficientk Number of thermocouples in the TEG moduleRc Thermal resistance of the heat sink on the cold

sideRh Thermal resistance of the heat sink on the hot

sideRth.TEG Thermal resistance of the TEG moduleRin,boost [W] The input resistance of the boost converterRs [W] The source resistance

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Parameters

fosc [Hz] The start up oscillation frequency of theboost converter

RL,esr [W] The equivalent series resistance of theinductor

Rp [W] The modeled parallel resistance of RL,esrRC,esr [W] The equivalent series resistance of the

capacitorCmv [F] The parasitic capacitance of the low

frequency voltage multiplierNprm The transformation ratio of the SMT transformerCp The parasitic capacitance of the CMOS

transistors in the start up oscillatorLsec [H] Inductance of the secondary winding of the

SMT transformerCse [F] The self capacitance of the secondary winding

of the SMT transformerRg The gate resistanceD1 The pulse width of the pulse signal in boost

converterRload [W] Load resistancePout [W] The DC output power

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Analog signals

Vds [V] The drain-source voltageVgs [V] The gate-source voltageVbias [V] The biasing voltageVref [V] The reference voltage in voltage reference

circuitVin [V] The DC input voltage to the DC-DC boost

converterVRF RF signal voltageVCLk Clock signalVL(t) The inductor voltageIC The capacitor currentIL The inductor current∆IL The ripple component in the inductor currentIL,average The average inductor current in the boost

converterVamp Amplitude of the RF sinusoidal signalVrec The RF input voltage to the rectifierVout [V] The DC output voltageVoc [V] The open circuit voltage of the TEG moduleVant The RF induced at antennaVrec,DC [V] The DC rectified voltage from rectifierVprm The primary voltage at the primary inductorVsec The secondary voltage at the secondary

inductorVosc The oscillation voltageVpulse The pulse signal of the boost converterVfilter The output signal of the high pass filterVcomp,1, Vcomp,2 The control signals of the boost converterVboost [V] The voltage required to drive the boost circuitsVout.div., Vref.low [V] The input differential signals of the comparatorVneg. [V] The output voltage of the negative voltage

rectifierVmux The output signal of the driving multiplexer

circuit

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Chapter 1

Introduction

1.1 Motivation

Wireless Sensor Network (WSN) are widely used in different applications nowa-days. These sensors are necessary for monitoring some important physical param-eters like temperature, humidity and mechanical stress etc. In the near future, itis expected that trillions of WSNs will be employed in various applications inorder to process tremendous amounts of data, which promote the human life toa better quality. Driving these wireless sensor circuits by regular power supplysuch as a battery limits the places in which these sensors can be installed.Energy harvesting gives the solution to operate the WSN nodes in various placesand environments. This is because battery-less electronics eliminate the needfor power wires, maintenance and labor cost required for battery replacementand toxic waste for environment. The energy harvesting is defined as a processby which the energy available from various sources is transformed to electri-cal power. This principle has recently attracted a considerable interest in theacademic and the industrial fields. The expected low power available from theharvester became usable because of the drastic reduction in power consumptionof electronic circuits in recent years.A variety of energy sources in the ambient environment can be utilized togenerate the electrical power. Such energy sources can be light, motion, radiofrequency (RF) radiation and thermal energy sources. Solar cells are one ofthe most widely used energy harvesting realizations. Here, the optical energy isutilized to generate the electrical power with wide range of sizes and power levels.The temperature difference in different applications is applied on the thermo-electric generator (TEG) module giving the electrical power as an example of thethermal energy harvesting. For a certain temperature difference, the generatedpower level is determined according to the size and physical characteristics of theTEG module used. The RF signals are exist with different frequencies while theradiation strength is related to the transmitted signal power. The ambient RFradiation in different frequencies can be captured by a receiving antenna givingan electrical signal. The vibration energy which is given by some mechanicalexcitations can be transformed into usable electrical power by the mechanicalenergy harvesting. Piezoelectric transducers are widely used for such purposes.

1

Chapter 1 Introduction

The output voltage given by the harvesting transducer is less than supply voltagelevel required for the typical sensor circuits. Therefore, voltage conversion circuitsare required to reach an acceptable output DC voltage. As the voltage givenby the micro harvesting generator is low, a high conversion ratio is needed.However, such high voltage conversion circuits are associated with high powerlosses contradicting with their use in low power applications. Consequently, lowpower conversion circuit designs are necessary to be suitable to the low powerproduced by the harvester.

1.2 Aim of the Thesis

The thesis concentrates on the energy harvesting systems within ultra lowpower range. The aim of the thesis is to recondition the harvested energy inorder to reach the requirements of the sensor circuits used in energy harvestingapplications. In addition to the low input power, more obstacles are expectedthat make the circuit design more challenging. Most of these obstacles are relatedto the nature of the energy source and the employed transducer such as the highfrequency RF input signal in RF energy harvesting and the quite low DC inputsignal in thermal energy harvesting. The main purpose of the suggested circuitdesigns is to overcome these constraints with strict low power budget. Moreover,it is important that economic solutions are preferable so that the harvestingsystems can be realized feasibly.

1.3 Thesis Structure

Chapter 2 starts with describing briefly the architecture of the energy harvestingsystem, where the power management circuit position in the system is illustrated.The circuit designs are based on the energy sources and the electrical signal pro-duced from the transducer. Therefore, the most known energy harvesting methodsare given including the related application and the power density expected inevery method. As mentioned in Section 1.2, the thesis focuses particularly onenergy harvesting systems within low power range. Therefore, the principles oflow-power low-voltage CMOS circuits are reviewed including the biasing circuits,reference generators and amplifiers. The voltage conversion circuits are explainedin detail with regard to both AC-DC rectifiers and DC-DC boost converters.Furthermore, the power losses associated with these circuits are demonstrated aswell. Once the fundamentals of low-power voltage conversion circuits are given,it is possible to define the system aspects which are within the scope of thisthesis. This includes the chosen energy harvesting methods, the conditions ofinput power level and input voltage and the targeted output results accordingly.Chapter 3 is assigned for the design of the CMOS RF energy harvesting

2

1.3 Thesis Structure

system. The general circuit model of the harvester is given with regard to theimpedance of the main parts of the harvester: antenna, CMOS RF rectifier andthe matching network. According to the given circuit model, the principles ofpassively maximizing the RF input voltage is detailed. With the fundamentalsof voltage conversion circuits given in Chapter 2, it will be possible to clarify theproposed system for RF energy harvesting. The proposed concept is presentedwith the explanation of the suggested methodology to increase the sensitivityof the CMOS RF energy harvesting system. The suggested CMOS system iscomposed mainly of an RF rectifier and a charge pump. The design of cross-coupled differential RF rectifier is detailed with simulation results. Moreover, thedesign of a cross coupled charge pump is illustrated including the design of thedriving circuits and the related simulation results. The layout of the proposedCMOS harvesting system is given in addition to the trade-offs of sizing thecapacitors and switches in the RF rectifier and charge pump. The chip is testedusing both an RF signal generator and a dipole antenna using two differentmeasurement boards. The measurement results using both test boards are shownand discussed.Chapter 4 is assigned for the design of low input voltage boost converter for

thermal energy harvesting. The circuit model of the thermal energy harvestingsystem is described according to the electrical model of the thermoelectric genera-tor (TEG). The suggested circuit design of the boost converter is given includingthe proposed methodology of the transformer reuse technique. The converter isoperated in two phases: the self-start-up phase and inductor based boost. Theself-start-up oscillator circuit is explained with simulation results. The circuitof the inductor based boost is given as well including the driving pulse signalgeneration circuit. Furthermore, the control circuit which decides the operationphase of the converter is clarified with regard to the low power comparatorand the driving multiplexer circuit. Similar to the RF energy harvesting system(chapter 3), the layout of the CMOS converter circuit is illustrated along withthe size limitations and trade-offs regarding the wide switches and capacitors.The measurements results are demonstrated and discussed. It is important tonotice that the test boards are the same as the ones used to measure the RFenergy harvesting system.

Chapter 5 gives a summary for the accomplished research in this thesis. Theconclusions regarding the achieved work and its experimental results are dis-cussed in addition to a brief comparison with previous works found in literature.The outlook for future works are presented in order to discuss the possibilitiesfor improving the performance of the implemented circuits.

3

Chapter 2

Fundamentals of Conversion Circuits in EnergyHarvesting Systems

Since the research in this thesis concentrates on low power energy energy harvest-ing systems, this chapter reviews the main fundamentals of low power CMOScircuits. The power management circuits are designed for the source energy.Therefore, the most known energy harvesting methodologies are clarified alongwith the nature of the generated electrical signal. The basics of low power circuitsas well as the power conversion circuits are inspected including those which areproposed to be used in this work.

2.1 General Architecture of Harvesting System

Energy can be found in different forms in ambient nature while the electricalenergy is a common human need. Various transducers are used to convert differentkinds of energy into electrical energy, Fig. 2.1 shows the general architectureof energy harvesting system. The main challenge in this application is thesufficiently wide gap between the produced voltage from the harvester and theminimum required voltage for the load. Therefore, voltage conversion is neededto boost the voltage up to the desired level. These power conditioning circuitscan limit the system performance. The power management circuits are based onthe characteristics of the transducers and the nature of their produced electricalsignals. According to the energy source, the harvested voltage can be AC or DCwith low or high level while the conversion circuit in the harvesting system canbe AC-DC rectifier or DC-DC up-converter.

2.2 Methods of Energy Harvesters

The energy sources available for harvesting can exist in four main forms: light,radio frequency (RF) electromagnetic radiation, thermal gradients, and piezo-electric and motion. Every energy kind has its related applications, requirements,transducers and power management circuits. Therefore, it is needed to explorethe harvesting methodology accompanied with every kind of energy source inorder to optimize the conversion circuits accordingly.

5

Chapter 2 Fundamentals of Conversion Circuits in Energy Harvesting Systems

Har

ves

ter

En

erg

y s

tora

ge

un

it

Sen

sor

no

de

DC

DC

AC

DC

Piezoelectric

energy

RF energy

Solar energy

Thermal

energy

Fig. 2.1: Energy harvesting system.

2.2.1 RF Energy Harvesting

RF energy harvesting is a process where the emitted EM radiation from nearbyambient RF sources is linked to a receiving antenna to be converted into usableDC voltage. The main advantage in RF energy harvesting is the availability ofpower sources everywhere and in various conditions. Radio waves with differentfrequencies are transmitted from many types of devices such as cell phones,WLAN routers, GSM towers and TV towers. On contact with a conductor suchas an antenna, these EM waves induce electrical current on the conductor’ssurface [42].jgsdSensor nodes in applications of temperature and moisture monitoring remainin deep sleep mode for long time while it is charged up by the transmitted RFpower. In a later step, it is activated at a certain voltage level. Similarly, thesensors in irrigation systems can be active during the water delivery and sleepagain [24]. Many applications are optimum within short distances from RF powertransmitters like the sensors of temperature, motion, position, water and smokein hotel rooms. RF energy harvesters using large antenna size can be useful todrive pollution sensors in zones which are crowded with pedestrians [24]. It ispossible to realize these applications as practical systems available commercially.Powercast and Microchip produced RF energy harvesting kit for a battery-lesswireless powered applications [3]. This given system is a combination of RFenergy harvester by Powercast from and an ultra low power MicroController µC.

RF Power Density

The transmitted power reduces strongly because of the losses in transmissionmedia in outdoor and indoor environments. In indoor areas, the transmittedpower from WLAN routers can be taken as an example. The losses can bedetermined using the path loss propagation model given in [6] which is a suitable

6


UHF TV Broadcasting

GSM

WSNRF-EH

WLAN

Data processing

Fig. 2.2: RF power sources are everywhere.

7


Table 2.1: Losses of walls inside buildings.Wall description Loss

[dB]

plasterboard or light concrete wall of 10 cm 3.4Thick concrete or brick wall of 10 cm 6.9

model for initial WLAN planning. The path loss in dB is given by

LdB = Lo,dB + 20 log10 d+ k

[kf + 2kf + 1−b

]f Lf +

kw∑i=1

kwiLwi, (2.1)

where kf denotes the number of penetrated floors. The parameter b is used tofit empirically the nonlinear effects of the number of floors on the path loss.Lf denotes the loss between adjacent floors. The integer kw is the numberof wall types, kwi and Lwi denote the number and loss for walls of ith type,respectively [6]. Lo,dB is the free space path loss at reference distance of 1m andit is calculated as

Lo,dB = 20 log104π.fc

, (2.2)

where f is the frequency and c is the speed of light [16]. In order to calculate thelosses of walls, Table 2.1 which is given by [6] gives loss approximation of twotypes of most known walls inside buildings. As a verification of the path losses,rough measurements have been done at the Integrated Analog Circuits and RFSystems Laboratory at RWTH Aachen University using the WLAN router astransmitter and the antenna of notebook as receiver (Fig. 2.3). The losses inRF power transmission were calibrated across open space and brick walls inthe building with a transmitted power of 20 dBm peak according to the routerdatasheet. On the notebook side, the inSSIDer software which is a Wi-Fi networkscanner application for Microsoft Windows and Apple OS X was used [1], [2].Fig. 2.5 and Fig. 2.6 show the measurement results and theoretical calculationsfor the path losses versus distance across open space and walls respectively, Thethickness of the walls is about 15 cm.It is not possible to compensate the massive path losses by increasing thetransmitted power because of health precaution and regulations. The RF exposureis of concern for many European researches which concentrate on the effects ofGSM non ionizing radiation like Biomedical Effects of Electromagnetic Fields[7]. These studies can be helpful to estimate the power density on moderatedistances from GSM base stations [46]. It was found by [46] that RF power

8


inSSIDerWLAN router

Fig. 2.3: Floor plan (first floor) of the laboratory building showing the locationsof measurements of WLAN signal path loss.

Fig. 2.4: Example of desktop scanning window by inSSIDer software [2].

9


2 4 6 840

50

60

Distance [m]

Path

loss

[dB]

Cost231inSSIDer

Fig. 2.5: Path losses of RF signal of WLAN router RF in open space.

2 4 640

50

60

70

Distance [m]

Path

loss

[dB]

Cost231inSSIDer

Fig. 2.6: Path losses of RF signal of WLAN router RF across two walls.

10


densities of 10−5 mW/cm2 to 10−4 mW/cm2 are expected at distances between25m to 100m from a GSM-900 base stations in indoor or outdoor on an elevatedlevel.

2.2.2 Thermal Energy HarvestingThermal energy (TE) is another form of energy freely available in the ambientenvironment. It can provide sufficient electrical power able to drive WSN systemsin various conditions. Thermal Energy Harvesting TE-H takes the advantagethermoelectric effect to produce electrical power using what is known as Thermo-Electric Generator TEG (see Section. 4.1). Simply, the thermal energy generatedfrom the heat source at certain higher temperature is channeled through theenclosed TEG while the residual heat is then released to the surrounding ambientair at lower temperature [44].The thermal energy harvester is based on temperature difference 4T betweenhot side of Th and cold side of Tc. The efficiency of conversion from thermalenergy to electrical energy relates directly to 4T as given in Carnot’s formula

ηcarnot = (Th − Tc)Th

. (2.3)

This temperature gradient can be found in various applications when there is aheat source at higher temperature than that of ambient environment [36]. The4T can reach 10 C between the human body skin and ambient temperatureof 25 C while the chest, head and the wrist are suitable body parts for energyharvesting. Sensors for preventive health-care, monitoring chronic deceases andvital body signs are related applications for such heat sources. Another exampleof heat sources is the waste heat from the daily used machines with Th higherthan that in human body. Moreover, the waste heat from the internal combustionengine exhaust can give 4T of several hundreds degrees by the exhaust gasesthemselves [36]. More related examples can be in the refrigeration systems andother heat pump cycles while the supplied sensors exist in automation systemsand industrial applications.The heat source availability is not the only advantage in thermal energy har-vesting. The thermal energy harvesters are featured by their small size givingflexibility to fit with different work environments. Moreover, TE-H systemswork autonomously while they can provide power continuously. Especially, withhuman, animal and other natural heat sources. The energy conversion processin TE-H is not accompanied by any remnants considered as pollutants. Theavailable electrical power from the TEG depends on the temperature gradient4T and the characteristics of the TEG and the heat sink used. Not far fromthe commercial thermoelectric generators that are used for energy harvestingapplications, Fig. 2.8 shows the open circuit voltage, Voc, and the available power

11


PN

PN

PN

PN

PN

NP

PN

NP

PN

NP

PN

PN

NP

PN

NP

PN

NP

PN

PN

PN

PN

PN

PNV Heat Sink

Hot side

(TEG)

Fig. 2.7: Thermal energy sources with thermoelectric generator TEG.

12


100 10110−1

100

101

4T [C]

PTEG

[mW

]

PTEG

Fig. 2.8: The output electrical power of typical TEG with size of 30mm2.

from the TEG, PTEG, for typical TEG with electrical resistance of 2W andsize of 30mm2 [34]. It is possible to obtain higher electrical power with highertemperature difference 4T and larger TEG devices. However, this is limitedwith cost, size and other operating conditions.

2.2.3 Piezoelectric Energy Harvesting

It is possible to utilize the mechanical vibrations in various applications toproduce electrical power. The vibrational energy sources can be high levelvibrations from the large industrial equipments or low level vibrations whichcommonly occur in the ambient environment. Fig. 2.9(a) shows the equivalentmodel of a general vibrational system proposed in [49]. If the system housing isvibrated with a displacement of y(t), the suspended seismic mass m is vibratedin contrast with a displacement of zt, the differential equation that describesthis relative motion is

mz(t) + d z(t) + k zt = −my(t) , (2.4)

where k is the spring constant and d is the damping constant. The magnitude ofoutput power according to [33] is given as

|P | =mζe ωnω

2 ( ωωn

)3Y 2(

2 ζe + ζm(ωωn

))+(

1−(ωωn

)2)2 , (2.5)

13


Table 2.2: Input frequency and acceleration of some common vibration sources[33].

Vibration source a (m/s2) FHCar engine compartment 12 200Blender casing 6.4 121Clothes dryer 3.5 121Nervously tapped heel 3 1Small microwave oven 2.5 121Windows next to a busy road 0.7 100CD on notebook computer 0.6 75Second story floor of busy office 0.2 100

where Y is the displacement magnitude of input vibrations, ζe is the electricaldamping ratio, ζm is the mechanical damping ratio, ω is the input frequencyand ωn is the natural frequency of spring mass system. For ω = ωn, the outputpower is maximum and Eq. 2.5 can be simplified as

|P | = mζeω3 Y 2

4 (ζe + ζm)2 = mζe a2

4ω (ζe + ζm)2 , (2.6)

where a is the acceleration magnitude of input vibrations. The output power isdirectly related to the acceleration and inversely related to the input frequencyused. Table. 2.2 gives the input frequency and acceleration of some commonvibration sources [33].There are three conversion mechanisms to generate electrical power from suchenergy sources [28, p.276]:• Inductive systems: An AC electrical current is induced in a coil due to arelative motion between a magnet and the coil (Fig. 2.9(b)).• Capacitive systems: A mechanically variable capacitance results in changingthe energy stored in the capacitor. For constant charge, the voltage increases asthe capacitance decreases. On the other hand, for constant voltage, charge willbe drained out of the capacitor as the capacitance decreases [33]. In both cases,the mechanical energy is converted to electrical energy (Fig. 2.9(c)).• Piezoelectric converters: When a mechanical stress is applied on a piezoelectricmaterial, a surface charge appears across the material layer giving an open circuitvoltage (Fig. 2.9(d)). Moreover, if an oscillating mechanical load is placed onsuch materials, AC electrical power is generated.

14


y(t)

z(t)

d

k

m

(a) Equivalent model ofvibrational system.

V(t)

I(t)

B

Y

(b) Inductive mechanism of vibra-tional to electrical enery conver-sion.

I(t)

Y

Constant charge

Constant voltage

V(t)

Y V

(c) Capacitive mechanism of vibrational toelectrical enery conversion.

Y

m

V

Piezoelectric Bimorph

(d) Piezoelectric bimorph for vibrational toelectrical enery conversion.

Fig. 2.9: Vibrational energy harvesting systems.

15


Table 2.3: Producible power with various optical energy conditions [28, p.274].Lighting condition Incident power density

(mW/cm2)

Sunny sky (day time) 100Cloudy sky 510 ft from an incandescent bulb 1010 ft from a CFL bulb 1

2.2.4 Solar Energy Harvesting

Solar energy is one of the most promising energy sources that can substitutethe expensive power sources used nowadays. The harvesting process from lightsources is strongly desired because it is free, clean and it is has no pollutantproducts that can harm the nature. Applications of solar energy harvestingcan be seen in various environments of residential, vehicular , space and navalapplications. In comparison with other energy sources, the solar energy is muchabundant. The energy supplied from the sun to the earth for one day is sufficientto power the total energy needs of the planet for one year [18, p.1].Solar power harvesting systems convert sunlight and other photonic energysources to electrical power. These harvesting systems based on photovoltaic cellsor what is also called as solar cells that utilize the photovoltaic effect will beexplained in sec. 2.2.4. The harvested power from light sources depends on thelighting conditions and area of photovoltaic cells. Table. 2.3 give some examplesof the incident power according to the lighting conditions.

Photovoltaic cells

The photonic energy is converted to electrical energy via a physical process calledphotovoltaic effect. The photovoltaic cell consists of two layers of semiconductormaterials, N-type material with majority of electrons and p-type material withmajority of holes (Fig. 2.10). A part of the incident photons on the solar cell areabsorbed so that the electrons are energized and move from the N-type layerto the P-type layer across the junction between them. Consequently, positivecharges are built along the N-type side of the PN junction and negative chargesare built along the P-type side. An electric field (DC) is generated at the PNjunction giving the force to move the electrons from the semiconductor towardthe negative side passing to the load. In contrast, the holes move in the oppositedirection toward the positive side [18, p.1]. Multiple photovoltaic cells can bearranged in series and parallel within arrays in order to raise the output voltageand output power as shown in Fig. 2.10. The conversion efficiency from photonic

16

2.3 Low Voltage Low Power CMOS Circuits

PV cell Module

Array

Photons

V+

N- type

P- type

Deplition layer

Anti-reflecting coating

Electrode

Electrode

V-

PV cell

(cross-section)

Fig. 2.10: Structure of photovoltaic arrays.

energy to the electrical energy of the PN junction depends on used technology.It define the produced output DC power from the solar cell. Table. 2.4 containsthe reported maximum efficiency obtained for some photovoltaic technologies.


2.3.1 Electrical Characteristics of CMOS Transistor in Sub-thresholdRegion

The complementary metal oxide semiconductor transistors abbreviated as CMOStransistors are used in various integrated circuits known nowadays. These devicesare referred as NMOS or PMOS when the current flow is due to electrons orholes respectively. Fig. 2.11 shows the structure of NMOS transistor fabricatedon a P-type substrate which is also called the bulk or body. The device has fourterminals referred as the gate G, source S, drain D and body B respectively. Thegate terminal is a polysilicon region insulated from the substrate via a silicondioxide SiO2; the source and drain terminals are formed by heavily doped Nregions in the P -type silicon bulk.Assuming that the source and substrate are grounded, when a positive voltage isapplied to the gate of the NMOS transistor, the holes in the channel are repelledaway from the surface and a depleted layer of negative ions (inverted charges) iscreated underneath the silicon surface. As the gate voltage increases, an electroncurrent flows from the drain D to the source S due to diffusion. This effect is

17


Table 2.4: Conversion efficiency of photovoltaic junction according to the usedtechnology [28, p.275].

Technology Efficiency %

a-Si 11p-Si 18SC-Si 25Organic 5Organic 5CIGS 19Multi-gap 35

N+ N+P+

GDS

P

W

L

P-Substrate

Fig. 2.11: Structure of an N-channel CMOS transistor.

18


called subthreshold conduction and the transistor operates in weak inversionregion or subthreshold region. The current in this region is finite but it relatesexponentially to the gate-source voltage as [29, p.27]

Id = Io exp(VgsnVT

), (2.7)

where n > 1 is nonideality factor and VT = (kt)/q is the thermal voltage, Iois the residual drain current in saturation for Vg = Vs = 0 [47, p.58]. Theweak inversion operating region is preferable with low supply voltage for lowpower applications because the currents are small. On the other hand, it isaccompanied with drawbacks of high noise, limited speed and it is hard toachieve good linearity.At a sufficient positive voltage value the electrons moves from the source to thedrain forming a channel of charge carriers and the transistor is turned on. Thevalue of the gate voltage at which this occurs is called the forward voltage orthe threshold voltage Vth. Similarly, PMOS transistor is turned on according toa similar principle to that of NMOS but with reserved polarities. The inversionlayer is formed from holes in N-substrate in the PMOS transistor when a negativegate-source voltage Vgs is applied.When |Vgs| ≥ |Vth|, the drain current referred as Id is related to the gate-sourcevoltage Vgs and drain-source voltage Vds [29, p.20] as

Id = µn CoxW

L

[(Vgs − Vth)Vds −

12V

2ds

](2.8)

where µn is the electron mobility ( cm2

V.s), W

Lis the aspect ratio and Vgs−Vth is the

overdrive voltage. The drain current Id reach maximum when Vds = Vgs−Vth. Forfurther increasing Vds, the transistor channel is pinched off and the drain currentwill not follow the Eq. 2.8. According to this condition, the transistor operates inthe saturation region and the drain current becomes relatively constant versusthe drain-source voltage as

Id = 12µn Cox

W

L(Vgs − Vth)2 . (2.9)

For Vds < Vgs−Vth the transistor operates in triode region and the drain currentrelates linearly to the drain source voltage.

2.3.2 Low Voltage Current Reference CircuitThe weak inversion region is advantageous by the minimum drain-source voltagerequired for saturation. The drain current can be constant with a voltage Vdsapplied to the transistor of 4VT to 6VT. This makes such an operating region

19


suitable for low voltage current mirror circuits. It is possible to build low voltagecurrent biasing circuits or amplifiers with supply voltage of less than 8VT to12VT. However, the drawbacks accompanied with subthreshold effect mentionedin Section. 2.3.1 should be taken into account.The regular current reference circuit shown in Fig. 2.12 can be used with lowsupply voltage while the gate-source voltage of the biasing transistors are lessthan the threshold voltage. The output current Iout is independent from thesupply voltage when the reference current Iref is derived from Iout. The PMOStransistors M1 and M2 are sized equally so that Iout = Iref . The source resistorRseries reduces the gate-source voltage of the NMOS transistorM4 in comparisonto that of the transistor M3, thus, the size of the transistor M4 is scaled up by afactor of (K) to compensate its drain current so that(

W

L

)M3

= K(W

L

)M4

,K > 1 . (2.10)

The circuit performance can be enhanced by adding cascode NMOS transistors.

M4M3

IREF

M2M1

Rser ies

IOUT

VDD

Fig. 2.12: Basic supply independent current reference circuit.

The cascode current mirror is used to improve copying the reference current Irefpassing in the transistor M3 to the output current Iout passing in the transistorM4. Additionally, the cascode NMOS transistors are useful for further stabilizingthe output current Iout with high supply voltage as well as reducing both Irefand Iout currents.In order to obtain Iout less than 100 nA for example, it is needed to use undesiredlarge resistor Rseries of more than 1MW. Alternatively, a chain of NMOS tran-sistors can be used while the gate terminals are connected to the ground in order

20


to increase their equivalent resistance (Fig. 2.13). Thus, the current Iout passingthrough the transistors Ms1 to Msn is decreased drastically. This is helpful toeliminate the size required for integrated large resistor, especially when ultralow output current is desired. The total resistance of these NMOS transistorsreferred as Zs is determined by the source voltage of the transistor Mcas.2 tothe output current Iout. The circuit shown in Fig. 2.13 has been simulated with

M4M3

IREF

M2M1

ZS

IOUT

VDD

MCas.1 Mcas.2

Ms1

Msn

Canscode

transitors

Chain of NMOS

transitors for high

equivalent Zs

Fig. 2.13: Cascode current mirror with chain of transistors proposed instead ofRseries.

supply voltage change for different temperature degrees. Eight series NMOStransistors have been used with (W/L = 20 um/5 um) giving high equivalentseries resistance Zs, while the other biasing transistors has been optimized toguarantee low reference current with minimum possible supply voltage. Theoutput current given by the circuit is 13 nA. Fig. 2.14 show the simulation resultsof Iout with supply voltage change for different temperatures. It can be seenthat the circuit can start-up with 350mV while the output current is close to be

21


independent from the supply voltage. Conversely, it is strongly affected by thetemperature change. As mentioned before, the drain current is strongly affected

0 0.5 1 1.5

0

10

20

Supply voltage [V]

I out[nA]

Temp.=0 CTemp.=27 CTemp.=50 CTemp.=80 C

Fig. 2.14: Simulation results of Iout with supply voltage using NMOS transistorschain instead of large Rseries.

by the temperature change when Vgs < Vth according to Eq. 2.7. Therefore, it isneeded to find a low power solution to decrease the temperature dependency ofIout. As the temperature rises, the reference and output currents are increasingwhile the gate voltage of the transistors Mcas.1 and Mcas.2 is decreasing. If theresistance Zs is increased, the Iout will decrease and vise versa. This principlecan be used to eliminate the temperature dependency of the drawn currents asshown in Fig. 2.15. The series connected NMOS transistors can be used as anactive load so that their gate voltages referred as Vactiveload are related to thegate voltage of the transistors Mcas.1 and Mcas.2. Thus, when the temperatureincreases, the biasing voltage Vactiveload changes inversely while the resistanceZs is increased reducing the output current. The biasing voltage Vactiveload canbe defined by a voltage divider circuit consisting of series of diode connectedNMOS transistors.The circuit shown in Fig. 2.15 has been simulated with temperature changes fordifferent supply voltages. The simulation results show that Iout changes slightlyfor wide range of temperature variations using the suggested temperature adap-tive current compensating circuit as shown in Fig. 2.16. The output currentat 27 C is higher than given in the previous circuit (Fig. 2.13) because thegate terminals of the series transistors are biased with the Vactiveload instead ofconnecting them to ground giving lower equivalent resistance Zs.

22


ZS

MCas.1 Mcas.2

Ms1

Msn

Voltage

divider

VActive load

Fig. 2.15: Low power circuit suggested to reduce the temperature influence onIout.

2.3.3 Reference Voltage Circuit with Low Supply VoltageIt is possible to generate a voltage reference circuit (Fig. 2.17) based on theproposed current reference circuit in sec. 2.3.2. An additional branch is usedcontaining a biasing PMOS transistor and diode connected NMOS transistor.The voltage across the transistor Mref represents the output reference voltagereferred as Vref . The gate-source voltage of the transistor Mref is equal to thedrain-source voltage and according to Eq. 2.9, the output reference voltage canbe determined as Vref

Vref = Vds =√√√√ 2 IDµn Cox

W

L

+ Vth , (2.11)

where ID = Ibias is the biasing current controlled by the width W of the PMOSbiasing transistor Mbias. The reference voltage Vref is related directly to thesquare root of the length of the transistor Mref and the drain current ID. Thesupply voltage range is the same as that of the current reference circuit. However,the minimum supply voltage is constrained with the threshold voltage Vth of thetransistor and the drain-source voltage of the biasing transistor Mbias.The advantage of a low saturation drain-source voltage when Vgs < Vth can befurther utilized to generate a reference current and voltage. Fig. 2.18(a) shows asimple low voltage reference circuit built by an NMOS transistor and resistor.

23


0 20 40 60 80

22

23

24

Temperature [C]

I out[nA]

V DD=0.5VV DD=1VV DD=1.5V

Fig. 2.16: The impact of the suggested temperature adaptive current compen-sating circuit.

The gate terminal has been grounded in order to achieve minimum gate-sourcevoltage giving minimum saturation drain-source voltage. At a certain V DDvalue, the drain current passing through the resistor reaches saturation giving aconstant reference voltage referred as Vref . High drain current or high resistanceresult in high Vref level and vice versa. The drain current is expected to be ultralow because of the extremely low gate-source voltage of the transistor Mbias.Consequently, high resistance Rseries is necessary to generate moderate referencevoltage value and to reduce the power consumption of the circuit.The resistor Rseries can be replaced by multiple PMOS transistors (Mp1...Mpn)connected in series while the source terminal of the transistor Mp1 is connectedto the drain terminal of the transistor Mbias and the gate terminals of thePMOS transistors are connected to ground (Fig. 2.18(b)). As the supply voltageincreases, the drain current increases and reaches the saturation while the outputvoltage is equal to the defined reference voltage. Using long PMOS transistorsenhance the equivalent resistance of the connected transistors and reduce thedrawing current needed to reach the desired Vref .

Low power Low-Voltage Reference Circuit

Not far from the principle used in sec. 2.3.3, the circuit proposed in Fig. 2.19can be used to generate the reference voltage. The circuit consists of two NMOStransistors (Mn1,Mn2) that are reverse biased while the voltage across thetransistor Mn2 represents the reference voltage Vref . The gate-source voltageof the transistor Mn1 is negative minimum (Vgs.n1 = −V DD) giving higher off

24


M4M3

IREF

M2M1

IOUT

VDD

VBias

Mref

Vref

Mbias

Fig. 2.17: Reference voltage generation using the suggested current biasing circuitin sec. 2.3.2.

resistance than that of the transistor Mn2 which has higher gate-source voltage(Vgs.n2 = − (V DD − Vdsn1)). Therefore, as the flowing current reaches satura-tion, the reference voltage is expected to be low. This circuit is advantageous forultra-low power consumption.

2.3.4 Low Voltage Amplifier CircuitsThe CMOS transistors can give acceptable gain even with low supply voltage byutilizing the advantage of minimum saturation voltage due to the subthresholdeffect. High transconductance gm can be obtained by increasing the width whilethe drain current remains constant. Low drain current is expected as Vgs < Vthleading to further an increased transconductance. The exponential relation ofthe drain current to the gate-source voltage (Eq. 2.7) encourages to use theCMOS transistors in subthreshold region in amplifier circuits. However, usingwide devices with low drain current can limit the circuit’s speed as mentionedbefore.

Inverter Amplifier

The inverter circuit shown in Fig. 2.20(a) is a simple form of inverter amplifiersused in oscillators, buffers, gain stages and digital circuits. Assuming that thesize of the PMOS transistor is chosen to keep charge mobility close to that inthe NMOS transistor, the signal gain increases with supply voltage. However,the aspect ratio W

Lof the used devices is further optimized according to the

circuit purpose. In ring oscillators, the frequency is determined by the number ofinverter stages and signal delay across every stage controlled by the device size.

25


Mbias

Rser ies

VDD

Vref

(a) Reference generation using resis-tance Rseries.

Mbias

Vref

VDD

Mp1

Mpn

(b) Reference generation usingPMOS transistors.

Fig. 2.18: Low-power voltage reference circuit using NMOS with low Vgs.

For driving buffers supplying heavy loads like the charge pumps, wider devicesare desired for low on-resistances.A common source amplifier (Fig. 2.20(b)) is another form of inverter amplifierwhile the current source load is used to maximize the gain. The transistor Mbias

can be biased by a current reference circuit giving constant current Ibias. Thevoltage gain is [29, p.58]

Av = −gm rout , (2.12)where rout is the output impedance seen at the output node and it is calculatedas

Rout = Ro,n ‖ Ro,bias, with Ro = 1ID λCMOS

, (2.13)

where λCMOS is the channel length modulation which improves with longtransistors. The voltage gain of the amplifier relates proportionally to the channellength of the transistors Mn and Mbias and, reversely, to the biasing currentIbias.It is possible to combine the CMOS inverter with a biasing PMOS transistorgiving an analog amplifier as in Fig. 2.20(c). This amplifier circuit can be used asa low-power high gain amplifier so that it gives an output signal with peak-peakamplitude equal to V DD even when the input signal has low amplitude. Thistechnique is helpful to raise the input signal amplitude so that it can be equalto supply voltage with minimum possible power consumption.

26

2.4 Power Managements Circuit

VDD

Mn1

Vref

Mn2

Fig. 2.19: Reference voltage generation using reverse biased NMOS transistors.

Differential Pair

The differential pair amplifiers (Fig. 2.21) are widely used in monolithic analogcircuits. The main advantage in using such circuit is the high rejection of thecommon mode signals in both inputs. These signals are eliminated due to thecoupled drain or source terminals of the input transistors. In subthresholdregion, high transconductance minimizes the difference of the gate voltages of thetransistor pair required to compensate their mismatch. However, the drawbackin using differential pair is its limited linearity.


As the electrical power is produced from the harvesting transducer, it is necessaryto process the incoming electrical signal giving the desired load conditions.Voltage conversion circuits are used for power conditioning purposes. Accordingto the harvester electrical signal, the conversion circuit can be AC-DC rectifierconcerning input AC signals or DC-DC up-conversion circuits regarding inputDC signals. Moreover, the power management circuit can contain both conversioncircuits.

2.4.1 Rectifier conversion CircuitsDiode Based Rectifier

Several stages of the voltage doubler shown in Fig. 2.22 can be used to build aconventional RF rectifier using CMOS diode connected transistors as rectifierdiodes. The shown circuit consist of a rectifier consisting of D1 and C2 and avoltage clamp consisting of D2 and C1. During the negative phase of the RF

27


VDD

Mn

Mp

VoutVin

(a) Inverter amplifier.

Mbias

Mn

Vout

Vin

VDD

Vbias

Ibias

(b) C-S amplifier with cur-rent source load.

Mn

Mp

VoutVin

VDD

Vbias

Ibias

(c) Biased inverter amplifier.

Fig. 2.20: Implementations of inverter amplifier with low supply voltage.

Vout

Vin-

VDD

Vbias

Ibias

Vin+

Fig. 2.21: PMOS differential pair amplifier.

28


C1

C2

Vrec D1

D2

VDC

Fig. 2.22: Voltage doubler circuit.

input voltage, D1 is off and D2 is on. The current pass through D2 with voltagedrop equal to Vth1 to charge C1 up to Vamp − Vth, where Vamp is the amplitudeof input sinusoidal signal. In the positive phase, D2 is off and D1 is on. Thecurrent passes through D1 to charge C2 similarly up to Vamp − Vth2 in additionto the stored energy in C1 during the negative phase so that the output DCvoltage is

Vout = 2Vamp − Vth1 − Vth2 . (2.14)

The voltage doubler circuit is the fundamental building block for many con-ventional CMOS voltage multipliers like the Dickson charge pump and theGreinacher voltage multiplier as shown in Fig. 2.23 and Fig. 2.24 respectively.The main draw back in diode connected rectifiers is the voltage drop acrossevery rectifying diode, which decrease the output voltage massively. The rectifiercannot work with an input voltage of less than a threshold voltage, when thediode is in the dead zone or cut-off region. This kind of rectifier is not suitable forlow input power, where the input voltage is expected to be ultra low. High inputpower applications on the other hand require less stages of voltage doublingcircuit for better efficiency and prefer rectifying devices of high power capabilitylike Schottky diodes rather than CMOS transistors.In order to evaluate the diode connected rectifier for low power RF energyharvesting, single-stage doubler rectifier has been simulated using HSMS2860Schottky diodes with an input power range of −16 dBm to 0 dBm at a frequencyof 0.85GHz. The rectifier has been matched to an ideal RF power source of 50Wfor an input power of −16 dBm using single series inductor. Fig. 2.25 shows thesimulation results for DC output voltage and efficiency versus input power. Theefficiency can reach up to 72% with a DC output voltage of 2.6V for an inputpower of 0 dBm. The efficiency and output voltage decrease in strict way for lowinput power, when the input RF voltage Vrec is less than the forward voltage Vthof the diode. The output power and voltage can be higher when the matchingnetwork is optimized for higher input power because the efficiency changes

29


Vrec

VOUT

C1

D1

D2 C2

Fig. 2.23: Dickson RF voltage multiplier.

Vrec

VOUT

Fig. 2.24: Greinacher charge pump.

30


−15 −10 −5 0

1

2

Pin(dBm)

Vout(V

)

40

50

60

70

Efficien

cy(%

)

VoutEfficiency

Fig. 2.25: Output voltage and efficiency of single stage rectifier using HSMS2860diode.

strongly with RF input power. This is due to the nonlinear input impedance andmismatch within high input power range as mentioned before. It can be seenclearly that a diode based rectifier is suitable for high input power range andnot optimum for ultra low power as in the application discussed in this work.

Threshold Compensating Rectifier

As it was shown by a diode based rectifier that the threshold voltage drops acrossevery rectifying diode, it decreases the efficiency significantly. The situation canbe worse when the input voltage is less than threshold voltage so that the rectifiercannot be powered up to produce noticeable DC voltage. For low forward voltageVth devices, the rectifier is enabled to give high DC voltage with low input power.In order to reduce the threshold voltage drop of the device, many alternativepassive and active techniques have been discussed in literature. Methods of usingexternal power sources are inconsistent with the autarkic operation concepttargeted in this thesis. Contrarily, passive techniques require auxiliary circuitsconsuming additional power.The threshold voltage technique can be simply realized in multistage rectifierwhen the gate of an NMOS transistor is connected to the next adjacent sourceof the following transistor instead of the traditional diode connected structuregiving a biasing gate-source voltage equivalent to the incremental voltage acrosseach stage. In case that a PMOS rectifying device is used, the gate terminal isconnected to the previous source of last stage. According to the same principle,

31


Vrec

VOUT

M1 M2 M3 M4 Mi Mi+1

C1 C2 C3 C4 Ci Ci+1

Fig. 2.26: Three-levels threshold voltage compensation method.

the bias gate-source voltage can be increased by extending the gate connectionto further next or previous stages.Fig. 2.26 shows a hybrid method of 3 stage compensation reported by [14].During the positive cycle of the input RF voltage, the PMOS transistor Mi isforward biased because the gate terminal is connected to the source of the thirdprevious transistor giving a negative gate-source voltage. During the negativephase, the gate-source voltage of the transistor Mi is still negative increasingthe leakage current of the reverse biased transistor.Most of the reported threshold compensation methods give the priority to reducethe threshold voltage drop while neglect the power losses by the reverse leakagecurrent when the CMOS transistor is reverse biased. The leakage current referredby ILeakage is expressed as

ILeakage = IDoW

Lexp

((Vgs − Vth)

nVT

), (2.15)

where Ido is the drain current when (Vgs − Vth) = 0, VT is the thermal voltageand W

Lis the device aspect ratio. In the threshold compensation technique, the

gate-source voltage contains a DC component is given constantly from the nextnodes even when the rectifying diode is reverse biased. This will increase thepower losses due to the leakage current. Consequently, using higher level ofthreshold voltage compensation is limited with the resulting leakage current.An adaptive method was presented by [15] according to this principle using aux-iliary circuits shown in Fig. 2.27. During the negative input phase, the PMOSauxiliary transistor Mib is switched off because its gate-source voltage is lessthan the forward voltage Vth while the diode connected PMOS transistor Mia

32


VRF

VOUT

M1 Mi-1 Mi Mi+1

C1 C2 Ci-1 Ci Ci+1

M1b M(i-1)b MibMiaM(i-1)a

Fig. 2.27: Adaptive threshold-voltage compensation method.

is on. Thus, the rectifying PMOS transistor Mi is back compensated from theprevious node so that its gate-source voltage is negative and it is forward biased.During the positive input phase, the source voltage of the auxiliary transistorMib is higher than its gate voltage so that it is switched on while the transistorMia is off. Thus, the transistor Mi is front compensated from the next node anditn reverse biased. The leakage current is reduced as well.The solutions given by threshold compensation rectifiers can enable the harvesterto work with lower input power in comparison to the conventional diode basedrectifiers. However, the auxiliary circuits increase the power budget of the con-version circuit giving that the usefulness of compensation technique is noticeableonly when a relatively sufficient power is available. The rectifier circuit designshould focus on the challenge of ultra low power received in environments of RFenergy harvesting.

Cross Connected Differential Rectifier

It is possible to utilize differential RF signals rather than single input to switch thePMOS and NMOS devices to on and off states giving a self-driven synchronousrectifier as shown in Fig. 2.28. When VRF is high and VRF is low, M1 and M4turn on while M2 and M3 are off. Current flows to the node VDCH through M4and out of the node VDCL through M1. During the opposite input voltages, M1and M4 turn off while M2 and M3 are on. Thus, the current still in the samedirection giving a DC voltage across the load connected between nodes VDCLand VDCH .The output voltage can be calculated as

VoutDC = VDCH − VDCL = 2 |VRF | − VNdrop − VPdrop , (2.16)

33


VRF

M1 M3

M2 M4

VDCL VDCH

Vout

VRF

Fig. 2.28: Elimination of the forward voltage Vth using cross connection tech-nique.

where VNdrop and VPdrop are the voltage drops due to the on-resistance of NMOSand PMOS devices, respectively.In order to achieve higher output voltage, multistage rectifier can be constructedby cascading multiple rectifying cells. The input differential RF signals areapplied in parallel to the rectifying stages across the coupling capacitors asshown in Fig. 2.29. When the input voltage Vrec is high and Vrec is low, current

Vrec

Vrec

VRF

VRF

M1 M3

M2 M4

VDCL VDCH

Rload

Vout

Cout

CupperCupper

Clower Clower

Fig. 2.29: Multistage differential input cross connected rectifier.

flows through transistor M1 while the coupling capacitor Cupper in the first stageis charged up to |Vrec| − (VNdrop + VPdrop)/2. When the input voltage Vrec islow and Vrec is high, the current flows throw the transistor M3 of the first stageand the transistor M2 in the second stage to charge the capacitor Clower ofthe second stage similarly up to |Vrec| − (VNdrop + VPdrop)/2 in addition to thecharge stored from Cupper in the first stage. The charge flow passes in parallel

34


through the transistors M4 of the first stage and the transistor M1 of the secondstage charging the capacitor Cupper in the second stage to be discharged intothe capacitor Clower in the following stage and so on. Consequently, the chargewill be added at every stage and the DC voltage is boosted up. The last stage isconnected without coupling capacitor to direct the DC current into the outputcapacitor.

2.4.2 DC-DC Up-Conversion CircuitsThe DC-DC up-converters are needed to step-up the low DC voltage availablefrom the harvester reaching the desired level. There are two categories of suchconversion circuits, the charge pump and the inductor based boost. The chargepump uses capacitors for charge transfer and energy storage while the inductorbased boost use inductors for energy transfer and capacitor for energy storage.

Low Power Charge Pump Circuits

The charge pump is switched capacitor based circuit used to generate highervoltage than the supply voltage for which the circuit is working. The basicstrategy in boosting charge pumps can be illustrated in the circuit shown inFig. 2.30. The circuit consists of single capacitor Cstage used for boosting andthree switches S1, S2 and S3 used to control charge transfer. When the switchesS1 and S2 are closed while the switch S3 is open, the capacitor Cstage is chargedto the input voltage Vin. When the switches S1 and S2 are opened while theswitch S3 is closed so that the capacitor Cstage behave as a voltage sourceconnected in series with Vin. Since the capacitor maintains its previously storedcharge (Q = C Vin), the output voltage rises to be twice the input voltage. It ispossible to cascade multiple stages of the circuit given in Fig. 2.30 so that theoutput voltage

Vin = (N + 1) Vin , (2.17)

where the N is the number of stages. The charge transfer switches can be

S1 Vout

Vin

S2S3

Cstage

Fig. 2.30: Basic structure of single stage charge pump circuit.

realized using CMOS transistors driven by two anti-phase clocks. The clock

35


voltage is usually limited with the input voltage, therefore, the minimum inputvoltage required to power up the charge pump is constrained with the forwardvoltage Vth of the CMOS switch. Another challenge facing the charge pumpsworking with low input voltage is the voltage drop across the used switcheswhich can be dominant with respect to the input voltage. Many circuit topologieshave been given in literature to enhance the charge pump performance with lowinput voltage. In this section, some of these circuits are reviewed including theoperation principle, advantages and disadvantages.

Dickson Charge Pump

The Dickson charge pump circuit given by John F. Dickson [25] (Fig. 2.31) isconsidered as a principle circuit for many known charge pump designs. The diodeconnected NMOS transistors work as switches while two out-of-phase clocksVCLk and VCLk are capacitively coupled to the consecutive nodes between theswitches. When the clock signal VCLk is low and VCLk is high, the transistor M1is on while the transistor M2 is off. The voltage at the first node V1 is settled toVin − Vth. When the clock signal VCLk is high and VCLk is low, assuming thatVCLk = Vin, the voltage V1 is calculated as

V1 = Vin + (VCLk − Vth) . (2.18)

At the same time, the transistor M2 is on leading to the voltage at the second

Vn

Mn+1

VoutV1

M1 M2

Vin

VCLK VCLK

Cout

Fig. 2.31: Multistage dickson charge circuit.

node is (V1 − Vth). When the cycle is repeated, the clock signal VCLk is low andVCLk is high so that the transistor M1 is off while the transistor M2 is on, thevoltage V2 becomes

V2 = Vin + 2 (VCLk − Vth) . (2.19)By using multiple stages, the voltage at the nodeN will be (VN = Vin +N (VCLk − Vth)).The last transistor MN+1 works as an isolating diode while the output voltageis [25]

Vout = Vin +N (VCLk − Vth)− Vth . (2.20)

36


The parasitic capacitances of the MOSFET devices influence the coupled clockvoltage amplitude at each node referred as V ′CLk. This effect can be eliminatedby using large coupling capacitor or minimizing the parasitic capacitance as [22]

V ′CLk = CstageCstage + Cparasitic

, (2.21)

where Cparasitic is parasitic capacitance. It is clear that the voltage gain inevery stage is reduced due to the forward voltage drop across the CMOS switch.Moreover, the voltage drop increases with the current supplied to the load. Theoutput voltage can be expressed taking into account the voltage fluctuationcaused by the load current referred as Vl as well as influence of the parasiticcapacitance as

Vout = Vin +N(V ′CLk − Vth − Vl

)− Vth . (2.22)

Charge Pump with Static Switches Biasing

The voltage drop across every switch due to the forward voltage Vth are highlyeffective when the input voltage is low. Another charge pump design was givenin [53] and [52] (Fig. 2.33) in order to overcome the reduction of the voltage gaincaused by the threshold voltage drop. The gate terminals of the main NMOSswitches referred as M1 ...M4 are connected to the nodes of the following stagesutilizing the high potential of these nodes so that the mentioned transistors areforward biased. The diode connected NMOS transistors are connected in parallel

VCLK

VCLK

V3

M4

VoutV1

M1 M2

Vin

M3

V2

Cout

Fig. 2.32: Three-stage charge pump with static switch biasing.

to the main switches to start-up the charge pump. The main NMOS switchesstill forward biased even when the clock signal coupled to their drain terminals

37


are low. Thus, part of the charge stored in the stage capacitors can be pumpedreversely to the previous stages instead of the next stages decreasing the circuitperformance.

Charge Pump with Dynamic Switches Biasing

The drawback of leakage current caused by static switch biasing can be solved ifthe main switches are turned on and off when the clock signal coupled to theirdrain terminals are high and low, respectively. Such solution has been given in [8]using inverter circuits to bias the gate terminals of the main switches M1 ...M3dynamically as shown in Fig. 2.33. The inverter which drives the switch M2 is

V3

M1 M2

VCLK

VCLK

VoutV1Vin V2

Cout

Fig. 2.33: Two-stage charge pump with dynamic switch biasing.

controlled by the node voltage V2 while the source terminals of the PMOS andNMOS transistors of the inverter are connected to the node voltages V3 and V1respectively. When the clock signal VCLk is high while VCLk is low, the nodevoltage V1 > V2 so that the output signal of the inverter goes high to turn thetransistor M1 on. When the clock signal VCLk is low while VCLk is high, thenode voltage V2 < V1 so that the output signal of the inverter is low to turn thetransistor M1 off.

Cross Coupled Charge Pump

Another method to bias the charge transfer switches dynamically is given in[26] without the need for inverter circuits, Fig. 2.34. Every stage consists oftwo parallel paths used for charge transfer and controlled by two out of phase

38


CuCu

MpuMnuMpu

VCLK

Mnu

Vin Vout

VCLK

VCLK

VCLK

Fig. 2.34: Multistage cross coupled charge pump.

signal clocks VCLk and VCLk. Each path consist of NMOS transistor and PMOStransistor while the clock signal is coupled through the stage capacitor which isconnected to the drain terminals of the mentioned transistor. When the clocksignal VCLk is low and VCLk is high, the transistor Mnu is on charging the stagecapacitor Cu of the first stage to the input voltage Vin. At the same time, thetransistors Mpu in the first stage and Mnu in the following stage are off so thatthe reverse current is eliminated. When the clock signal VCLk is high and VCLk islow, the transistors Mpu in the first stage and Mnu in the second stage are on sothat the coupling capacitor in the second stage is charged up to 2Vin. During thenext duty cycles, the output voltage is raised according to the number of stagesto reach maximally (N + 1)Vin as mentioned in Eq. 2.17. The same operationprinciple is applied in the opposite path, but in complementary fashion so thatone coupling capacitor is charging while the coupling capacitor in the oppositepath is pumping the charge to the output side.

Inductor Based Boost

The magnetic based DC-DC converters can give a voltage step-up conversionmechanism using quasi-lossless inductor for energy transfer from the powersource to the output. The principle of the inductor based boost is based onenergizing and de-energizing the inductor L from the input voltage Vin to theoutput voltage Vout in two alternating phases, (Fig. 2.35). During the energizing

39


phase, the switch Mn is on and the diode is off so that the energy is built upin the inductor by the input voltage (VL(t) = Vin) while the output capacitorCout supplies the load with current

(IC(t) = −Vout

Rload

). During the de-energizing

phase, the switch Mn is off and the diode Mp is on and the inductor voltage isreversed to be (VL(t) = Vin − Vout) while the output capacitor Cout is chargedup to

(IL,average − −Vout

Rload

), where IL,average is the average inductor current.

The net inductor voltage for the whole switching period Ts according to theprinciple of inductor volt-second balance is given by

Vpulse

Vout

Mn

Vin

Cout Rload

IL

VL(t)

Vin

VL(t)Vout

Cout Rload

Vin

VL(t)Vout

Cout Rload

Mswitch is on Mswitch is off

Energizing Phase De-energizing Phase

L

L L

IC

Fig. 2.35: Magnetic-based DC-DC up-conversion circuit principle .

VinD1 Ts = (Vin − Vout)D2 Ts ⇒ Vin = (1−D1)Vout ⇒VoutVin

= 1(1−D1) .

(2.23)Conversely, the average capacitor current IC for the switching period Ts is zeroaccording to the principle of capacitor ampere-second balance resulting in

−VoutRload

D1 Ts +(IL,average −

−VoutRload

)D2 Ts ⇒ IL,average = Vin

D22

= Vin

(1−D1)2 .

(2.24)

40


D1Ts

D2Ts

t

VL(t)

Vin

Vin -Vout

Fig. 2.36: Inductor voltage waveform during the switching time Ts.

2.4.3 Power Losses in Conversion CircuitsGenerally, the available power from the transducer is almost low. Therefore, thepower losses of the conditioning circuits can be dominant in comparison to theharvested power. This motivates to understand the losses accompanied withthe conversion circuits and in opposite, the solutions on the circuit design andoptimization are given. The main source of the aforementioned losses are theparasitic resistance, capacitance and inductance associated with the lumpedcapacitors and inductors and the CMOS switches as well as the driving andcontrol CMOS circuits.The power losses are classified mainly into two categories, conduction losses anddynamic losses. Conduction losses refers to the power dissipated in the parasiticresistors of the lumped elements and switches. Dynamic losses concerns the powerlost by the parasitic capacitances of the switches during the incoming controlclock signals. The reverse returned current from the output capacitor is referredalso as dynamic losses. In this section, power losses are briefly reviewed withtheir causes and related expressions. The inductor-based boost circuit shown inFig. 2.37 can be taken as a typical example of power conversion circuits.

Conduction Losses

The power conduction flow through the resistive elements is associated withconduction losses. These elements include the on-resistances of the PMOS andNMOS switches referred as Ron.p and Ron.n, respectively, the equivalent seriesresistance of lumped inductor L1 referred RL,esr and lumped output capacitorCout referred as RC,esr. For simplicity, the on-resistances of the CMOS switchesare assumed to be equal so that Ron.p = Ron.p = Ron. The inductor currentIL consists of the DC component IL,average and the AC component ∆IL. Theresistive losses due to the DC current Iload is

Pres,dc = I2L,averageRL,esr+I2

L,averageRon (D1 +D2) = I2L,average (RL,esr +Ron) .

(2.25)

41


Cgs Cgd

Cgd

Cgs

Vpulse

Vout

Mn

Vin

Cout Rload

IL

VL(t)

LIC

Ron

Ron

RL,esr

RC,esr

Fig. 2.37: Magnetic based boost converter circuit and its parasitic elements.

Moreover, the AC part of the inductor current ∆IL flows through the resistorsgiven in Eq. 2.25 and the equivalent series resistance of the output capacitorRC.esr. The ∆IL is determined as

∆IL = dIL(t)dt

= VL(t)L

= Vin − VoutL

= VinLD1 Ts . (2.26)

The resistive losses due to the AC component of the inductor current is

Pres.ac = (∆IL)2rms (RL,esr +Ron +RC.esr) . (2.27)

For (∆IL)rms = IL√12 (R.M.S. of a triangle ripple current) and by substituting

the ∆IL from Eq. 2.26 into Eq. 2.27, the Pres.ac is given as

Pres.ac =(∆IL)2

rms

12 (RL,esr +Ron +RC.esr) . (2.28)

The DC and AC resistive losses are decreased by using high quality lumpedelements, wider switches for less on-resistance and using higher switching fre-quency for less (∆IL)rms. However, wider devices and higher switching frequencyincrease the dynamic losses as will be explained later.

Dynamic Losses

The dynamic losses include the gate drive losses, the bidirectional losses andthe quiescent current losses when both NMOS and PMOS switches are on. Gatedrive losses refer to the energy lost due to charging and discharging of theparasitic capacitors of the switch gates Cgs and Cgd. This switching gate-driving

42

2.5 The Proposed System Aspects

losses are directly related to the switching frequency fs, the input voltage Vinand the gate parasitic capacitors (device size) as

Pdyn = fs (Cgs + Cgd) V 2in . (2.29)

Bidirectional losses are caused due to light average inductor current and largeripple current ∆IL during the de-energizing phase so that the inductor currentIL(t) is reversed being negative. In order to avoid this kind of power losses, thefollowing condition is provided

IL,average >12∆IL ⇒

VinD2

2 Rload>VinL

D1Ts ⇒2L

Rload Ts> D1 (1−D)2 .

(2.30)Another solution can eliminate the bidirectional losses by changing to discontin-uous mode DCM where an additional operation phase of disconnecting inductorfrom the output capacitor Co and Rload to avoid reversing the inductor current.Quiescent current losses is caused when both PMOS and NMOS switches beingon so that high current peaks are drained to the ground. This power loss happenstwice during the switching cycle and is proportional to the time duration whenboth transistors are on.


The energy harvesting system can be proposed in accordance to the conditionsassociated with targeted energy sources on one side and the fundamentals givenin this chapter regarding the conversion circuits on the other side. This sectionwill summarize the main targets of this work and define the main principles ofthe proposed circuits for energy harvesting.

2.5.1 Harvested Power Conditions and Targeted Energy SourcesThe advantages of RF energy harvesting that have been listed in Section. 2.2.1give the motivation to present a complementary conversion circuit for suchenergy harvesting method. It has been explained that the RF power densityis strongly reduced with distance from the transmitter (see Section. 2.2.1).Therefore, the operation condition of ultra low input power is the main challengeto the conversion circuit proposed for RF energy harvesting.Thermal energy harvesting as another kind of energy harvesting methods hasbeen discussed including its feature in Section. 2.2.2. The available power fromthe typical TEG modules (off the shelf TEG modules) is higher than harvestedfrom RF energy harvesting. On the other hand, the DC voltage of the TEG isexpected to be quite low (10mV/K to 50mV/K). Therefore, this gives anotherexample of the harvested power conditions which require different conversion

43


circuit design rather than should be designed for RF energy harvesting.The main purpose of this work is to present various CMOS circuit solutions forlow-power low-voltage available from the harvester. Thermal and RF energyharvesting methods are associated with such harvested power conditions andrequire different power conversion circuits, thus, fitting optimally with scope ofthe work.

2.5.2 Sensitivity EnhancementThe input voltage and current are reproduced using the power conversion circuitin order to supply the needs of the loading application. Literature refers to thepower conversion efficiency of the conversion circuit as its principal figure ofmerit. Power conversion efficiency ηPCE can be calculated as

ηPCE = PoutDCPin

, (2.31)

where Pin is the input electrical power to the conversion circuit and PoutDC isthe output DC power supplied to the load calculated as

PoutDC = V 2out

Rload, (2.32)

where Vout is the output DC voltage applied to the load resistance Rload. Op-timizing the conversion circuit for high efficiency requires using wider CMOSdevices and less voltage boosting stages in order to supply highest possibleDC power to the load with lowest voltage drop due the the on-resistance. Aswas explained in Section. 2.4.3 wider devices can increase the switching powerlosses. Moreover, additional circuit might be necessary to enhance the efficiency.This, however, can increase power consumption of the power conditioner like theforward voltage Vth compensation circuits or the MPPT circuits.The energy sources in the surrounding environment can be considered as bound-less reservoir of energy utilized by the harvester, but its main drawback is lowpower density. It is expected that output power from the harvester is low anddoes not fit to the regular power hungry loads like the transmitting power am-plifiers which that can tolerate conversion circuits with high power consumption.The energy source is not able to supply such power dumps. Therefore, solutionshave been given in literature to extend the operational life of energy harvestingapplications.The development in semiconductor technology and IC design have contributedeffectively in reducing the power consumption of the sensor node. Simply, a WSNnode consists of low power micro-controller to process data from the applicationand low power RF transceiver for information transmission [20]. Recent studiesproposed a duty-cycled power management strategy is divided to sleep phase

44


Tsleep

TActive

Time

Time

VMin.

Energy storage phase Energy discharge phaseVWake-up

Fig. 2.38: Cycled power management strategy by micro-controller in low powerWSN.

and active phase [39]. The sensor system is going in sleep or stand by mode whilethe storage capacitor of energy harvester is charged up. At a defined voltagelevel, the power management unit switches the system to the active mode andthe main circuits are activated utilizing the stored energy.Duty-cycled operation is desired in energy harvesting applications because itgives the opportunity to prolong the sleeping time Tsleep and reduce the averagedrawn current by the sensor node. Fig. 2.38 shows the power consumption schemeduring a typical duty cycle manged by an ultra-low power microcontroller µC.The total power consumption over the whole cycle time can be calculated as

Average Power consumption = Active mode power + sleep mode powerTsleep + Tactive

(2.33)

45


This kind of energy conditioning strategy is useful to provide high energy at theoutput when only low power is available from the source. The minimum inputpower or input voltage required to produce a desired output DC voltage withsufficient energy stored in the output capacitor is referred as the sensitivity. As theenergy harvesting system has high sensitivity, it is able to work with challengingoperation conditions similar to that given in Section. 2.5.1. Improving the systemsensitivity is proposed in this work rather than maximizing the efficiency becauseit fits optimally to the expected conditions of power density.

46

Chapter 3

RF Energy Harvesting System using Low-PowerCharge Pump

This chapter presents a proposed methodology to enhance the sensitivity of theRF energy harvesting systems by amplifying the input RF voltage and supportingthe rectifier by a DC-DC up-converter. The rectifier is based on keeping a highinput reactance to maximize the quality factor of input impedance giving highvoltage gain via matching network. On the other hand, an ultra-low powercharge pump is connected to the rectifier in order to boost the DC voltage. Theharvesting system has been realized in 130 nm CMOS technology. The designhas been proven by an RF source and dipole antenna as well. The sensitivity ofthe harvester is taken at the input power, where the unloaded output reaches 1V.The measurements show a sensitivity of −25 dBm over the frequency range from800MHz to 870MHz using RF power source. Dipole antenna has been designedand fabricated using economical FR4 substrate. The measurements show thatthe sensitivity using the dipole antenna is −25 dBm over the frequency rangefrom 810MHz to 830MHz.

3.1 Circuit Model of RF Energy Harvester

The RF energy harvester (RF-EH) consists basically of an antenna, a matchingnetwork and an RF to DC conversion circuit as shown in Fig. 3.1. The RF poweris transmitted as a radiation of EM waves to be picked up by the receivingantenna giving an AC electrical power. The conversion circuit referred as RFrectifier converts the input AC signal to DC signal while the harvested electricalenergy is stored in the output capacitor. Fig. 3.1 shows a simple model of thecircuit of RF-EH. The antenna can be modeled as an RF power source withcomplex impedance, ZA, composed of effective loss resistance, Rloss, effectiveradiation resistance, Rr, and imaginary part, XA, which is mostly inductivereactance

ZA = Rr +Rloss + jXA . (3.1)

With regard to the antenna impedance, power is converted into heat by theohmic resistance, Rloss, while RF power is emitted from the antenna into space

47

Chapter 3 RF Energy Harvesting System using Low-Power Charge Pump

Rr Rloss XA Xmatch

Rin

Xin

Pr

Vrec

ZinZA

VA

Antenna Matching RF rectifier

Fig. 3.1: Circuit model of RF energy harvesting system.

in the form of EM waves by the radiation resistance, Rr. On the other side,the impedance of RF rectifier is almost capacitive and it consists of real part,Rin, and imaginary part, Xin. In regular CMOS rectifiers, the input impedanceis nonlinear but it can be assumed to be constant with low input power [21].The antenna impedance should be equal to the rectifier impedance in order toensure maximum power transfer from the source to the rectifier, therefore, amatching network is necessary. The antenna and the CMOS harvesting systemare optimized according to the RF frequency band, the expected power receivedand the minimum output DC voltage required by the load.

3.2 Passive Amplification of Input RF Voltage

Typically, high efficiency rectification circuits require a minimum input RFvoltage of more than the forward voltage, Vth, of the rectifying device. This canbe guaranteed only with sufficient input power. Therefore, low input power isthe main obstacle to any system concept since it limits the performance of powerconversion circuits. Using Schottky diodes or CMOS rectifying transistors withlow threshold voltage can enable the system to work with relatively low inputpower as will be shown later. In this section, the main scope is to maximizethe available RF voltage from antenna in order to overcome the barrier of theforward voltage, Vth, of the rectifier.

3.2.1 High Radiation Resistance

The induced RF voltage, VA, at the receiving antenna is related to the availablepower, Pav, and the radiation resistance, Rr, as

VA =√

8Pav Rr . (3.2)

48

3.2 Passive Amplification of Input RF Voltage

−30 −25 −20 −15 −100

0.5

1

Input power [dBm]

VA[V

]

Rr= 50WRr= 200WRr= 500WRr= 2000W

Fig. 3.2: VA vs the radiation resistance for (Rr = Rrec).

It can be seen from Eq. 3.2 that the induced voltage at the antenna, VA, increaseswith, Rr, even when the available power, Pav, is low. Assuming that the ohmicresistance Rloss in the antenna is negligible and the input reactance, Xin, of therectifier is quite small value and equal to (XA +Xmatch), the input RF voltageto the rectifier, Vrec, can be calculated as

Vrec ≈ VARin

(Rin +Rr). (3.3)

The input RF voltage, Vrec, can be maximized with the conditions of high Rrand (Rin = Rr), Fig. 3.2 shows how Vrec increases with high radiation resistance.

3.2.2 Input Impedance With High Quality

In looking to Fig. 3.1, taking into account the influence of the inductance inthe antenna (XA) and the matching network (Xmatch) on one side and thecapacitance in the input impedance of the rectifier (Xin) on the other side, itis possible to amplify the input RF voltage effectively using high quality LCcombination. The voltage gain in input voltage referred as, Avmatch, can becalculated from [41]

Avmatch = VrecVA

= Xin +Rin(XA +Rloss +Rr) + (Xmatch) + (Xin +Rin) . (3.4)

49


0 100 200 300 4000

0.1

0.2

|Xin| [jΩ]

Vrec[V

]

Rr=10WRr=25WRr=50WRr=100W

Fig. 3.3: Impact of high Xin on Vrec.

The induced voltage at antenna, VA, in Eq. 3.2 can be substituted in Eq. 3.4 aswell leading to Vrec is related to the available RF power, Pav, as

Vrec =√

8Rr Pav · (Xin +Rin)(XA +Rloss +Rr) + (Xmatch) + (Xin +Rin) . (3.5)

For (Xin=XA + Xmatch and assuming that the ohmic resistance is neglected(Rloss ≈ 0), Eq. 3.5 can be simplified to

Vrec =√

8Rr Pav · (Xin +Rin)Rr +Rin

. (3.6)

The impact of high input reactance Xin on the input RF voltage Vrec has beenexamined with different radiation resistance Rr values as shown in Fig. 3.3assuming that Rin = Rr and Rloss = 0 and the received RF power −25 dBm.It can be noticed from the shown results that high radiation resistance caneliminate the desired advantage of high input reactance.Increasing the quality factor of input impedance extremely would make thevoltage gain very sensitive to the frequency because of the impedance mismatch.The model shown in Fig. 3.1 has been simulated to examine the variation ofvoltage gain of Vrec versus frequency with different quality factor Q values.The simulation based on using ideal RF power source with center frequencyof 850MHz and frequency range from 800MHz to 900MHz while (Rin = Rr),Fig. 3.4 shows the simulation results.It can be seen that the voltage gain Avmatch is maximum at center frequencywith high quality input impedance, but the frequency bandwidth is narrow.

50

3.3 Proposed CMOS RF Energy Harvesting System

800 820 840 860 880 900

5

10

15

20

Frequency [MHz]

Vrec/VA

Q=5Q=10Q=20

Fig. 3.4: Variation in voltage gain with frequency for fc = 850 MHz.

The voltage gain decreases sharply when the operating frequency deviates fromthe center frequency so that the advantage of high quality input impedancefades away. On the other side, the mismatch influence of the low quality LCresonator is less affected by the frequency. Within some limits, it is possible tocalm the response of the RF voltage gain to the frequency by using moderateinput resistance and radiation resistance values. Therefore, there is an optimumtrade-off between using RF rectifier with high input reactance Xin and usingantenna with high radiation resistance in order to get sufficient input RF Vrecwith low input power and wide frequency range.

3.3 Proposed CMOS RF Energy Harvesting System

Various RF energy harvesting systems are previously presented in literature inorder to obtain an accepted DC output voltage from low input power. RF energyharvester has been given to utilize a high input impedance of the rectifier tomaximize the RF input voltage and improve the sensitivity [41]. Despite of itshigh sensitivity, the system needs for an off-chip control loop circuit to providean adaptive matching network. Furthermore, the given sensitivity of −27 dBmis reached at singly frequency of 868MHz. High efficiency RF rectifier has beenpresented in [15] is based on threshold voltage compensation technique. Therectifier efficiency reaches to 32% at −15 dBm with a sensitivity of −20.5 dBm forthe frequency range from 902MHz to 928MHz. However, it is difficult to receivesuch high power levels from RF ambient sources as explained in Section. 2.2.1. Aboost converter circuit can be connected to the rectifier in order to increase the

51


Matching RF Rectifier

Vrec

Antenna

VinDC DC

DC

VOUT

CP

CMOS integrated RF

energy harvesting system

Fig. 3.5: The proposed CMOS integrated RF energy harvesting system.

output voltage as proposed in [35]. High sensitivity of −25.5 dBm was reached ata single frequency of 2.2GHz. Off-chip coupling capacitors were needed for thecharge pump. A similar concept was adopted by [31] but with a fully integratedsystem. The achieved sensitivity was relatively low at −17.5 dBm for a singlefrequency of 900MHz.In this work, a CMOS RF energy harvester is proposed that can work withultra-low input power giving highest possible output DC voltage. Moreover,the intended system aims to show smooth response vs frequency within thechosen bandwidth. The RF rectifier is preferable to work with familiar antennatype of typical 50W impedance. On one hand, such antennas can be availablecommercially at an economical cost with desired characteristics. On the otherhand, as mentioned in Section. 3.2.2, the source resistance should not be largebecause this would decrease the desired RF voltage gain by resonance, and itshould not be small because this would make the voltage gain by resonancebecoming sensitive to the frequency. Therefore, a resistance with 50W is amoderate desirable value.Furthermore, it is suggested to support the RF rectifier by additional chargepump based DC-DC up converter giving higher output DC voltage for less inputpower. The CMOS RF energy harvesting system consist simply of two mainblocks, RF rectifier and the DC-DC up converter as shown in Fig. 3.5.In order to investigate the feasibility of the proposed solution, a comparison hasbeen made between adding further RF voltage multiplying stages and adding amultistage charge pump as shown in Table. 3.1.The charge pump advantages are: lower power losses and higher voltage up-conversion gain in comparison with RF rectifier. On the opposite side, the RFrectifier is advantageous by smaller coupling capacitors and no driving circuitsneeded. The coupling capacitors in the charge pump are related directly to loadcurrent and inversely to the clock frequency so that the size can be reduced withlow load current as expected in this application. The DC-DC up converter can

52

3.4 Low Power RF Rectifier

Table 3.1: Additional RF multiplying stages vs charge pumpRF multiplying stages charge pump stagesHigh switching losses due tohigher operating RF frequency

Less switching losses because thedriving clock frequency is low

Lower efficiency with Vgs ≤ Vth Higher efficiency with Vgs ≥ VthLess added DC voltage for addedstages because Vrec is low

Higher added DC voltage for ad-ditional stages because Vin is rel-atively high

No driving circuit needed to op-erate the rectifier

Driving circuit is necessary forthe charge pump consuming ad-ditional power

Small coupling capacitors withhigh RF frequency

Large coupling capacitors withlow driving clock frequency

be helpful rather than too many stages in RF rectifiers only when the powerconsumption of the charge pump is minimized. The minimum required inputvoltage of the charge pump is an essential parameter because it affects its designand the architecture of the RF rectifier. As the charge pump can be poweredup with low input voltage, a minimum rectified DC voltage is needed and aminimum input RF power is sufficient.Design methodology, circuit topology and optimization of both RF rectifier andcharge pump including the driving circuit will be explained in the followingsections. The charge pump is designed to boost the rectified DC voltage Vrec,DCup to maximum possible output voltage with minimum Iin,rms drawn by thecharge pump. For low input RF power, it is required from the rectifier to providesufficient DC power able to start up the charge pump. In summary, a highlysensitive RF energy harvesting system is enabled to work with a wide frequencybandwidth.


RF rectifier is the main power conversion circuit in RF energy harvesters whichconvert RF power to DC power. It can be constructed using low thresholdSchottky diodes or CMOS devices. The AC-DC rectifier in general has to dealwith several challenges like the switching losses and the conduction losses whichhave been detailed in Section. 2.4.3. Moreover, the RF low input voltage (lessthan VTH) and the leakage current which is dominant in subthreshold region areadditional obstacles face the rectifier. Such problems would decrease the outputDC voltage. The RF rectifier in this application is preferable as it has high Xin

53


VDD

260 fF

80 Ω

270 fF

300 pH 300 pH 1.5 nH 0.5 Ω 50 mΩ 50 mΩ

ESD

diodes

ESD

diodes

Chip

Parasitic components

of PackagingParasitic components

of PadPCB

Board

Fig. 3.6: Equivalent circuits of pad and package connections including parasiticcomponents.

for high input RF voltage Vrec as explained before. The parasitic capacitances ofthe pads, package and ESD diodes, shown in Fig. 3.6, decrease the quality factorof the input impedance, especially with high frequency. The circuit principlesand topologies of the most used AC-DC rectifier types have been discussed inSection. 2.4.1.

3.4.1 Design of Differential Cross-Coupled RF Rectifier

The circuit of a multistage differential input cross-coupled rectifier is shown inFig. 2.34. The cross connection of the four transistors in every stage gives asimple solution to eliminate the threshold voltage drop without using additionalpower consuming circuits. Additionally, the symmetrical property of the rectifiercircuit topology is useful to cancel all even order harmonic currents and suppressthe power losses caused by them. Another advantage of the differential rectifieris its high input reactance Xin. The signals Vrec and VRF are added at thedifferential input pads of the rectifier leading to the parasitic capacitance of pads,package and ESD diodes will be halved and Xin is doubled. In comparison withthe reviewed RF rectifier types, the cross connected differential rectifier canperform better to overcome the given challenges of RF energy harvesting. Thus,it has been chosen to be implemented in this work with some optimizations.Since the circuit topology of RF rectifier has been decided, the following stepis to optimize the transistor sizes, number of rectifying stages and couplingcapacitors giving an accepted performance. Higher efficiency is obtained withwide transistors because this will decrease the losses in Ron resistance, but thiswill decrease the input impedance and influence the resonance. The number of

54


−30 −25 −20 −15

20

40

Pin [dBm]

ηPCE

[%]

2 stages, Wn=1.6µm4 stages, Wn=10.4µm6 stages, Wn=14µm8 stages, Wn=16µm

Fig. 3.7: Total power efficiency vs received power at a frequency of 850MHz andtypical 50W RF power source.

stages is chosen as a trade-off between being high for higher output DC voltageand low for high RF voltage gain by resonance.For every number of stages, there is an appropriate device size enabling therectifier to produce highest output DC power. In order to find the optimumnumber of stages, the rectifier circuit shown in Fig. 2.29 has been simulatedwith different numbers of stages and different device sizes using 0.13 um CMOStechnology. Low-threshold devices were used while PMOS transistor width Wp

is two times larger than that of an NMOS Wn to compensate the lower mobilityof holes. A 50W RF power source was used with power range of −30 dBm to−16 dBm given as received power. Fig. 3.7 and Fig. 3.8 show the simulationresults of efficiency with the DC rectified voltage at maximum output power vsinput power respectively, for every number of stages with its suitable transistorwidth.It can be seen that using few number of stages, small device size is optimumto enhance the quality factor of input impedance giving highest RF voltagegain Avmatch. The achieved efficiency is low because of the high on-resistanceof CMOS transistors while low DC voltage because of low number of stagesused. On the opposite side, using large number of stages require wider devicesgiving higher output DC voltage, but, wider devices decrease the RF voltagegain Avmatch and increase the switching losses so that efficiency is low. Efficiencyis increased using four stages and moderate device size to reach 42% withoutput DC voltage of 0.72V. This represents a solution for the trade off betweenenhancing the quality factor of the input impedance and reducing the ohmic

55


−30 −25 −20 −15

0.5

1

Pin [dBm]

Vrec,DC

[V]

2 stages, Wn=1.6µm4 stages, Wn=10.4µm6 stages, Wn=14µm8 stages, Wn=16µm

Fig. 3.8: Output DC voltage at maximum output power vs received power at afrequency of 850MHz and typical 50W RF power source.

losses across the rectifying transistors. The DC voltage is further increased usingsix stages with a slight decrease in efficiency to 40%. The six-stage rectifier waschosen as an optimum for high efficiency and acceptable output DC voltage.

3.5 Low-Power Charge Pump

The circuit topologies of charge pumps have been detailed in the previous chapterincluding the advantages and disadvantages of every topology and its relevanceto the application of low-power DC-DC up conversion with low input voltage.The most appropriate design is the cross-coupled charge pump and it has beenchosen in this work because of several reasons as will be discussed in this sectionin addition to the circuit design optimization and added modifications.

3.5.1 Design of Cross-Coupled Charge Pump

The circuit of the cross-coupled charge pumps and their operational concepthave been given in Section. 2.4.2. The cross-coupled charge pump gives a simplemethod to cancel the Vth drop across the PMOS and NMOS switches withoutusing auxiliary circuits [51]. Elimination of the auxiliary circuits would avoid thecharge sharing between the coupling stage capacitors and parasitic capacitorsin these circuits used to bias the charge transfer switches. Besides that, theswitching signal passes directly to the gates of the switches without additionalcontrol devices which can add time delay and increase the reverse current. The

56


risks of applying high potentials across low voltage devices and gate over-stressare avoided also in this topology because the voltage difference between theswitches is equal to the input voltage Vrec,DC [50].Several modifications and optimizations have to be applied to the typical structureof the cross-coupled charge pump to fit optimally for the application in this work.The following sections discuss these added adjustments including the proposeddriving circuits.

Reverse Bulk Biasing

It is important to notice that the main challenge in this topology and othertopologies of low input voltage is the bulk biasing which increase the Vth ofNMOS devices in the last stages when the bulk terminal is connected to ground.Therefore, a triple-well process is necessary in order to avoid the negative influenceof body biasing. It is possible to take advantage of the bulk biasing to alter theVth of the charge transfer switch according to its on or off states. The CMOStransistor can work as an efficient switch when the drain current Id is maximumduring the on state and leakage current Ileakage is minimum during the off state.In order to decrease the leakage current, it is preferable to decrease the thresholdvoltage of the device when it is on and increase it when it is off because leakagecurrent relates inversely to the forward voltage Vth. The bulk terminal voltageaffect the threshold voltage Vth according to following equation

VTH = VTHo + γ(√|2Φ + Vsb| −

√|2Φ|

), (3.7)

where Vtho is the threshold voltage when the source-bulk voltage Vsb is zero, γis the body effect coefficient and Φ is the Fermi potential.Forward body biasing refers for negative Vsb in NMOS device or positive Vsbin PMOS device, Vth is decreased and this is referred as forward body biasingwhich is useful during on state to increase the Id. The same principle is appliedinversely by positive Vsb in NMOS device or negative Vsb in PMOS device sothat Vth is increased and this is referred as reverse body biasing which is neededto eliminate the leakage current as given in Eq. 2.15.Suppressing the leakage current is very important to reduce the power con-sumption of charge pump, reverse bulk body biasing have been utilized incross-connected charge pump as shown in Fig. 3.9. The bulk of every PMOSdevice is connected to the capacitor of next stage to give a positive Vsb andhigher Vth when the device is off. Similarly, the bulk of every NMOS device isconnected to the capacitor of the previous device to give a negative Vsb when itis off.

57


ONON

ON OFFOFF

OFFOFF

ON

Vin Vout

Fig. 3.9: Cross-coupled charge pump using reverse bulk biasing.

Charge Pump Optimization

The charge pump is adjusted including the charge transfer switches sizes, numberof stages, size of coupling capacitors and clock frequency according to the desiredconditions. Minimum Vrec,DC and R.M.S. drawn current Iin,rms are aimed whenstart up the charge pump which has to boost up the output voltage as highas possible across a capacitive load. Wide device size is desirable for higherIload, but it increases the switching losses and ILeakage. Similarly, high clockfrequency is desirable for higher Iload and small stage capacitor, but it causeshigher switching losses as well. It is expected in this application to supply theoutput voltage to a capacitive load as mentioned before so that it is not neededto consider high load current requirements.The structure shown in Fig. 3.9 was simulated using low threshold 0.13µmCMOS devices and ideal pulse voltage sources connected to the stage capacitorsto reach optimum design parameters. Transistor sizes have been minimized to150 nm to reduce the power losses. For the same reason, a low frequency of200 kHz was chosen while the stage capacitors can be kept small as 2.5 pF. Usinga lower frequency would necessitate large capacitors and decrease the outputvoltage. The charge pump was built with 7 stages as trade-off between higheroutput voltage and high Iin,rms. It is not helpful to scale up the switch sizes ofthe initial stages because leakage current losses increase dominantly especiallywith low input voltage.

58


3.5.2 Driving Clock GeneratorThe cross coupled charge pump run with two out-of-phase clocks that are appliedoppositely to every stage. The ring oscillator consisting of an odd number ofinverters can generate the clock signal while the oscillation frequency is definedby the signal delay across every inverter stage and number of inverters. Lowsupply voltage is the key challenge to design a low power ring oscillator becauseof the given reasons before. Using long devices is helpful in such application toreduce the power consumption of the oscillator while it is beneficial to give lowfrequency signal rather than adding extremely large number of inverters.The second challenge to the design of low power ring oscillator is that thefrequency increases strongly with the supply voltage. Consequently, the powerlosses increase heavily for small raise in Vrec,DC . It is possible to stabilize the clockfrequency with supply voltage by a current biasing circuit. However, these typesof circuits require high supply voltage and consume high power in comparison tothe rectified DC power from RF rectifier. In this work, it is proposed to supplythe oscillator by a low power reference voltage circuit instead of Vrec,DC . Thiswould keep low oscillation frequency and maintain low switching losses for highVrec,DC .The proposed reference circuit topology shown in Fig. 2.18(b) and explained inSection. 2.3.3 can be utilized in this application to generate a constant voltagereference for slightly higher supply voltage. This reference circuit is advantageousby its simplicity and the ability to give multiple reference values with horizontaland vertical cascading. The output voltage of the reference circuit Vout,ref isrelated to the supply voltage as

Vout,ref =Vrec,DC for Vrec,DC < Vref

Vref for Vrec,DC ≥ Vref. (3.8)

This circuit consumes not more than few nano watts for low V DD while it doesnot require high supply voltage. The circuit shown in Fig. 2.18(b) was simulatedusing standard CMOS devices in a single column with one NMOS transistor and9 PMOS transistors. The devices have been sized to generate a voltage referenceof 250mV. The simulation results given in Fig. 3.10 show that the output voltagebeing close to the defined level when Vrec,DC is higher. It is possible to reducethe drawn current but the circuit was optimized to be able to supply powerto the oscillator circuit in this application or other reference circuits as will bediscussed later. However, this reference circuit has low performance with regardto the temperature variation.The clock signal will have maximum peak-peak voltage equal to Vref since theoscillator is supplied by the reference circuit. Therefore, additional circuit isrequired to have a peak-peak voltage equal to the input Vrec,DC of the chargepump. As mentioned before, the reference circuit can be cascaded vertically

59


and horizontally giving higher reference voltage values. This principle can beutilized to generate higher reference voltage by using a similar reference circuitwhile the drain of last PMOS transistor is connected to the output terminal oflower Vref . The higher Vref circuit was optimized to reach 350mV supplied toan inverter following the oscillator giving a clock signal with higher peak-peakvoltage. The latter signal would be able to drive an inverter supplied directly fromVrec,DC of the charge pump. Additional driving inverters enlarged sequentiallyare connected to be able to charge up the stage capacitors in charge pump.Fig. 3.11 shows the block diagram of the driving clock generator connected tothe charge pump.

0 1 2 3 4 5

0

0.2

0.4

0.6

0.8

T ime [ms]

Voltage[V

]

Vrec,DCVref1

Fig. 3.10: Reference voltage Vref1 vs Vrec,DC .

The charge pump based DC-DC up-converter has been simulated with inputDC voltage range of 0mV to 800mV according to the proposed driving circuit.The input voltage increase with time as expected when the input RF powerincreases and the rectified DC voltage getting raised as well. The simulationresults shows that the output peak-peak clock signal is equal to the input voltageof charge pump as shown in Fig. 3.12. The oscillation frequency starts increasingwhen Vrec,DC is less than Vref1 and it is stabilized on 200 kHz for higher inputvoltage. The simulations show that the charge pump is able to give more than1V when Vrec,DC is 200mV at a power consumption of 90 nW. Impediments ofpower consuming driving circuits have been solved by low power solutions. Incomparison with high number of stages in RF multiplier, the sensitivity can beimproved using such DC-DC up-converter.

60

3.6 System Implementation

Ring

oscillator

Vref.2 = 0.35V

Reference Generator

Vclk

Vclk

VDD

3 x Inv.

2 x Inv.Inv. Inv.

Charge pump

VOUT

Vref.1 = 0.25V

0.25V0.35V

Vrec,DC

Fig. 3.11: Block diagram of the charge pump based DC-DC up-converter.


The Tape-out of the suggested system has been achieved using CMOS UMC0.13 µm technology. Low threshold devices were used in RF rectifier for low Vrecas expected. Low threshold devices have also been used in the charge pumpin order to enable start-up of the DC-DC up-converter with low input voltagewhile triple-well NMOS transistors were required in order to avoid the substratebiasing. In the ring oscillator, standard devices were utilized in order to guaranteelow frequency and low drawing current. MIM capacitors have been used with1 pF in RF rectifier and 2.5 pF in the charge pump. The rectifier output storecapacitor was chosen to be 10 pF. The sizes of capacitors were optimized intrade-off between optimum performance and area considerations. ESD protectiondiodes were used with typical pads according to the chosen technology in inputand output pins. The layout area of the system is (0.5× 0.5) mm2 (Fig. 3.15)within a total area of (1.6 × 1.6) mm2 for multiple systems chip as shown inFig. 3.14. The chip is packaged in a 48-pin QFN package with 0.5mm pin pitch.

61


0 1 2 3 4 5

0

0.2

0.4

0.6

0.8

T ime [ms]

Voltage[m

V]

Vrec,DCVclk

Fig. 3.12: Clock signal with peak-peak equal to Vrec,DC .

0 200 400 600 800

50

100

150

200

Vrec,DC [mV]

Frequency

[kHz]

Fig. 3.13: Oscillation frequency stabilization with Vrec,DC .

62


RF energy harvesting system

Fig. 3.14: Chip micro graph of the RF energy harvesting system within a tape-out using UMC 0.13 um technology and total area of (1.6x1.6)mm2.

RF Rectifier

Charge pump

Measurments

Ref. 250mV

Ref. 350mV

Osc. & driving

Inverters

480 um

520 um

Fig. 3.15: Layout of the proposed energy harvesting.

63


3.7 Experimental Results Using RF Power Source

In order to test the fabricated CMOS RF energy harvester, a Printed CircuitBoard (PCB) referred as Board1 has been designed to measure the systemfunctionality as well as the performance of each circuit block. The board wasfabricated using FR4 substrate with two layers and a thickness of 1.55mm witharea of (5× 5) cm2. The board is connected to the power source with 50W via anSMA connector so that the the chip is supplied by the input RF power with thetargeted bandwidth 800MHz to 900MHz. The designed rectifier has differentialinputs so that balun is needed with 50W impedance for balanced and unbalancedports. Off-chip SMD inductors were used for matching the source to the inputimpedance of the rectifier. The harvested energy is stored in external capacitorwhere the output DC voltage is measured. Fig. 3.17 shows the test PCB withthe chip placed in the center surrounded with other mentioned components.

3.7.1 Test ProcedureThe test setup is based on measuring the system sensitivity to produce 1Vacross unloaded capacitor with frequency range of 800MHz to 900MHz. It isnecessary to define matching network between the source impedance and theinput impedance of the rectifier. The charge pump is coupled to RF rectifierand influences its input impedance. For simplification, the charge pump ismodeled as a resistor determined by measuring the drawn Iin,rms with minimumrequired Vrec,DC to produce 1V across the output capacitor. The resistor value iscompensated back in a simulation test bench shown in Fig. 3.16. Other parasiticcapacitors and inductors of pads, package and ESD diodes are taken into accountto find the required inductance value in matching network.

3.7.2 Measurement Results of Charge PumpFig. 3.19 shows the output voltage of the DC-DC up-converter and the drawnIin,rms versus input voltage applied from DC power supply. The maximumimpedance of voltmeter Rvoltmeter is about 10MW while it is intended to measurethe voltage with a capacitive load. Therefore, a series resistance of 90MW isconnected in series to the voltmeter (Fig. 3.18) so that the output voltage ismeasured by the voltage reading with a multiplication factor according to

Vout = Vvoltmeter ·Rs,meas +Rvoltmeter

Rvoltmeter, (3.9)

where Rs,meas is the added series resistance, Rvoltmeter and Vvoltmeter are thevoltmeter impedance and readings, respectively. This factor can be calibratedby applying 1V across the total impedance and measuring the Vvoltmeter. The

64


RF source

Matching

270 fF

1.25Ω1.8nH

Vrec,DC

C.P. ModelPAD

PAD270 fF

Package 1.2 V

1.25Ω1.8nH

RF rectifier

ESD

Fig. 3.16: Matching network based on the charge-pump model coupled to rectifier.

charge pump is able to produce more than 1V for input DC voltage of 0.2Vwith a power consumption of less than 100 nW. It is important to notice thatthe charge pump is switched off for input voltage of more than 1.3V. Thisvoltage is high enough for the driving inverters to show continuous state sincethe maximum peak-peak input clock signal is limited by Vref2 = 0.35 V as wasshown in Fig. 3.11. However, this is helpful as a protection for the charge pumpagainst extremely high input DC voltage.

3.7.3 Sensitivity Measurements of RF Energy Harvester

Once the matching network is defined in a procedure explained in Section. 3.7.1,it is possible to measure the system sensitivity using an RF power source andbalun with the mentioned frequency range. An off-chip balun from HHMserieswas used with an insertion loss of 1.4 dB according to the data sheet. Fig. 3.21shows the measurements results of Vout vs input RF power at the center frequencyof 850MHz.The output voltage can be more than 1V for input power of −23.5 dBm. Takinginto account the balun and cable losses, the system sensitivity for 1V acrossthe output capacitor can be defined to be better than −25 dBm. It is clear fromthe measurement results that the output voltage is related directly to the inputpower and increases to reach more than 5V for input power of −9 dBm. Thecharge pump would switch off with higher input power when Vrec,DC reaches1.3V as mentioned in the previous section.In order to test frequency influence on the sensitivity, the output voltage wasmeasured with frequency range of 800MHz to 900MHz and input power of

65


Vout

VinDC

Balun

and matching network

CMOS Energy

Harvesting system

PinRF

Rs,meas

Fig. 3.17: Sensitivity measurements using RF4 PCB and RF source.

66



DC

DC

Vout

C. P.

CMOS Integrated RF Energy

Harvesting System

RF source

50Ω

Pin

Balun

V

90MΩ

DC decoupling

VVoltmeter

Vrec,DC

A

DC Power

supply

CP measurment

Fig. 3.18: Charge pump and sensitivity measurement setup.

0.2 0.4 0.6 0.8 1 1.2 1.4

2

4

6

Vrec,DC(V )

Vout(V

)

10

20

I in,rms(uA)

VoutIin,rms

Fig. 3.19: Measurements of the output voltage and drawn current of the chargepump.

67


800 820 840 860 880 900

−25

−20

−15

−10

Frequency [MHz]

S11

[dB]

Fig. 3.20: Measurement of S11 parameter using of Board1 with the extractedmatching network (Section. 3.7.1).

−25 −20 −15 −10

2

4

Pin [dBm]

Vout[V

]

Fig. 3.21: System sensitivity measurement with center frequency of 850MHz.

68

3.8 Design of PCB Antenna for RF energy harvesting

800 820 840 860 880 9000.8

0.9

1

1.1

1.2

Frequency [MHz]

Vout[V

]

Fig. 3.22: Measurements of frequency influence on the sensitivity.

−23.5 dBm as shown in Fig. 3.22. The CMOS RF energy harvester keeps givingmore than 1V with frequency range 800MHz to 870MHz and decreases smoothlywith higher frequencies. The input impedance of the RF rectifier with moderateRin value and sufficient quality factor enable the system to show stable responsefor wide frequency bandwidth.


The antenna is a component in which the radiation or reception of EM waves hasbeen optimized for certain frequency ranges by fine tuning of design properties[13, p.118]. The electromagnetic wave is generated by the transmitting antennato be propagated in far-field environment. In opposite, the receiving antennaresonates at the same frequency of the radiated EM to induce an electrical RFsignal. The antenna is considered as a major complementary element to RF-EHas it collects the incoming RF signals of various frequencies and converts themto electrical power. In this work, it is intended to prove the ability of the givenCMOS RF-EH which has been designed and fabricated to perform successfullyin normal environment of wireless power transfer using a proposed PCB antenna.Therefore, general information for antenna characteristics and types would begiven briefly in this section as well as the deigned and fabricated antenna.

3.8.1 Antenna CharacteristicsDefinitions of the most known parameters of antenna:

69


Gi

Radiation pattern of directional antenna

Radiation pattern of isotropic antenna

Fig. 3.23: Comparison of radiation pattern between isotropic emitter and direc-tional antenna.

Directivity and Gain

For an isotropic emitter, the energy is radiated uniformly in all directions. Atdistance of r, the radiation density S can be calculated as [13, p.112]

S = PEIRP4πr2 , (3.10)

where PEIRP is the Effective Isotropic Radiation Power. For a real antenna, theradiation density is greater in the preferred direction of the antenna. Fig. 3.23shows the difference between radiation patterns of directional antennas andisotropic emitter. It can be seen that the radiation density is focused in onedirection to be more than that of isotropic emitter by a certain factor. Thisfactor is referred to as the gain of the antenna Gi. The radiation density can betaken into account via the gain effect as [13, p.117]

S = Pt.Gi4πr2 , (3.11)

where Pt is the given power to the antenna. The antenna design may includereflectors in order to increase the directivity, D, which defines the ability of theantenna to radiate in a specific direction. The Gi is related to D and efficiencyof antenna ηantenna as [23]:

Gi = D.ηantenna . (3.12)

The ηantenna depends mainly on the loss tangent of the substrate and the resistivelosses of the metal. Furthermore, both ηantenna and D are strongly frequencydependent.

70


Effective Aperture

The maximum power received by antenna referred as, PinRF , is related to thepower density, S, and effective aperture, Ae, of antenna [13, p.119]

PinRF = Ae.S . (3.13)

The Ae is identified according to the antenna design and it determines also theRF power absorbed and transferred to the connected terminating impedanceZin. The Ae is related to the gain of antenna as [23]

Ae = λ2

4πGi . (3.14)

Antenna Impedance and Radiation Resistance

The antenna impedance has been modeled in Section. 3.1 as a complex impedanceconsisting of Rr, Rloss and XA. At the resonant frequency of the antenna, XAtends toward zero. For an ideal antenna when Rloss = 0, Rr represents theantenna impedance at its operating frequency. Rr is highly important as itaffects efficiency of antenna and VA. With the matching condition of Rr = Rin,the voltage gain at resonance is influenced by Rr in relation to Xin as was shownin Fig. 3.3. The value of Rr depends on the antenna type and design as will beexplained in the following section.

3.8.2 Antenna TypesPatch Antenna

Patch antenna (Fig. 3.24) consist of a typical PCB substrate metalized on bothsides while the bottom side is continuous plate and the top side is a patchrectangle fed via a microstrip [13, p.125]. Large directivity can be obtaineddue to the ground plane which acts as a reflector. This explains also how theradiation pattern is in semihemispherical form. A patch antenna is advantageousby its miniaturized size and circular polarization, but it is not optimal for thiswork because it has a single port rather than differential ports needed for thedefined RF-EH in this work.

Loop Antenna

Loop antenna is a metallic conductor bent into a closed curve of various shapeslike circular, square (Fig. 3.25), elliptical with a gap in this curve to formdifferential terminals. The main advantage in loop antenna is its small sizecompared with the wavelength in free space. It is used in different communicationapplications as a receiving antenna where the signal to noise ratio is mostly

71


PCB substrate

Patch

Ground plane

Fig. 3.24: Typical structure of PCB patch antenna.

PCB substrate

Loop antenna

Fig. 3.25: PCB square loop antenna.

considered rather than efficiency. The loop antenna efficiency is lower thanother antenna types because Rloss is higher than the radiation resistance Rr.However, this low Rr value makes loop antenna not desirable in this work as itis preferable to have moderate Rr value. The loop antenna is not optimum forwide frequency bandwidth performance because the quality factor is quite high(large inductance).

Dipole Antenna

In its most basic forms, the dipole antenna is composed of a piece of copperwire with a defined length of (λ2 ). The dipole is fed at the halfway along theantenna. The PCB dipole antenna can be realized on a PCB substrate as tworectangular arms hatched on the top layer without bottom ground layer. The

72


Dipole antenna

3-Wire folded dipole

antenna

2-Wire folded dipole

antenna

λ/2 λ/2 λ/2

Fig. 3.26: Dipole antenna realizations.

total length of the antenna is affected since the wavelength calculation is affectedby the effective dielectric constant of the substrate εeff of the PCB. The effectivedielectric constant is calculated as

εeff = ε+ 12 + ε− 1

2

1√1 +

(12 dsubstrateWdipole

) , (3.15)

where ε is the dielectric constant of the substrate material, the width of thecopper track Wdipole and the substrate thickness dsubstrate. The length of thedipole antenna, Ldipole, is determined as

Ldipole = λ

2 = C

2 f √εeff., (3.16)

where λ is the wavelength, C is the light speed and f is the frequency. However,factors like the gap between the microstrip arms of the dipole has to be takeninto account.For regular dipole realization, the radiation resistance Rr is less than 73W [13,p.122]. Therefore, it is easy to optimize the width Wdipole and the length Ldipolein order to set the antenna impedance to 50W at the resonance frequency. Itis possible to increase the radiation resistance using the 2-wire folded dipoleand 3-wire folded dipole, Fig. 3.26 shows the mentioned dipole realizations. Thebandwidth of the antenna relate inversely to the quality factor. Increasing theconductor width would decrease the inductance and quality factor consequentlygiving wider bandwidth.

3.8.3 Dipole Antenna ImplementationIt has been found by the extracted layout simulation that the real part of theinput impedance of the chip is 35W with input power of sensitivity. Consequently,

73


Table 3.2: Characteristics of the substrate used for antenna fabrication.Specification ValueSubstrate type FR4, two layersSubstrate thickness 1.55mmDielectric constant 4.1Copper thickness 35 umLoss tangent 0.013

the radiation resistance of the antenna should not be too low as in the loopantenna or too high as in the folded dipole antenna. The radiation resistanceof the standard dipole is sufficient regarding the input impedance of the chip.Moreover, it is possible to enhance the frequency bandwidth of the antennawith increasing the Wdipole. In order to make the measurements feasible withthe power source on one side and the spectrum analyzer on the other side, theantenna impedance is preferable to be settled to 50W. It is possible to fabricatethe dipole antenna using an economic FR4 substrate with acceptable efficiencyand gain. Therefore, standard dipole has been chosen to be implemented in thiswork.The antenna has been fabricated using typical FR4 substrate with the character-istics listed in Table. 3.2. The copper track width has been chosen to be 10mm inorder to increase the bandwidth. It is intended to use single board for measuringboth the RF and thermal energy harvesting systems. For center frequency fc of850MHz, the antenna length is quite long which leads to combining the antennawith the required lumped elements of both systems will make the size of thePCB to be extremely large. Instead of straight rectangular arms, the dipoleterminals have been bent to reduce the board length. The bending arcs havebeen enlarged to eliminate the influence of the track bend. The antenna has beendesigned for 50W impedance at center frequency of 850MHz. Fig. 3.27 showsthe layout and radiation pattern of the designed antenna.

3.9 Experimental Results Using The Dipole Antenna

The main board Board2 used for measurements is shown in Fig. 3.28 with sizeof (106× 105.3) mm2. It contains mainly the antenna, harvesting chip, matchinginductors and the output capacitor. The differential port of the antenna isconnected to the input pins of the chip using matching inductors. Another board(Dipole) has been fabricated with exactly similar dipole antenna and the SMAconnector only as shown in Fig. 3.29. This board is needed to measure the powerreceived at the harvester point.

74


Y

Z

X

(a) Laout of the designed dipole antenna.

Y

Z

X

(b) Radiation pattern of the degined dipole.

Fig. 3.27: Design of PCB dipole antenna.

75


Vout(C.P.)

VinDC

Matching network

CMOS Energy

Harvesting system

RTWO

106.05 mm

105.3

2 m

m

Fig. 3.28: Main board measurement Board2 of RF energy harvesting system.

107.58 mm

69

.68

mm

Fig. 3.29: Dipole Antenna realization using FR4 substrate.

76


800 820 840 860 880 900

−14

−12

−10

Frequency [MHz]

S11

[dB]

MeasurementSimulation

Fig. 3.30: Simulated and measured S11 parameter of dipole antenna.

3.9.1 Test Procedure

In order to determine the matching inductance, it is necessary to calibratethe antenna impedance while the input impedance of the chip is tested fromthe simulation. Once the matching network is given, the (Board2) is ready tomeasure the sensitivity of the system using the dipole antenna. The power istransmitted from the power source via the transmitting antenna (Dipole) tobe received by (Board2) at a certain distance. The output voltage is measuredacross the output capacitor at a certain distance from the transmitter and thetransmitted power Pt. In order to measure the system sensitivity, the receivedRF power Pin is measured using two (Dipole) boards.

3.9.2 Measurements of The S11 Parameters

Fig. 3.30 shows a comparison of S11 parameters between the simulations andmeasurements. The measurement results are close to that of the simulation withslight difference in the center frequency of the fabricated antenna of 820MHzwhile the center frequency of the simulated deign is 840MHz.

3.9.3 Sensitivity Measurement Using Dipole Antenna

Fig. 3.32 shows the received power Pr and the output voltage Vout versusfrequency at a distance of 1m for a transmitted power, Pt, of 6.5 dBm. Themaximum power received is around −21.5 dBm with an output DC voltage,Vout, of 2.6V at 820MHz which is close to the frequency at which minimum S11

77


1m

PrPt

Fig. 3.31: Measurements of RF energy harvester in Board2 at 1m distance fromthe transmitter.

parameters have been measured (Fig. 3.30). The matching is strongly alteredwith frequency leading to the input RF voltage, Vrec, changes with frequency aswell. This explains the sharp fluctuations in the output voltage. One more causefor this wobbling in the power received is the effects of indoor measurementenvironment (laboratory room).The RF energy harvester in (Board2) has been measured at distance of 9.2mfrom the transmitting antenna in indoor long corridor (Fig. 3.33). The outputDC voltage reaches 2.4V with power received of −23 dBm and frequency of850MHz while the transmitted power is (Pt = 20 dBm).

78


800 820 840 860 880 9000

1

2

Freqeuncy (MHz)

Vout(V

)

−35

−30

−25

−20

Pin

(dBm)

VoutPower received

Fig. 3.32: Measurements of RF energy harvester at a distance of 1m from thetransmitter and (Pt = 6.5 dBm).

9.2 m

Pt

Pr

Fig. 3.33: Measurements of RF energy harvester using Board2 at 9.2m distancefrom the transmitter.

79

Chapter 4

Low Input Voltage Boost Converter ForThermal Energy Harvesting

4.1 Thermoelectric Generator

The thermoelectric effect has two main effects within: the Seebeck effect, Peltiereffect. In 1821, Thomas Johan Seebeck found that a temperature differencebetween hot and cold junctions of different electrical conductors produces avoltage difference across them as shown in Fig. 4.1. This voltage difference relatesdirectly to the 4T between the junctions while the coefficient of a material ordevice to generate a voltage per unit of temperature is known as its Seebeckcoefficient, αS , with a unit of V/C. In 1834, Jean Charles Peltier discover thereverse effect. He found out that passing an electric current through a junction oftwo different conductors could cause it to act as a heater or a cooler dependingon the direction of the current. However, the solid state devices used accordingto Peltier effect can be used in temperature control applications. These devicesare called Peltier devices, while same devices can work reversely according toSeebeck effect and used nowadays in TE-H applications. The TEG is composedof a number of k semiconductor thermocouples are organized to create a serieselectrical connection and thermal parallel connection as shown in Fig. 2.7. Thetop and bottom of TEG is made of a material that can give an electrical insulationand thermal conductivity simultaneously. When a TEG is attached to the heatsource, a heat sink is necessary to be added to the cold side in order to keepthe temperature difference between hot and cold sides, otherwise, the entire

Th

+

FeFe

Cu

Tc

V

Fig. 4.1: The Seebeck effect principle.

81

Chapter 4 Low Input Voltage Boost Converter For Thermal Energy Harvesting

TEG would heat up to nearly same of Th temperature erasing the temperaturegradient [34].

4.1.1 Thermal and Electrical Model of the TEGThe thermal and electrical characteristics of the TE-H can be used to predictand simulate its behavior for a certain 4T . It is possible to build simple circuitsfor this purpose based on the TEG and the attached heat sink. In this section,the thermal and electric circuit models are reviewed briefly according to theliterature showing the effects of the related parameters on the produced powerDC.

Thermal Resistance Model

In reality, the actual 4T across the TEG junctions is lower than the totaltemperature gradient because of the thermal resistances of heat sinks residing onthe cold and the hot sides of the TEG represented by Rc and Rh, respectively.The thermal resistance is a measure of the temperature gradient by which anobject resist the heat flow. When a heat energy given to different materialsattached to each other, the biggest share of energy is utilized by material ofhigher thermal resistance. Fig. 4.2(a) shows that the thermal resistance of heatsink and TEG determine which portion of the total 4T is concentrated acrossthe TEG [34]. The actual temperature difference across the TEG sides is referredas 4TTEG to differentiate it from the total 4T and it is calculated as

4TTEG = 4T Rth.TEGRth.TEG +Rh +Rc

, (4.1)

where Rth.TEG is the thermal resistance of the thermoelectric generator. In orderto minimize the temperature drop across the heat sinks and thermal contacts,the TEG thermal resistance Rth.TEG should be as high as possible in comparisonwith Rc and Rh.

Electrical Model

The electrical behavior of TE-H can be simulated according to the Seebeck effect.The open-circuit voltage Voc across the terminals of the TEG is related to theSeebeck coefficient αS , number of thermocouples in the TEG used and 4TTEGas

Voc = nαS4TTEG = nαS (Th − Tc) . (4.2)When the TEG is connected to an input resistance Rin,boost as shown inFig. 4.2(b), electrical current passes through the circuit and it is determined as

Iin,rms = Voc(Rin,boost +Rs)

, (4.3)

82

4.1 Thermoelectric Generator

Rc

Heat source

Rth.TEG

Rh

Ambient temperature

ΔT ΔTTEG

(a) Equivalent thermal re-sistance of the heat sinksand the TEG.

Rs

Rinαs ΔTTEG VinVoc

TEG Load

(b) Eletrical model of the thermal system using thethermoelectric generator.

Fig. 4.2: Thermal and electrical modeling of the thermal energy harvester.

where Rs is the TEG internal electrical resistance based on the current-voltagecharacteristic. The DC power delivered to the connected load PTEG can becalculated as

PTEG = I2inRin,boost =

(Voc

(Rin,boost +Rs)

)2

Rin,boost . (4.4)

4.1.2 Choosing TEG Module For Thermal Energy HarvestingThe commercial off-the-shelf TEG modules vary significantly regarding theproduced electrical power with 4TTEG. The produced DC voltage from themodule for a certain 4TTEG depends mainly on the Seebeck coefficient of theTEG. It is possible to increase the open-circuit voltage Voc by increasing thenumber of the thermocouples but, this will increase the source resistance Rsresulting in higher voltage drop when the TEG is loaded. Such a trade-off isnoticed in the size of the module, i.e. larger harvester can give higher outputvoltage for a certain 4TTEG but its Rs is relatively large. Table. 4.1 lists some ofthe commercially available and recommended by [34]. The Voc of these modules is10mV/K to 50mV/K with typical source resistances Rs of 0.5W to 5W accordingto the TEG size.

83


Table 4.1: Commercial Off-The-Shelf TEG modules with part numbers andmanufacturers [34].

Manufacturer 15mm2 30mm2 40mm2

CUI INC(Distributor) CP60133 CP60333 CP85438FERROTEC 9501/031/030 B 9500/097/090 B 9500/127/100 BFUJITAKA FPH13106NC FPH17108AC FPH112708ACMARLOWINDUSTRIES RC6-6-01 RC12-8-01LSTELLUREX C2-15-0405 C2-30-1505 C2-40-1509TETECHNOLOGY TE-31-1.0-1.3 TE-71-1.4-1.15 TE-127-1.4-1.05

The maximum power supplied from the TEG is reached when the input resistanceis equal to the electrical resistance of the TEG. The circuit shown in Fig. 4.2(b)has been simulated with sweeping the input resistance, Rin,boost, using a constantopen-circuit voltage, Voc, of 10mV for different TEG resistances, Rs. It is clearby the simulation results (Fig. 4.3) that maximum power is delivered whenRin,boost = Rs. In opposite, it can be noticed that the input voltage, Vin, ishigher with higher input resistance, Rin,boost. However, higher input impedanceis associated with less input power.

4.2 Proposed DC-DC UP-Converter for Thermal EnergyHarvester

As it has been illustrated in the second chapter, the power conversion circuit isnecessary because the voltage produced from the harvester (TEG) is less thanthe supply voltage required to be applied to the load (sensor node). The outputsignal from the TEG is a DC signal leading to that DC-DC up-converter isneeded as a power conditioning circuit. The principles of DC-DC boost circuitdesign has been explained in details in Section. 2.4.2.Several solutions have been presented in literature to start up the convertersystem with minimum possible input voltage. The boost converter given by [19]is based on a self start up oscillator with the help of an SMT transformer towork with low input voltage. The system was able to start up with an opencircuit voltage of 20mV. Moreover, maximum efficiency is reached of 40% foran open-circuit voltage of 55mV. Similar principle has been adopted for startup the boost circuit in [17]. In later step, the system reuse the transformer

84

4.2 Proposed DC-DC UP-Converter for Thermal Energy Harvester

0 5 10 15 20 250

5

10

Rin,boost [W]

PTEG

[µW

]

Rs=2.5WRs=5WRs=10WRs=20W

Fig. 4.3: The power delivered from the TEG to the load as a functions to theinput resistance.

0 5 10 15 20 250

2

4

6

8

Rin,boost [W]

Vin

[mV]

Rs=2.5WRs=5WRs=10WRs=20W

Fig. 4.4: The available DC voltage from the TEG to the load as a functions tothe input resistance.

85


as an inductor based boost when the input voltage is high. Despite of higherefficiency reported of 60% at open circuit voltage of 300mV, the minimum startup voltage is 40mV. The converter system presented by [45] is based on usingcoupled inductors of 1:1 turn ratio instead of using SMT transformer with hightransformation ratio. This was helpful to minimize the switching losses due tothe transformer parasitic capacitance. This circuit was able to start up withminimum open circuit voltage of 21mV while maximum efficiency was 75% atan input power of 2mW. However, the maximum DC output voltage was limitedto 1V.The circuit is chosen and optimized according to the input voltage, Vin, which isexpected to be as low as the available power from the TEG (PTEG) as mentionedin Section. 2.5.1. The input resistance, Rin,boost, of the boost circuit mightbe preferable to be close to Rs in order to extract maximum power from thethermoelectric generator. However, this condition is not optimum for low opencircuit voltage Voc. This is because the input voltage to the boost will be half ofVoc giving that it will be challenging to start up the converter. Therefore, it isproposed to optimize the boost circuit to keep the Rin,boost is relatively higherthan Rs to obtain an accepted input voltage. This condition is only possiblewith minimum input current, Iin,rms, drawn into the converter circuit.

4.2.1 Transformer Reuse Self Start-Up Technique

The input voltage is unlikely to start up a regular boost converter. This is becauseof the limitation of the minimum supply voltage required for the driving signalcircuit. Consequently, the DC-DC work in two phases, the self start-up phaseand inductor based boost phase. The circuits associated with both operationphases will be explained in details in Section. 4.3 and Section. 4.4. The selfstart-up phase based on using a current sense SMT transformer to generate anoscillated AC signal spontaneously. The generated AC voltage is rectified by arectifying diode giving DC output voltage as shown in Fig. 4.5(a). In the secondphase, the circuit is switched to inductor based boost phase using the secondaryinductor of the transformer as shown in Fig. 4.5(b).The self start-up phase is necessary to initiate the circuit. However, it is associatedwith high power losses in comparison to the inductor based boost phase (as willbe discussed later in this chapter). During self start-up phase, when the inputvoltage, Vin, is high, the secondary voltage would be extremely high becauseof the high transformation ratio given by the transformer. Thus, the circuitsconnected to the secondary inductor might be damaged due to the extra highvoltage. On the other hand, it is possible to optimize the inductor based boostto give voltage conversion ratio higher than that given by self start up oscillator.Therefore, it is preferable to switch the operation phase to the inductor basedboost phase once the output DC voltage is high enough to run its related driving

86

4.3 Design of Self Start-UP Oscillator

Vin

Vout

Vprm

VsecSosc

Sboost

(a) Self start-up phase.

Vin

Vout

Vprm

VsecSosc

Sboost

(b) Inductor based boost phase.

Fig. 4.5: System operation phases.

circuit successfully. This principle result in enhancing the efficiency in the lowinput power range matching with scope of the work. It is proposed in this work toconsider the output voltage, Vout, as a measure to decide the switching betweenthe mentioned operation phases.The output voltage point at which the phase switching occurs is defined so thatthe inductor based boost increases the concurrent output DC voltage and power.Low power comparator circuit is necessary to decide the operation phase ofthe converter. The comparator is optimized to start up working with minimumsupply voltage enabling the comparator functioning during the self start upphase.


4.3.1 Self Start-Up Techniques

The self start up oscillator circuit is needed when the input voltage is extremelylow so that it is not able to power the DC-DC up converter. Instead of usingcharge pump or inductor based boost converters, simple oscillator is used togenerate an AC voltage which can be further processed via a rectifier or a voltagemultiplier circuit. In this section, the self start up oscillator circuit topologiesare reviewed including the advantages and drawbacks of every circuit.

87


VDD

Vosc

Ls Ls

RL,esr

CoscCosc Lp Rp Cosc

RL,esr

Fig. 4.6: Cross-coupled LC tank based self start up oscillator.

4.3.2 LC Based Start-Up OscillatorThis low voltage starter circuit is based on using LC tank oscillator. The circuitshown in Fig. 4.6 illustrate an LC oscillator with cross coupled NMOS transistors.Simply, the LC tank resonates at a frequency, fosc, given as

fosc = 12π√Ls Cosc

. (4.5)

In reality, the inductor is associated with series ohmic resistance, RL,esr, deter-mine its quality factor, Q,. The series resistance is modeled as a parallel resistor,Rp, calculated at resonance as [29, p.497]

Rp ≈L2s ω

2

RL,esr≈ LsRL,esr Cosc

withLp ≈ Ls . (4.6)

In order to minimize the V DD voltage required for oscillator, low thresholdvoltage or native NMOS transistors can used. The oscillation start up conditionis given in [48] as

V DD >4

Rp gm.n+ Vth.n ⇒ V DD >

4LsRL,esr (Cosc + Cp) gm.n

+ Vth.n , (4.7)

where the Cp is the parasitic capacitance of the native NMOS transistors. Theseries resistance, RL,esr, is small leading to the DC level of Vosc is close to the

88


supply voltage, therefore, the peak point of the oscillation voltage exceeds V DD.The circuit can be optimized properly to give peak to peak voltage swing largerthan V DD.Since the output voltage from the oscillator is still low, it needs a further voltagemultiplying circuit in order to produce an accepted DC voltage as shown inFig. 4.7. Such a conversion circuit is loaded to the oscillator while its inputcapacitance and resistance will affect the oscillation frequency as well as theconditional start up voltage. The voltage multiplying circuit can be optimizedso that wider devices are needed with large number of stages in order to avoidincreasing the load resistance of the oscillator. Moreover, the parasitic capacitancecan be effective, especially, when the NMOS transistors are enlarged to increasethe gm. Eq. 4.7 can be rewritten as

V DD >4Ls

RL,esr (Cosc + Cp + Cmv) gm.n+ Vth.n . (4.8)

where Cmv is the input capacitance of the voltage multiplier circuit. The sizesof coupling capacitors are reversely related to the oscillation frequency. Highfrequency is also relatively desired to decrease the minimum supply voltageneeded to start up the oscillator. High frequency on the other hand leads to highdynamic losses as mentioned in Section. 2.4.3. The main drawback in this methodis the need for conversion circuit associated with typical power losses. Anotherdrawback in using LC self start up oscillator is that it has low voltage conversionratio even with large number of voltage multiplier stages being added. For aninput voltage of 50mV, the output AC signal can be ranges from 100mV to150mV with proper design, but, this will need large number of voltage multiplierstages to reach an accepted output voltage.

4.3.3 Transformer Based Start-Up OscillatorThe transformer based oscillator consists basically of a common source amplifierloaded by an SMT transformer with a transformation ratio of NSMT as shownin Fig. 4.8(a). The polarity between the primary and the secondary transformerwindings can be used with the inverter amplifier to compose a positive feedbackloop. The noise signal generated at the gate of the NMOS transistor, Sosc, istranslated into a drain current passing through the primary inductor of thetransformer. Consequently, a primary voltage of Vprm is given across the primaryside of the transformer leads to a secondary voltage of (Vsec = NSMT Vprm) acrossthe secondary side. The Vsec is fed back positively to the Sosc giving higherdrain current and higher Vprm so that the generated AC voltage is maximizedby resonance. The oscillation frequency fosc is determined by

fosc = 12π√Lsec (Cse + Cgs + Cd)

. (4.9)

89


VDD

Vout

Lp Rp CoscLpRpCosc

AC

DCVosc

Rp Cosc Cmv CpLp

Fig. 4.7: Cross-coupled oscillator loaded with voltage multiplier circuit.

where Lsec is the secondary inductance of the transformer and Cse is the selfcapacitance of the secondary winding. The main condition to start up theoscillation is

Positive feedback loop gain > 1⇒ gm (Rp || Rg)N

> 1 , (4.10)

where Rp is calculated from the RL,esr of the secondary inductor in similar wayto that given in Eq. 4.6 and Rg is the resistive part of the input impedance ofthe transistor Sosc. The Rg can be effective for extremely wide transistors sothat it can influence the loop gain. On the other hand, the transconductanceincreases with the transistor width and the gate source voltage Vgs. There is atrade off with wider devices between high transconductance on one hand andlow quality factor

(fosc ∝ 1

Cgs

)and relatively low loop gain on the other hand.

In comparison with LC based start up oscillator, the transformer based oscillatoris advantageous by higher voltage conversion ratio and less power losses. Thetransformer based self start up technique given in Section. 4.3.3 is chosen to beused in this work to start up the DC-DC converter. As mentioned before, theSMT transformer is reused for inductor based boost once the output voltagereach a defined level. In order to reach the switching point with minimum Vinpossible, it is preferable to use a transformer with high transformation ratio inorder to obtain high output voltage in consequent. An SMT transformer hasbeen chosen with characteristics listed in table. 4.8As it was given in Eq. 4.10, high gm is necessary to minimize the start upinput voltage. Thus, the transistor, Sosc, has to be wide enough in order to

90


Vin Vout

Sosc

Vsec

Vprm

Cse

(a) Oscillator circuit.

Lsec Cse Cgs Cd-1/gmRp2 Rg

(b) Equivalent model LC combination withparasitic compnents.

Fig. 4.8: Transformer based self start up oscillator.

Table 4.2: Characteristics of the current sense transformer used for the boostconverter.Specification ValueManufacturer, MFG P/N Pulse electronics, P8208NLTurns ratio 1 : 100Secondary Inductance Lsec 2mHDC resistance of Lsec 5.5WParasitic capacitance Cse ≈ 46 pF

91


obtain high transconductance. Native NMOS transistor is not desirable becauseit has long channel length. It is associated with extreme large Cgs getting less Q.The leakage current is dominant in native devices, especially, with quite widedevices. Low threshold NMOS transistor is an alternative solution since it isadvantageous by less parasitic gate-source capacitance and less leakage current incomparison to the native transistor. When the converter switches to the inductorbased boost phase, the transistor Sosc has to be turned off, otherwise, high powerlosses are wasted via current passing through the primary inductor. Therefore,additional circuit is necessary to control the NMOS transistor Sosc according tothe operation phase.Low threshold PMOS transistor is proposed in this work to build a positivefeedback loop as shown in Fig. 4.5(a). The PMOS transistor is turned offautomatically once the converter switches to inductor based boost so that nocontrol circuit is needed. The bulk terminal can be connected to the outputvoltage increasing the threshold voltage and reducing the leakage current.The transformer based self start up oscillator has been designed using CMOSUMC 0.13 um technology. Wide low threshold PMOS transistor has been usedwith minimum channel length. Diode connected standard PMOS transistor hasbeen used for rectifying the generated AC signal.In order to simulate the oscillator circuit, the TEG is modeled as DC voltagesource connected with series resistance of (Rs = 2.5 Ω) as an average of thesource resistances of the typical commercial TEG modules. A Large capacitor of100 uF is connected across the input terminal of the converter. The big capacitorserves as an RF bypass to ground and supply a smooth input voltage to theconverter. The simulation results shows that the oscillator can start up with anoscillation frequency of 434MHz for open circuit voltage Voc of 10mV.

4.3.4 Negative Voltage Rectifier

The boost switch, Sboost, is preferable to be wide enough to draw high currentinto the boost converter and to obtain an accepted power transfer from thesource to the load. Even when the gate voltage of the boost switch is grounded,the leakage current is still dominant. This is because the device is quite largewith wide width. The leakage current influence the oscillation start up negatively,especially, with low input voltage. It is proposed to bias the boost switch with anegative voltage during the self start up phase. Voltage rectifier is fed by thesecondary voltage Vsec in order to obtain a negative DC voltage. The rectifierconsists of two stages voltage doubler circuit built with standard PMOS devicesas shown in Fig. 4.10.

92


0 0.5 1 1.5 2

−500

0

500

Time [ms]

Volta

ge[m

V]

VsecVout

Fig. 4.9: Simulation results of the self start up oscillator with Voc = 10 mV.

Vsec

Vneg

Fig. 4.10: Negative voltage rectifier using PMOS transistors.

93


4.4 Design of Low Power Inductor Based Boost Circuit

The inductor based boost is optimized so that the power consumption of thedriving circuits is minimum. This will enable a switched operation mode withminimal input voltage. For the same purpose, the boost circuit is designed to givehigh voltage conversion ratio. According to Eq. 2.23, (D2 Ts = 1−D1 Ts) has tobe quite narrow. However, such a condition is possible only with low switchingfrequency. The pulse generating circuit and its following buffer circuits will sufferfrom undesired high power losses with high fs as given in Section. 2.4.3.For an open circuit voltage of around 30mV, the boost can be optimized toobtain a high conversion ratio

(VoutVin≈ 100⇒ D1 = 0.99

). The output voltage

can reach 2V taking into account effects of the parasitic components given inSection. 2.4.3. Low switching frequency with low IL.average lead to bidirectionallosses unless high inductance is used as given in Eq. 2.30. The principle of theSMT transformer reuse technique is based on reusing secondary winding in theinductor based boost circuit. The Lsec is 2mH as given in table. 4.2. Assumingthe load resistance, Rload, is high in the range of 100 kW, the switching frequencyfs required to avoid bidirectional losses is

fs >D1 (1−D1)2 Rload

2Lsec= 0.99 ∗ 0.012 ∗ 100 ∗ 103

2 ∗ 2 ∗ 10−3 ⇒ fs > 8 kHz . (4.11)

The switching frequency fs is chosen to be 10 kHz. The boost driving circuitconsists of the secondary inductor of the transformer, the boost switch Sboost,oscillator, pulse signal generator and its following driving inverters as shown inFig. 4.11.

4.4.1 Ring Oscillator CircuitThe driving clock signal can be produced using ring oscillator. The switchingfrequency has been given (10KHz). In comparison with the ring oscillator givenin Section. 3.5.2, the switching frequency is quite low. More inverter stages withlonger CMOS devices is needed to obtain low fs. Instead of biasing the oscillatorusing low voltage reference generator, the proposed oscillator for the boostconverter is biased using low power current reference circuit shown in Fig. 2.15.This current reference circuit is optimum for the proposed boost because thesupply voltage (Vout) is expected to reach high voltage levels of 3V.Standard CMOS devices has been optimized to be extremely long (L = 25 um)in order to decrease the oscillation frequency while 17 stages are used for thesame reason. The peak-peak voltage of the produced clock signal from the biasedoscillator Vclk.low is low in the range of 250mv. Therefore, another biased inverter(Inv.clk) is used as an amplifier following the oscillator, as shown in Fig. 4.12, inorder to give the clock signal Vclk with peak-peak voltage equal to the supply

94

4.4 Design of Low Power Inductor Based Boost Circuit

Vin

Vprm

VoutVsec

Sboost

VclkVfil terVpulse

OscillatorH.P.F.

Fig. 4.11: Driving circuit of the inductor based boost.

voltage. The NMOS transistor in the inverter Inv.clk has been sized equal tothe PMOS transistor because of the low voltage of the input signal Vclk.low.The principle of the biasing circuit is explained including simulation results inSection. 2.3.2. It keeps the oscillation frequency constant with supply voltagewhile the current drawn by the oscillator and (Inv.clk.1) is kept constantly low aswell. Fig. 4.13 and Fig. 4.14 shows the simulation results of the peak-peak voltageof the clock signal and the fs, respectively, with the supply voltage increasing.The clock signal is equal to the supply voltage while the clock frequency startwith 9.5KHz at 0.21V and reaches 10.2KHz at 3.3V.

4.4.2 Pulse Signal GenerationThe boost switch Sboost is driven by the pulse signal Vpulse. It has been proposedto generate the pulse signal by passing the clock signal through a passive highpass filter as shown in Fig. 4.15. It is possible to optimize the resistance, Rfilter,and the capacitance, Cfilter, in this simple filter circuit to control the durationof the pulse signal. The resistor is designed to a high value of around 0.5MW(integrated resistor) to reduce the power consumed in the resistor. Thus, the pulsewidth is determined by the value of Cfilter. For a switching frequency of 10 kHzand a voltage conversion ratio of

(V2V1≥ 100

), the duration of D2 = 0.01Ts ≈ 1 us

is needed. A metal-insulator-metal MIM capacitor has been used with size of(Cfilter = 1 pF). The high pass filter is followed by three inverters so that thegiven signal by the filter is reproduced giving a pulse signal with the desired

95


Vclk.lowVclk

Oscillator

VDD

Biasing

Inv.osc.

Inv.clk

6 um

25 um

3 um

25 um

Fig. 4.12: Clock signal generator circuit.

0 10 20

0

1

2

3

Time [ms]

Volta

ge[m

V]

V DD

Vclk

Fig. 4.13: Simulation results of the biased oscillator circuit for supply voltagechange with time.

96

4.5 Control Circuit

0 1 2 3

9.6

9.7

9.8

9.9

VDD [V]

Freque

ncy[K

Hz]

Fig. 4.14: Simulation results of the fs for supply voltage change with time.

duty cycle. Fig. 4.16 and Fig. 4.17 shows the simulation results of the producedsignal by the filter Vfilter and the pulse signal Vpulse for supply voltage of 2V.

4.5 Control Circuit

As has been mentioned in Section. 4.2 that a comparator circuit is needed todetermine if the converter operates in start up phase or inductor based boostphase. In addition to the comparator circuit, the control circuit includes theinterface circuit needed to control the boost switch Sboost. The designs of thesescircuit are explained in details in this section includes the simulation results.

4.5.1 Low Power Comparator Circuit

Low power comparator circuit is needed to measure the output voltage Voutgiving the control signals Vcomp,1 and Vcomp,2 accordingly. When the voltage Voutis less than a reference level referred as Vboost, the signals Vcomp,1 and Vcomp,2states are low and high, respectively. When the output voltage becomes higherthan the defined reference level, the signals Vcomp,1 and Vcomp,2 change to highand low respectively. The voltage Vboost is determined so that the inductor isable to increase concurrent output voltage. It has been found by simulation thatminimum supply voltage required for such condition is around 0.7V.

97


Vclk Vfil ter Vpulse

VDD

V

t

Fig. 4.15: Pulse signal generator circuit.

Differential Amplifier Circuit

The output voltage of the converter, Vout, is compared with a reference voltageVboost = 0.7 V using a differential amplifier. The main obstacle to the design ofdifferential amplifier in this application is that the supply voltage is one of thedifferential input signals to the differential PMOS transistors. Consequently, theconnected PMOS transistor to the supply voltage (Vout) is switched off. There aresome solutions have been presented for such problems like the differential amplifiercircuit given in [27] and shown in Fig. 4.18. In this circuit, the differential inputsignals are fed to the bulk terminals of the PMOS transistors pair. When thesupply voltage exceeds the defined reference voltage, the output signal switchesfrom low to high. However, this circuit is not suitable for high supply voltagesand relatively low reference voltage levels. This is because the bulk biasing ofthe PMOS transistor will decrease the threshold voltage as given in Eq. 3.7 andincrease the drain current and power consumption dominantly.Instead of measuring the output voltage directly, it is proposed to scale it downby a certain factor to be compared with a reference voltage. In comparisonto the reference voltage Vboost = 0.7 V, low reference voltage, Vref.low, for theproposed amplifier is used. Therefore, it will be possible to use typical differentialamplifier using differential PMOS transistors, Mp.in1, and, Mp.in2, as shown inFig. 4.19(b). The amplifier circuit is biased using the biasing circuit given inFig. 2.15 to ensure stable performance with supply voltage. The biasing PMOStransistor is biased in subthreshold region and its drain-source voltage is highso that the source voltages of the input transistors pair is low. Thus, the input

98

4.5 Control Circuit

140 160 180 200 220 240 260

−1

0

1

Time [us]

Volta

ge[V

]

Fig. 4.16: The output signal of the high pass filter for an input clock signal of10 kHz.

140 160 180 200 220 240 2600

1

2

Time [us]

Volta

ge[m

V]

Fig. 4.17: The pulse signal generated for input clock signal of 10 kHz.

differential signals should be low in order to avoid switching PMOS transistors,Mp.in1, and, Mp.in2, off.

Generation of Differential Signals

A division of the output voltage referred as, Vout.div., is extracted using ultra lowpower voltage divider circuit. This circuit is built by a series of diode connectedstandard PMOS transistors. The Vout.div. is measured across the the last diodegiving quite low voltage. This reduces the sensitivity to the process variations asthe voltage will be affected by a single diode rather than multiple diodes. Forthe same reason, the Vout.div., is less affected by the current-voltage nonlinearbehavior of the CMOS devices.Low reference voltage, Vref.low, is given in contrast to Vout.div.. The principles oflow power reference circuits have been given in Section. 2.3.3. The circuit givenin Fig. 2.19 can be used to generate Vref.low because it is sufficient to producelow reference voltage.

99


VDD

Vamp.

Vref.

Vbias

Fig. 4.18: Bulk input differential amplifier given in [27].

The scale factor in the voltage divider circuit and the reference voltage aredefined so that the output signal of the amplifier referred as Vamp. gets down atsupply voltage of 0.7V. The voltage divider circuit has been built by 12 diodesMp.d1...Mp.d10 optimized so that (Vout.div. ≈ (Vout/10)). On the other hand, theNMOS transistors Mn1 and Mn2 has been optimized to produce a referencevoltage of 25mV.For Vout.div > Vref.low, the converter switches to the inductor based boostphase. The boost takes a while to work properly while the output voltagedecreases slightly to be less than the defined, Vboost, during this time duration.Consequently, the output signal from the comparator oscillates as well as theoperation phase of the converter and the output voltage stopped at Vout =Vboost ≈ 0.7 V. In order to avoid this oscillation, an adaptive reference circuit issuggested so that the reference voltage, Vref.low, becomes lower after switchingwhile the control signals, Vcomp,1, and, Vcomp,2, are kept unchanged. Fig. 4.19(c)shows the suggested reference voltage circuit. When the control signal, Vcomp,1,changes to high state, the transistor Mn,adaptive is switched off and the drawncurrent into the transistor Mn2 and the reference voltage are both decreased(see Fig. 4.19(c)).

Output Stage Circuit

When the supply voltage exceeds the Vboost level, the output signal of thedifferential amplifier Vamp. changes from low state to high state but, it is stillless than V DD and not sharply skewed as desired. The output stage is neededin order to generate a nearly digital control signals. The output stage consists ofbiased inverter amplifier followed by two inverters Inv.1comp and Inv.2comp asshown in Fig. 4.20. The biased inverter circuit will amplify its input signal Vamp.while the control signals Vcomp,1 and Vcomp,2 are given by the inverters Inv.1comp

100

4.5 Control Circuit

VDD

Vout.div

Mp.d1

Mp.d11

Mp.d12

(a) Voltage dividercircuit.

VDD

Vamp.

Vref.low

Vbias

Ibias

Vout.div

Mbias

Mp.in1 Mp.in2

(b) Differential pair amplifier.

Mn2

VDD

Vref.low

Vcomp,1

Mn,adaptiveMn1

(c) Adaptive low voltage refer-ence circuit.

Fig. 4.19: Amplifier circuit with differential signals generation circuits.

and Inv.2comp respectively. Additional RC circuit is placed between theses twomentioned inverters in order to absorb any undesired signals generated from thesupply voltage when the inductor based boost starts working. This will eliminatethe influence of such undesired signals on the control signal Vcomp,2.

4.5.2 Driving Multiplexer Circuit

As has been explained in Section. 4.3.4, in order to minimize the leakage currentdrawn into the boost switch, Sboost, during start up phase, the gate terminal ofthis NMOS switch is biased by the negative voltage, Vneg., generated from thenegative voltage rectifier. During the inductor based boost, the Sboost is drivenby the pulse signal generated from the pulse signal generator. This requiresa driving multiplexer circuit to interchange the gate connection according tothe operation phase. Fig. 4.21 shows the proposed (2× 1) multiplexer circuitcontrolled by the the signal, Vcomp,2, generated from the comparator.The negative voltage is given through the NMOS switch Sneg controlled by thesignal Vcomp,2. The pulse signal, on the other hand, is given through the PMOSswitch Sp,pulse controlled by the control signal Vcomp,2 and the NMOS switchSn,pulse controlled by the signal Vinv,cont which is given by the inverter Inv.cont.When the signal Vcomp,2 is high, the switch Sneg is turned on and the negative

101


Vcomp,2

VDD

Inv.1comp Inv.2comp1pF

Vcomp,1

Vbias

Vamp.

Fig. 4.20: Output stage of the comparator.

voltage is applied to the Sboost. The PMOS switch Sp,pulse is turned off with theVcomp,2 is high. The source terminal of the NMOS device in the inverter Inv.contis connected to the source terminals of the switch, Sneg, so that the output signal(Vinv,cont = Vneg) and the switch Sn,pulse is turned off. Thus, the converter isoperated in the start up phase. When the signal Vcomp,2 is low, the switch Snegis turned off while the PMOS switch Sp,pulse is turned on. The signal Vinv,contgoes high so that the NMOS switch Sn,pulse is turned on. Consequently, thedriving pulse signal Vpulse is applied to the boost and the converter is operatedin the inductor based boost. The block diagram of the whole boost convertercircuit including the control circuit is shown is in Fig. 4.22.

4.5.3 Simulation Results of The Control Circuit

The DC-DC up converter circuit has been simulated with open circuit voltage(Voc = 30 mV and source resistance of (Rs = 2.5 Ω) in order to evaluate thecircuit behavior and control signals during the start up and the inductor basedboost phases. The Figures:(Fig. 4.24, Fig. 4.25 and Fig. 4.26) show the simulationresults of the signals given by the comparator circuit: Vout.div, Vref.low, Vamp.,Vcomp,1 and Vcomp,2. These signals are generated in response to the outputvoltage (Fig. 4.23) as has been explained in Section. 4.5.1. It can be seen thatthe control signals Vcomp,1 and Vcomp,2 are reversed at (Vout = 0.72 V) and theconverter switches to the inductor based boost. The output voltage is slightlydecreased until the boost works properly. Once the signal Vcomp,1 goes high,the reference voltage Vref.low decrease from 25mV to 15mV so that the outputsignals of the comparator are kept unchanged.Simulation results of the output signal of the driving multiplexer circuit Vmux is

102


VoutVsec

Sboost

Vneg

Vpulse

Vcomp2

Sneg

Sp.pulse

Sn.pulse

Inv.cont

VInv,cont

Vmux

Tipple well NMOS

transistors

VDD

Fig. 4.21: The suggested multiplexer circuit to drive the switch Sboost.

shown in Fig. 4.28. The driving pulse signal is applied to the switch Sboost whenthe control signal Vcomp,2 changes from high state to low state. The negative DCvoltage produced from the negative voltage rectifier is shown in Fig. 4.27. It canbe seen that the rectified negative DC voltage contains large ripple voltage. Thisis because the output capacitor of the negative voltage rectifier is quite small.


The proposed boost converter circuit has been taped out using CMOS UMC0.13 um technology. Various CMOS devices types have been used in the convertercircuits like the standard transistors, high threshold transistors, low thresholdtransistors and triple well NMOS transistors.The low threshold PMOS transistor Sosc has been sized to be quite wide (3mm)in order to guarantee the oscillation start up with low input voltage. However,increasing the size of this switch is limited by the available chip area. On theother hand, increasing the width of the transistor Sosc will increase the drawncurrent into the converter Iin,rms and decreases the input impedance Rin,boost.As explained in Section. 4.2, the input impedance is proposed to be higher thanthe source impedance in order to keep the input voltage within an acceptedrange. On the other hand, the size of the NMOS switch Sboost is also limitedwith the available chip area.The size of the MIM capacitor used in the negative voltage rectifier have been

103


Vout

Neg

ativ

e v

olt

age

rectifi

er

Pulse generation

circuit

Vmux

VpulseVneg

Vcomp,1Vcomp,2

MUX

Ref.

circuit

Vo

ltag

e d

ivid

er

Vin

Vprm

Vsec

Vref,low

Vout,div

Comparator

Sboost

Sosc

Fig. 4.22: Block diagram of the proposed boost converter circuit.

0 2 4 60

1

2

Time [ms]

Volta

ge[V

]

Fig. 4.23: The output voltage for an open circuit voltage of 30mV.

104


0 2 4 60

0.05

0.1

0.15

Time [ms]

Volta

ge[V

] Vout.divVref.low

Fig. 4.24: The differential input signals to the amplifier circuit.

0 2 40

0.2

0.4

Time [ms]

Volta

ge[V

]

Fig. 4.25: The output signal of the differential amplifier circuit.

0 2 4 60

1

2

Time [ms]

Volta

ge[V

] Vcomp,1Vcomp,2

Fig. 4.26: The output signals of the comparator circuit.

105


0 2 4 6

−0.6

−0.4

−0.20

Time [ms]

Volta

ge[V

]

Fig. 4.27: The negative DC voltage generated from the negative voltage rectifier.

0 1 2 3−1

0

1

2

Time [ms]

Volta

ge[V

]

Fig. 4.28: The output signal of the driving multiplexer circuit.

106

4.7 Experimental Results

Low input voltage boost

converter

Fig. 4.29: Micro-graph of multiple block chip with a total area of 1.6× 1.6mm2

containing the boost converter system.

minimized to 0.5 pF. Despite of the large ripple voltage in the rectified negativeDC voltage, Vneg, it is sufficient to eliminate the leakage current of the boostswitch Sboost during the start up phase. The sizes of the capacitor used in the highpass filter in signals generation circuit and and low pass filter in the comparatorcircuit have been optimized according to the desired signals characteristics likelow power consumption and the duty cycle of the pulse signal D1. On the otherhand, the capacitor CLPF in the low pass filter inside the comparator circuithave been optimized to 1 pF to absorb the noise signals coming from the supplyvoltage. The layout area of the proposed converter is shown in Fig. 4.30, theoccupied area is (270× 270) mm2 within total area of (1.6× 1.6) mm2 multipleblocks including the RF energy harvesting system given the third chapter. Asmentioned in Section. 3.6, the chip chip is packaged in a 48-pin QFN packagewith 0.5mm pin pitch.


The PCB boards Board1 and Board2 mentioned in Section. 3.7 and Section. 3.9,respectively, has been used to test the low input voltage boost converter. Theinput power is supplied to the chip from DC power supply connected in seriesto a resistor of 2.5W in order to model the thermoelectric generator TEG (SeeSection. 4.3). Large capacitor of 100 uF is placed in parallel to the input pin

107


Biased oscillator Pulse generation circuit

Negative voltage

rectifier

Sboost

Biasing circuitSosc

Reference circuit 270 um

270 um

Differential Amplifier

Voltage divider circuit

L.P.F.

Fig. 4.30: Layout of the proposed low input-voltage boost circuit.

of the on chip converter in order to construct in combination with the sourceresistance Rs a low pass filter. This filter absorbs the undesirable ripple in theinput voltage Vin. On the output side, the SMD capacitor Cout (100 nF) isconnected to the output pin of the converter. Fig. 4.31 shows the test boardcontaining the fabricated chip, SMT transformer and other SMD mentionedcomponents.

4.7.1 Test Procedure

The chip verification is composed of two parts: start up phase and inductorbased boost phase. The open circuit voltage Voc is increased from 0V in orderto reach minimum Voc required to start up the converter. As the DC sourcevoltage supplied by the DC power supply is further increased, the output voltageincreases as well until reaching the switching point Vout = Vboost ≈ 0.7 V. Atthis point, the converter is operated in inductor based boost phase. The outputcapacitor is connected to a variable load resistance Rload in order to measure theoutput power, efficiency and the output voltage according to the given sourcevoltage.The board has been connected to a small TEG module from CUI INC withsize of (15× 15 mm2) in order to proof the ability of the presented converter towork properly in a practical application. The test bench used to measure the

108


CMOS low input voltage

boost converter

106.05 mm

10

5.3

2 m

m

SMT

transformer

Cout

Vout

Vsec

Vin

Fig. 4.31: Test board of the CMOS boost converter.

low input voltage converter is shown in Fig. 4.32.

4.7.2 Measurements of Minimum Start-Up Input Voltage

The hot side of the thermoelectric generator module has been attached to aheating plate which is used as heat source. The residual heat is radiated viaa heat sink with low thermal resistance. As the temperature of the heatingplate is increased, the open circuit voltage is increased as well until reaching theminimum source voltage required to start up the converter. The measurementsshow that the minimum open circuit voltage given by the TEG module to startup the converter is less than 10mV. Fig. 4.33 show the measurements of opencircuit voltage before connecting the TEG to the chip and the rectified outputDC voltage from the boost converter. The chip has been measured with DCpower supply and an equivalent source resistance of 2.5W in order to proofthe system ability to work with a wide range of the TEG modules which arecommercially available.The measurements show that the converter can start up with minimum sourcevoltage of 12mV giving an output DC voltage of 0.48V (see Fig. 4.34). Themeasured drawn current Iin,rms at the start up voltage is less than 0.5mA while

109


DC Power

supply

Vin

Vout

V1

Vsec

2.5 Ω

100uF

Voc

Sboost

Cout Rload

Sosc

LsecLprm

CMOS low input voltage

boost converter

SMT

Transformer

(1:100)

Fig. 4.32: The measurement test bench of the low input-voltage boost converter.

the input voltage Vin is 11mV. The input impedance is quite higher than theequivalent Rs.

4.7.3 Measurements of The Converter In The Inductor-Based Boostphase

As the source voltage is increased, the output voltage Vout increases until reachingthe switching point. The measurements results show that the converter switchesfrom the start up phase to the inductor based boost phase at Vout = 0.75 Vwith source voltage Voc = 30 mV. The measurement shows that the oscillationfrequency during the start up phase is 440 kHz close to that found by simulationwith 434 kHz. Both simulation and measurement results are given while theinput impedance of oscilloscope (15 pF ‖ 1 MΩ) is connected to the secondaryinductor (see Fig. 4.32).Once the switching occurs, the output voltage becomes 2.7V for the same sourcevoltage of 30mV. Maximum output power can be obtained by varying the loadresistor Rload. Fig. 4.35 shows the maximum power conversion efficiency achievedand the associated output DC voltage with the source voltage ranging from30mV to 100mV. The maximum achieved efficiency is 35% at source voltage of35mV while the associated output voltage is 1.9V. This matches with the scopeof this project to achieve best characteristics with low input power.

110


Fig. 4.33: Measurement of start-up voltage of the converter connected to theTEG.

20 40 60 80 100

1

2

3

Voc [mV]

Vout[V

]

Vout

Fig. 4.34: Measurements of output voltage of the converter.

111


40 60 80 100

26

28

30

32

34

Voc (mV)

Efficien

cy(%

)

50

100

Outpu

tpo

wer

(uW

)

EfficiencyPout

Fig. 4.35: Measurements results of output power and efficiency.

112

Chapter 5

Conclusions and Outlook

5.1 Conclusions

The aim of the achieved research in this thesis is to present CMOS circuit designsthat enable energy harvesting in challenging conditions like low power availablefrom the harvester as well as low input voltage. In this work, a highly sensitiveRF energy harvesting system and low input voltage DC-DC boost converter forthermal energy harvesting have been presented.The RF energy harvesting system consists of differential input cross coupledrectifier and low power charge pump. The rectifier has been designed withhigh input reactance in order to maximize the RF input voltage by resonance.Moreover, the rectifier has been optimized to be able to drive the charge pump.The suggested circuits of the low-voltage oscillator and the low-voltage referencegenerator contributed effectively to minimize the power consumption and thestart-up voltage of the charge pump. Consequently, the rectifier is able to drivethe charge pump even when the RF input power is low.The measurement results show that the calibrated system sensitivity to producemore than 1V for a capacitive load is −25 dBm within a frequency range of800MHz to 870MHz. Furthermore, a dipole antenna using an economical FR4substrate has been fabricated in order to prove the design concept with a realantenna rather than using an RF power source. The best sensitivity of the RFenergy harvesting system is −25 dBm at 820MHz using the dipole antenna. Itcan be concluded by the measurement results that using the charge pump ishelpful to maximize the DC output voltage for low RF input power with widebandwidth.The performance of the presented RF energy harvesting system in this thesisis sufficiently acceptable in comparison with literature as shown in Table. 5.1.The sensitivity measurement is slightly less than that given in [41] and [35]. Inopposite, the presented design is able to work with wider frequency bandwidth.Furthermore, the harvesting systems in [35] and [41] require off chip controlloop (to control the input impedance) and off chip capacitors (for low frequencycharge pump). In contrast, the power conversion system presented here is fullyintegrated.Low input voltage CMOS boost converter consists of self start-up oscillator,

113

Chapter 5 Conclusions and Outlook

Table 5.1: Performance comparison to the state-of-the-art of RF energy harvest-ing systems.

Parameter This work Stoopman -2014 [41]

Hameed -2015 [15]

Salter -2009 [35]

Technology UMC130 nm

TSMC90 nm

IBM130 nm

IBM130 nm

Die area 0.25mm2 0.029mm2 0.25mm2 NaFrequency (800 to

870) MHz- (902 to

928) MHz2.2GHz

Frequencyusingantenna

810 to 830)MHz

868MHz - -

Requirement Deep n-well Off chipcontrolloop

- Off chip ca-pacitor

Sensitivity −25 dBm,Rload ≈ ∞

−27 dBm,Rload ≈ ∞

−20.5 dBm,Rload =1 MΩ

−25.5 dBm,Rload ≈ ∞

max. Vout 5V atPin =−9 dBm

3V atPin =−15 dBm

5VatPin =−5.8 dBm

1.5V atPin =−23.5 dBm

Efficiency - 40% atPin =−17 dBm

32% atPin =−15 dBm

-

114

5.2 Outlook

inductor-based boost and control circuit. The self start-up oscillator has beendesigned to be able to start up with minimum possible voltage and maximumpossible input impedance. The measurements show that the boost can start upwith an open circuit voltage of less than 10mV using typical TEG module givinga DC output voltage of 0.48V. The inductor based boost has been optimizedto give high voltage conversion ratio while its driving circuits are driven bylow supply voltage. The suggested pulse signal generation circuit minimized therequired supply voltage and the power consumption. For control circuit, lowpower circuits like low current biasing, the adaptive reference generator, thelow power comparator and the driving multiplexer circuit have been presented.These circuits contributed successfully to control the converter operation withminimum power consumption.It has been found by measurements that the converter can start up for an opencircuit voltage of 12mV with source resistance of 2.5W as an average for thesource resistances of the commercially available TEG modules. Besides, whenthe inductor based boost circuit is activated, the output voltage is raised from2V to 2.9V for open circuit voltage range of 30mV to 100mV with an averageefficiency of 31%. It can be seen from the measurements that the proposedconverter design is optimum for thermal energy harvesting applications of lowinput voltage.Table. 5.2 shows a comparison with the state-of-the-art regarding the low inputvoltage boost converter. The minimum input voltage of the achieved designin this work is less than those reported in literature. The produced outputvoltage is higher than those given in the mentioned designs. Furthermore, themeasured efficiency with an input voltage range of 30mV to 100mV is acceptablein comparison to the previously published converters.The power management circuits which have been designed in this thesis matchwith aim of work to provide successful energy conditioning with minimum possiblepower losses. The presented designs gave solutions to overcome the challengingconditions of low power available from the harvester as well as low input voltage.Consequently, the electrical power produced from the harvester can be usableeven when the distance between the RF transmitter antenna and the harvestingsystem is long (in RF energy harvesting), or when the temperature differenceacross the TEG module is quite low (in thermal energy harvesting).

5.2 Outlook

The measurement results of the presented designs match the targets of the thesis,yet, it is still possible to make these designs more efficient for wide range of inputpower. Mainly, the given solutions concentrates on working with low power whileit was found that performance is not increasing with high input power.

115


Table 5.2: Performance comparison to the state-of-the-art of low input voltageboost circuits.

Parameter This work LTC3108 -2010 [19] ,Industrialapplication

Jong-PilIm - 2012[17]

Teh - 2014[45]

Technology UMC 130 nm na 130 nm 130 nmMinimumVoc

10mV 20mV 40mV 21mV

Max. Vout 2.9V 2.35V, 5V 2V 1VPeak effi-ciency

31% at Voc =30 mVto100 mV

40% atVoc =55 mV

61% atVoc =300 mV

74% forPin =2 mW

Max. Pout 130 uW atVoc = 100 mV

600 uWat Voc =500 mV

2.7mWat Voc =300 mV

1.5mW atVoc = 1 V

MPPT no no yes yes

For the RF energy harvesting system, the parasitic capacitance of the padsdecreases the input reactance massively and decreases the RF voltage gain byresonance. The sensitivity can be improved by using smaller pads. When theRF input power increases , the rectified voltage from the rectifier can be higherthan 1V. Consequently, the rectifier output terminal can be connected directlyto the output capacitor instead of the charge pump based boost converter. Thisgives the possibility to obtain high efficiency with high input power. This can bemanaged using low power comparator with two switches as shown in Fig. 5.1.The comparator is optimized so that its output signal is switched from high tolow at certain input power level when the rectified voltage Vrec,DC is higher than1V. Furthermore, since the the input impedance is varying with input power,an adaptive matching network will be helpful to guarantee maximum powermatching for wide range of RF input power. The adaptive matching network canbe realized using variable capacitor or switched capacitors that are connected inparallel to the input terminals.For the boost converter design, it is possible to increase the output voltageduring the start-up phase using multistage rectifier instead of single diode. Therectifier can be switched off when the converter changes to inductor based boost.Off chip capacitors might be needed for this suggestion because the oscillationfrequency is low so that large capacitors will be required.Furthermore, additional maximum power point tracking (MPPT) circuit will be

116

5.2 Outlook

Ref.


Vrec

Antenna

Vrec,DC DC

DC

Vout

CP

CMOS integrated RF

energy harvesting system

Matching

adapter

Fig. 5.1: Suggested RF energy harvesting system for future works.

helpful to increase the efficiency and guarantees maximum power transfer fromthe source to the converter. The duty cycle of the driving pulse signal can bechanged by changing the capacitance of the high pass filter. Switched capacitorsare suggested to be controlled by the MPPT circuit according to the inputvoltage. It is possible to increase the output power during the inductor-basedboost phase by increasing the width of the boost switch. A rectifying diode withwider width is preferable to decrease the conduction losses.

117

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Curriculum VitaeName Durgham Al-ShebaneeDate of birth 09.19.1980Place of birth Muthanna, Iraq

Education

10.2004 – 07.2007 M.Sc. in electronic engineering, , field of microwavetechnology. Department of electrical and electronicengineering, university of technology, Baghdad - Iraq

10.1999 – 09.2003 B.Sc. in electronic engineering, Department of electri-cal and electronic engineering, university of technology,Baghdad - Iraq

09.1995 - 09.1999 Secondary school, Samawah secondary school,Muthanna - Iraq

Professional Experience

since 10.2011 Research assistant (Full time PhD Student) in thechair of Integrated Analog Circuit and RF systems inRWTH Aachen University, Germany

03.2008 - 06.2011 Tutor assistant in Muthanna University and an engi-neer in Muthanna University Bureau for scientific andengineering consultation, Muthanna - Iraq

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