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CMOS Differential Logic Family For Low Power Application

1Amal Jyothi College Of Engineering

CHAPTER 1

INTRODUCTION

In this paper, a set of CMOS differential logic circuits are introduced for low power

applications. They perform a conditional operation for statistical power reduction in logicoperations. The measurement results indicate that the counter with the proposed logic

family achieves 50% power reduction compared with conventional logic family. Among

many components contributing to overall power consumption, the switching power

component, which is caused by charging and discharging internal capacitive nodes is a

dominant part. Since, the amount of switching power consumption linearly depends on the

operating clock frequency, minimising this type of power component will become a very

important issue in next generation SoCs.

1.1 LOGIC FAMILY

A logic family may refer to one of two related concepts. A logic family of monolithic

digital integrated circuit devices is a group of electronic logic gates constructed using one of

several different designs, usually with compatible logic levels and power supply

characteristics within a family. Many logic families were produced as individual components,

each containing one or a few related basic logical functions, which could be used as

"building-blocks" to create systems or as so-called "glue" to interconnect more complex

integrated circuits.

A "logic family" may also refer to a set of techniques used to implement logic

within large scale integrated circuits such as a central processor, memory, or other complex

function. Some such logic families, such as Complementary Pass-transistor Logic, use static

techniques to minimize power consumption. Other such logic families, such as domino logic,

use clocked dynamic techniques to minimize size, power consumption, and delay.

1.2 DIFFERENT LOGIC FAMILY

y Diode logic ( DL)y Direct-coupled transistor logic (DCTL)y Resistortransistor logic (RTL)y Resistor-capacitor transistor logic (RCTL)y Diodetransistor logic (DTL)y Emitter coupled logic (ECL) also known as Current-mode logic (CML)

o Positive emitter-coupled logic (PECL)o Low-voltage positive emitter-coupled logic (LVPECL)

y Transistortransistor logic (TTL) and variantsy P-type metaloxidesemiconductor logic (PMOS)y N-type metaloxidesemiconductor logic (NMOS)y Complementary metaloxidesemiconductor logic (CMOS)y Bipolar complementary metaloxidesemiconductor logic (BiCMOS)y Integrated injection logic (I2L)

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style with CMOS usescomplementary and symmetrical pairs of p-type and n-type metal oxide

semiconductor field effect transistors (MOSFFTs

Cfor logic functions

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CMG H

Differential Logic Family For Low Power Application

3Amal JyothiCollege Of Engineering

Two important characteristics ofCMOS devices are high noise immunity and low

static power consumption. Significant power is only drawn when the transistors the CMOS

device are switching between on and offstates.Consequently,CMOS devicesdo not produce

as much waste heat as other forms of logic, for example transistor-transistorlogic (TTL) or

NMOS logic, which uses all n-channeldevices without p-channeldevices.CMOS also allowsa high density of logic functions on a chip. It was primarily this reason why CMOS won the

race in the eighties and became the most usedtechnology to be implementedinVLSI chips.

The phrase "metaloxidesemiconductor" is a reference to the physical structure of certain

field-effect transistors, having a metal gate electrode placed on top of an oxide insulator,which in turn is on top of a semiconductor material. Aluminium was once used but now the

materialis poly silicon.

Besides these static CMOS logic circuits there are also dynamic CMOS logic circuits

that have some advantagesin certain circumstances.

STATICCMOS

The principle ofstatic CMOS logic isshown in Fig: the outputis connectedto ground

through an n-block andto through a dual p-block. Without changes ofthe inputsthis

gate consumes only the leakage currents ofsome transistors. When itisswitching itdraws anadditional current which is neededto charge anddischarge the internal capacitances andthe

load. Although the gate'slogic function isideally independent ofthe transistor channel

widths,they determine the dynamic behaviour essentially: widertransistors willswitch a

capacitive load faster, butthey will also cause a largerinput capacitance ofthe gate. Unless

otherwise noted, minimum-width and, of course, minimum-channel-length transistors are

assumed. For given capacitancesthe transistors' on-state current willlimitthe switchingspeed ofthe gate and, consequently,the maximum clock frequency of a synchronous circuit

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Static-CMOS NAND gate with three input

Two other important parameters determining the speed are the so-called fan-in which is the

number of inputs of a gate, and the fan-out which is the number of unity loads

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(i.e., inputs I connected to a gate's output. For a static-CMOSNAND gate asshown in Fig.

Fin=3,means that three transistors areconnected in series, which is roughlyeP

uivalent to one longer

transistor which can conduct on lon/Fin=Ion/3. Theeffect ofFout is an Fout-fold load capacitance.

Thiscould lead to the assumption that the gate delay is is proportional to bothFin andFout.

However, thesituation is morecomplex. Another fact to beconsidered is that a large fan-in will

degrade the normalized noise margins if the transistor sizesW

are not adapted accordingly.

One way to improve speedisto make the outputlesssensitive to the capacitive load

by inserting a buffer asshown in Fig. Note thatthe input must be inverted andthe logic

blocks must be replaced by theirdualsin orderto perform the same logic function

F(x)=FT(x).

2.2DYNAMICCMOS

As an example, consider firstthe static logic implementation of a NAND gate (here in

CMOS):

This circuitimplementsthe logic function

IfA andB are both high,the output will be pulledlow, whereasif one ofA andB are

low,the output will be pulled high.Mostimportantly,though, at alltimes,the outputis

pulled eitherlow or high.

The advantages ofthistype oflogic are thatthe inputs are connected only to NMOStransistorsso thatthe inputload capacitance is much smaller. Therefore,dynamic logic is

fasterthan static CMOS. Furthermore, for complex functionsthe transistor countis almosthalved. The big disadvantages ofthistype oflogic isthe need for repeated charging and

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COMPLEMENTARY CMOS LOGIC

Complementary CMOS logic is composed of pull-up and pull-down networks. The pullup and pull down networks are duals of each other. Each networkis composed of NAND

(series connection) and/or NOR(parallel connection)functions. Pull up networkis connected

to supply voltage, whereas pulldown network is connected to the ground.Separate input is

given to pull up and pulldown networks. The outputistaken from the junction of pull up and

pullsdown networks. The advantage ofthis circuitisthatthere is no static powerdissipation.

EXAMPLE: NORGATE

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Complementary CMOS logic can be implemented with the hel p of an example(NORgate).The Boolean function ofthe NORgate is given by

Y =A+B

The pulldown network performsthe NORoperation which is given by

PDN=A+B

i.e.it act as a parallel NMOS

PUN performsthe dual operation of PDN i.e., PUN performsthe NAND operation.

PUN =PDN=A+B=A.B

i.e.it act as a series PMOS

CMOS AS AN INVERTER

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In CMOS circuits, p-type and n-type metaloxidesemiconductor field-effect transistors

serve as pull-down and pull-up elements. StandardCMOS logic gates are constructed with a

network of PMOS transistors connecting the output to thepositive supply and a network ofNMOS transistors connecting the outputto the negative supply (or ground,typically);the two

networks are generally designed to be complementary, in the sense that the output will also

we pulled high or low, and not both at once. Thus CMOS can be thought as a system

combining NMOS and PMOS subcomponents. The composition of a PMOS transistor creates

low resistance when a low gate voltage is applied and high resistance when a high gate

voltage is applied, and the NMOS the other way around. This duality allows obtaining the

most elementary logic gate NOT by connecting the input to both a PMOS transistor and anNMOS transistor.

OPERATION

Ifthe voltage of input A is low,the NMOS transistor has high resistance so itstops voltagefrom leaking into ground, while the PMOS transistor has low resistance so it allows the

voltage source to transfer voltage through the PMOS transistor to the output. The outputwouldtherefore register a high voltage.

When the voltage of input A is high, the PMOS transistor would have high resistance so it

would block voltage source from the output, while the NMOS transistor would have low

resistance allowing the outputto drain to ground. This would resultin the output registering alow voltage. In short, the outputs of the PMOS and NMOS transistors are complementary

such that when the input is low, the output would be high, and when the input is high, theoutput would be low. Because ofthis,the CMOS circuits' outputis by defaultthe inversion of

the input.

In the transition region, where the input voltage is halfthe supply voltage, both the transistorsconduct;they operate in active mode andthe whole circuit behaves as an inverting amplifier

with very high gain. The two transistors may be thought as two voltage-driven currentsources (current-stable resistors) that are connected in series and are driven by opposite-

varying complementary input voltages. They try to set the desired current magnitudes bychanging significantly their present resistances in opposite directions. As a result of this

interaction,the output voltage changessignificantly;the gain is high andthe transition zone

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is narrow. From this viewpoint, each of the two transistorsserves as an active load for theother one.

SYSTEM ON CHIP (SoC)

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System on chip (SoC OR SOC) refersto integrating all components of a computer or other

electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-

signal, and often radio-frequency functionsall on one chip. A typical application is in the

area of embeddedsystems.

Microcontrollerstypically have under 100K ofRAM (often just a few Kbytes) and often

really aresingle-chip-systems; whereasthe term SoCistypically used with more powerful

processors, capable of running software such as Windows or Linux, which need externalmemory chips (flash,RAM) to be useful, and which are used with various external

peripherals. In short, forlargersystemsSU steV -oW -a-chipis hyperbole,indicating technical

direction more than reality: increasing chip integration to reduce manufacturing costs andto

enable smallersystems.

A typical SoC consists of:

y One microcontroller, microprocessor or DSXcore(s

Y. SomeSOCscalled multiprocessor

System-on-Chip (MPSoC) include more than one processor core.

y Memory bloc s including a selection of ROM, RAM, EEPROM and Flash.y Timing sources including oscillators and phase-loc

aed loops.

y Peripherals including counter-timers, real-time timers and power-on reset generators.y External interfaces including industrystandardssuch as USB, FireWire, Ethernet, USART, and

SPI.

y Analog interfaces including ADCs and DACs.y Voltage regulators and power management circuits.These blocks are connected by either a proprietary orindustry-standard bussuch astheAMBA bus from ARM. DMA controllers route data directly between externalinterfaces

and memory, by-passing the processor core andthereby increasing the data throughput ofthe SoC

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Microcontroller-based System-on-a-Chip

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TEC NIQUE 1: PSEUDO NMOS

It is employed to eliminate pull up network. Here clock input is given only to pulldown network. Pulldown network can be implemented using any gate.

Pseudo NMOS logic uses fewertransistors as only the NMOS logic blockis neededto

create the logic. For N inputsit requires N+1 FETS. The basic topology of a pseudo NMOSgate isshown in the figure.

The single PMOSFET is biased active since the grounded gate gives gate voltage is

equalto the supply voltage. It acts as a pull up device thattriesto pullthe outputto the power

supply voltage. Logic is performed by the PDN network.

The pseudo-NMOS logic must be ratio sensitive so as to minimize the loss in powerdissipation. In other words,the PMOS must be weak orsmallso asto have less capacitance

associated with the device. In this configuration, the charge will be pulled up much moreslowly by the PMOS than it can be discharged through the NMOS devices. In this way, a

pull-down path to groundthrough the NMOS logic blockshould easily pulldown the output.When no pull-down path to ground exists via the NMOS logic,the outputisthen pulled high

through the PMOS load. Although pseudo-NMOS logic can be utilizedto reduce the numberof PMOS components in the system, not only does the static power dissipation serve as a

detriment, butthe speed ofthe circuitislimited by the time necessary forthe weak PMOS tocharge up the output node

BENEFITS

1. Substantial reduction in input capacitances-fasterspeed

ISSUES

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1. Static powerdissipation.

2. Asymmetric propagation delays (falling edge faster).

TECHNIQUE 2: DCVSL

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s

DCVSL stands for differential cascade voltage switch logic. CVSL provides dual-raillogic gatesthat have latching characteristics buildinto the circuit itself. The output results f

and f are held untilthe inputsinduce a change. A DCVSL isshown ion the above figure.

The circuit consists of 2 PMOS transistors and 2 PDN networks. The 2 PMOSFETS areconnectedto the supply voltage whereasthe 2 PDN networks are grounded. The inputs given

to the 2 PDN networks are complements of each other. The logic tree is modeled as a pair ofcomplementary switchessuch that one is closed while the otheris open asdetermined by the

BENEFITS

1. Fasterspeed2. No static powerdissipation3. It provides much lowerinput capacitance forthe same output current4. It provideslowerswitching threshold5. It also increases the performance when there are interdependencies among

the minterms of a logical expression

ISSUES

1. Slowerthan Pseudo NMOS requires more powerthan ComplementaryCMOS

2. Data switching activity islow3. It cannot be used with a global clock having voltage swing lessthan supply

voltage

APPLICATION

1. Natural choice forthe implementation oftiming-criticallogic functionsinSoCs

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TECHNIQUE 3: DYNAMIC LOGIC CIRCUIT

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Dynamic logic gate uses clocking and charge storage properties ofMOSFETsto implementlogic operations. The clock provides a synchronized data flow which makes the technique

usefulin designing sequential networks. The characterizing feature of a dynamic logic gate isthatthe result of calculation is valid only for a short period oftime.

This circuit consists of two transistors, PMOS and NMOS.The PMOS transistor is

connected to the supply voltage, whereas NMOS transistoris connected to the ground. Theclock drives a complementary pair oftransistors. The clocking signal definestwo distinct

modes of operation during every cycle. When =0, the circuit is in precharge with PMOStransistor on and NMOS transistor off. This establishes a conducting path between supply

voltage andthe output. The PMOS transistoris called pre charge FET.

A clocktransition to =1 drivesthe circuitinto evaluation mode where PMOS is off and

NMOS is on. NMOS transistoris usually calledthe evaluate transistor.

BENEFITS

1. The elimination of the complimentary PMOS transistors significantly reduces thesurface area needed to implement the various logic functions not only because the

physical number oftransistors is nearly cutin half, but because the physicalsizeof the

PMOS transistorstendto be much largerthan the size of an NMOS transistor.2. The switching speeds are also increased using the dynamic logic configuration since the

speed bottleneck caused by the lengthiertime the PMOS requiresto pull-up the outputnode is eliminated. Since this node is already precharged high through the PMOS during

the precharge phase,the output node needs only to be selectively dischargedduring the

evaluation phase. Discharging the output node through the NMOS devices is

significantly fasterthan the time neededto charge up the output node through the PMOS

device.3. No static powerdissipation4. Less number of components

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ISSUES

1. The basic dynamic CMOS logic configuration causes the output node to bedisconnected from VDD during the evaluation phase, even if the output is also

disconnected from GND, the charge of the output node will begin to diminish due tothe non-ideal effects of the system.

2. Parasitic capacitances, for example, may leak the charge away from the output nodeand eventually cause a logic error. Since there is, a finite time needed for the charge to

erroneously escape, the use of faster the clockspeeds will eliminate this kind of error.This implies that there is a minimum clock speed at which dynamic CMOS logic

structures may be operated.

3. It also eliminates the possibility to idle the basic dynamic CMOS logic circuit.4. High design complexity.5. Cascading requires care.

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PROBLEM ENCOUNTERED IN THE DESIGN OF DYNAMIC CMOS

Other characteristics ofdynamic CMOS logic that must be taken into consideration whendesigning dynamic logic are the problems that can occur when cascading the dynamic logic

blocks. Due to the finite pull down time of the NMOS logic block,during the ver y firstportion of the evaluation phase, the output will always register an output high state for at least

a brief moment in time before the output charge can be removed via the pull-down path toGND. This is considered a racing problem since the logic is evaluated correctly only when

the time to pull down the output node is faster than the time needed for the briefly high outputcaused by the precharge phase to propagate as an erroneous logic signal to the next stage.

Since the output node of one dynamic CMOS logic block is connected to an input of the next

dynamic CMOS stage, an output high state however brief could complete a pull-down path to

GND in the following stage and erroneously cause a discharge in the output of this next

stage. Since the charge on the output node cannot be recovered until the next precharge

phase, the logic error would remain and propagate through the system. Dynamic CMOS logic

blocksshould therefore not be directly cascaded. Note that care must also be taken to insure

that the input logic signals to the NMOS logic block are correct andstable for the complete

duration of the evaluation stage or a similar logic error could occur.

The errors occurring due to cascadeddynamic logic blocks can be overcome by adding aninverterstage between the output of one stage and the input of another (see Fig. 9).

This inverter then would start out low at the very beginning of the evaluation phase.

The output low state of the inverter would cutoff the NMOS logic gates in the next

stage preventing any erroneous pull-down path. If a pull-down path is formed by the

NMOS logic block of the first stage, the output of the inverter buffer would

conditionally charge from low to high. Only if the inputs to the first stage NMOS logic

block warrant a discharge of the output node would the output inverter make the low tohigh transition. When the output of this inverter buffer goes high, the following stage

of NMOS logic would conditionally form a pull-down path to ground. In this way, the

addition of the inverter buffer eliminates any logic errors caused by the finite pull-

down time of the NMOS logic block. This kind of design is referred to as DominoLogic since the pull-down of one stage can conditionally cause the pull-down of

succeeding stages and so on like falling dominoes. The number of Domino Logicstages that may be cascaded is limited only by the sum of the total pull-down times in

all cascaded logic blocks which must be contained within the evaluation clock phase.

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Drawbacks to this design are of course the addition of two additional components toeach dynamic block. Extra design consideration must also be observed when using

dynamic CMOS logic blocks in conjunction with static CMOS logic blocks. Since thefinal output to the Domino logic blocks is the inverted form of the origonal output due

to the additional inverter buffer stage, only non-inverting logic may be used between

the output and input ofdynamic logic. That is,since the inverter must make only one

conditional state change from logic low to high (not high to low) during the evaluationphase only an even number of static logic blocks may be used in between dynamic

logic blocks.

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CHARACTERISTICS OF CMOS

1. Low power consumption 10 nw per gate2. Propagation delay 25ns to 50 ns3. Controlled rise time4. Noise immunity5. Temperature range - -55 to 1250c

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COMPARISON

CMOS TTL

1. Simple 1. Complex

2. Cheaper in fabrication 2. Costlier in fabrication

3. Small in size 3.Large in size

4. Consumes less power 4.More power

5. Fabrication is easy 5.Difficult

6. Lesss pace on chip 6.More space

7.

Low operating speed 7.High speed

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CONCLUSION

In this paper, a set of CMOS differential logic family isdesigned for low power applications.

It discusses about the three techniques namely, pseudo NMOS, DCVSL (differential cascade

voltage switch logic), dynamic logic circuits. Each of these techniques is having its own

advantages and disadvantages. The dynamic logic circuit is found to provide better low

power design. This type of logic is of great interest because it can provide striking

improvements in switching speed.

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REFERENCE

1. Introduction to VLSI Circuits and Systems by John P Uyemura.

2. VLSI circuits by Botkar

3. CMOS circuits layout anddesign by R.Jacob Baker,

Harry w.Li,

David.e.Bayce

4. IEEEjournals

5. IEEE website

6. http://www. Google.com

7.http://www.wikipedia.com

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