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Intel Corporation
Page 84 - ITRS 2011 Edition Executive Summary
http://www.itrs.net/Links/2011ITRS/2011Chapters/2011ExecSum.pdf
Power
Delivery
Verification
Becoming a
Significant
Issue!!
Impact on Power Grid verification
Current Density
Wire Resistivity
Database Size
IR Drop Analysis Time
Complexity of Analysis and
Debug
Operating Voltages
Multi voltage Domains
Moore’s Law
Full-chip
Sections
Partitions
Stdcells Memories
Full Chip Layout hierarchy
Flat-IR Method of
Power Grid verif ication Limitations
Large runtime
Huge memory consumption
Difficult to Debug
Need
Overnight runtime
Lesser Compute need
Same accuracy as Flat-IR
Methodology Summary
Partitions IR analysis done separately
Obtain via currents for partition
Select via layer (HVCOM via) to be modeled
Create Current sources at HVCOM via
Create DEF only for layers above HVCOM via
FC IR done with the partition HVCOM DEF files
H VCO M M et h o do l o gy H i e r a r c h i c a l V i a C u r r e n t O v e r r i d e M o d e l
Features, Assumptions
Upper and lower layers converge separately
Uniform grid resistance profile assumed
Random current density assumed
Not applicable for custom power grids
HVCOM Model for Graphics IP IR Drop Analysis
Fullchip has abutting sections
Sections have abutting partitions
Partitions contain stdcells and memories
Hierarchical Method From Vendor
Partit ion Abstract Model (PAM)
Library &
technology Full-chip IR drop analysis
IR s imulat ion Data
Library &
technology Partition IR drop analysis
IR s imulat ion
Data
Partition-1
Abstract View
Library &
technology
Full chip IR drop
analysis
IR s imulat ion Data
Partition-1
Abstract View Partition-N
Abstract View
Accuracy, Compute
Via Current
Computation
Partition-1 HVCOM
View
Partition-1
HVCOM
View
Partition-2
HVCOM
View
Partition-N
HVCOM
View
Fu l l Ch ip IR
s imulat ion
Data
Data Prep Analysis
- Power Calc
- PG Extract
- Static IR Run
- Power Calc
- PG Extract
- Full Chip Static IR Run
Library &
technology
~3x faster 61% less memory 99.9% accurate HVCOM
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