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Contents

CHAPTER 1 INTEGRATED-CIRCUIT DEVICES AND MODELLING 1

1.1 Semiconductors and pn Junctions 1 1.1.1 Diodes 2 1.1.2 Reverse-Biased Diodes 4 1.1.3 Graded Junctions 7 1.1.4 Large-Signal Junction Capacitance 9 1.1.5 Forward-Biased Junctions I 0 1.1.6 Junction Capacitance of Forward-Biased Diode II 1.1.7 Small-Signal Model of a Forward-Biased Diode 12 1.1.8 Schottky Diodes 13 MOS Transistors 14 1.2.1 Symbols for MOS Transistors 15 1.2.2 Basic Operation 16 1.2.3 Large-Signal Modelling 21 1.2.4 Bodx Effect 24 1.2.5 p-Channel Transistors 24 1.2.6 Low-Frequency Small-Signal Modelling in the Active Region 25 1.2.7 High-Frequency Small-Signal Modelling in the Active Region 30 1.2.8 Small-Signal Modelling in the Triode and Cutoff Regions 33 1.2.9 Analog Figures of Merit and Trade-offs 36

1.3 Device Model Summary 3 8 1.3.1 Constants 38 1.3.2 Diode Equations 39 1.3.3 MOS Transistor Equations 40

1.4 Advanced MOS Modelling 42 1.4.1 Subthreshold Operation 42 1.4.2 Mobility Degradation 44 1.4.3 Summary of Subthreshold and Mobility Degradation Equations 4 7 1.4.4 Parasitic Resistances 47 1.4.5 Short-Channel Effects 48 1.4.6 Leakage Currents 49

1.5 SPICE Modelling Parameters 50 1.5.1 Diode Model 50 1.5.2 MOS Transistors 51 1.5.3 Advanced SPICE Models ofMOS Transistors 51

1.6 Passive Devices 54 1.6.1 Resistors 54 1.6.2 Capacitors 58

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Contents

1.7 Appendix 60 1.7.1 Diode Exponential Relationship 60 I. 7.2 Diode-Diffusion Capacitance 62 * ... ~~--- 1.7.3 MOS Threshold Voltage and the Body Effect

_____. 1.7.4 MOS Triode Relationship 66 64

;..~~ ~ 1.8 Key Points 68 1' 1.9 References 69

CHAPTER 2

CHAPTER 3

1.10 Problems 69

PROCESSING AND LAYOUT

2.1 CMOS Processing 73

2.2

2.3

2.4

2.5 2.6 2.7

2.1.1 The Silicon Wafer 73 2.1.2 Photolithography and Well Definition 74 2.1.3 Diffusion and Ion Implantation 76 2.1.4 Chemical Vapor Deposition and Defining the Active Regions 78 2.1.5 Transistor Isolation 78 2.1.6 Gate-Oxide and Threshold-Voltage Adjustments 81 2.1.7 Polysilicon Gate Formation 82 2.1.8 Implanting the Junctions, Depositing Si02, and Opening

Contact Holes 82 2.1.9 Annealing, Depositing and Patterning Metal, and Overglass

Deposition 84 2.1.1 0 Additional Processing Steps 84

CMOS Layout and Design Rules 86 2.2.1 Spacing Rules 86 2.2.2 Planarity and Fill Requirements 94 2.2.3 Antenna Rules 94 2.2.4 Latch-Up 95 Variability and Mismatch 96 2.3.1 Systematic Variations Including Proximity Effects 96 2.3.2 Process Variations 98 2.3.3 Random Variations and Mismatch 99 Analog Layout Considerations 103 2.4.1 Transistor Layouts I 03 2.4.2 Capacitor Matching I 04 2.4.3 Resistor Layout I 07 2.4.4 Noise Considerations I 09 Key Points 113 References 114 Problems 114

BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS

3.1 3.2 3.3

Simple CMOS Current Mirror 118 Common-Source Amplifier 120 Source-Follower or Common-Drain Amplifier 122

73

117

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Contents xiii

3.4 Common-Gate Amplifier 124 3.5 Source-Degenerated Current Mirrors 127 3.6 Cascode Current Mirrors 129 3.7 Cascode Gain Stage 131 3.8 MOS Differential Pair and Gain Stage 135 3.9 Key Points 138 3.10 References 139 3.11 Problems 139

CHAPTER 4 FREQUENCY RESPONSE OF ELECTRONIC CIRCUITS 144

4.1 Frequency Response of Linear Systems 144 4.1.1 Magnitude and Phase Response 145 4.1.2 First-Order Circuits 14 7 4. 1.3 Second-Order Low-Pass Transfer Functions with Real Poles I 54 4.1.4 Bode Plots 157 4.1.5 Second-Order Low-Pass Transfer Functions with Complex Poles 163

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Frequency Response of Elementary Transistor Circuits 165 4.2.1 High-Frequency MOS Small-Signal Model 165 4.2.2 Common-Source Amplifier 166 4.2.3 Miller Theorem and Miller Effect 169 4.2.4 Zero-Value Time-Constant Analysis 173 4.2.5 Common-Source Design Examples 176 4.2.6 Common-Gate Amplifier 179

Cascode Gain Stage 181 Source-Follower Amplifier 187 Differential Pair 193 4.5.1 High-Frequency T-Model 193 4.5.2 Symmetric Differential Amplifier 194 4.5.3 Single-Ended Differential Amplifier 195 4.5.4 Differential Pair with Active Load 196

Key Points 197 References 198 Problems 199

CHAPTER 5 FEEDBACK AMPLIFIERS

5.1 Ideal Model ofNegative Feedback 204 5.1.1 Basic Definitions 204 5.1.2 Gain Sensitivity 205 5.1.3 Bandwidth 207 5. 1.4 Linearity 207 5.1.5 Summary 208

5.2 Dynamic Response of Feedback Amplifiers 208 5.2.1 Stability Criteria 209 5.2.2 Phase Margin 211

204

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xiv Contents

CHAPTER 6

5.3

5.4

5.5 5.6 5.7

First- and Second-Order Feedback Systems 213 5.3.1 First-OrderFeedbackSystems 213 5.3.2 Second-Order Feedback Systems 217 5.3.3 Higher-Order Feedback Systems 220

Common Feedback Amplifiers 220 5.4.1 Obtaining the Loop Gain, L(s) 222 5.4.2 Non-Inverting Amplifier 226 5.4.3 Transimpedance (Inverting) Amplifiers 231

Summary ofKey Points 235 References 235 Problems 236

BASIC OPAMP DESIGN AND COMPENSATION 242

6.1

6.2

6.3

6.4

6.5 6.6 6.7

6.8 6.9 6.10 6.11

Two-Stage CMOS Opamp 242 6.1.1 Opamp Gain 243 6.1.2 Frequency Response 245 6.1.3 Slew Rate 249 6.1.4 n-Channel or p-Channel Input Stage 252 6.1.5 Systematic Offset Voltage 252

Opamp Compensation 254 6.2.1 Dominant-Pole Compensation and Lead Compensation 254 6.2.2 Compensating the Two-Stage Opamp 255 6.2.3 Making Compensation Independent of Process and Temperature 259

Advanced Current Mirrors 261 6.3.1 Wide-Swing Current Mirrors 261 6.3.2 Enhanced Output-Impedance Current Mirrors and Gain Boosting 263 6.3.3 Wide-Swing Current Mirror with Enhanced Output Impedance 266 6.3.4 Current-Mirror Symbol 267

Folded-Cascade Opamp 268 6.4.1 Small-Signal Analysis 270 6.4.2 Slew Rate 272

Current Mirror Opamp 275 Linear Settling Time Revisited 279 Fully Differential Opamps 281 6.7.1 Fully Differential Folded-Cascode Opamp 283 6.7.2 Alternative Fully Differential Opamps 284 6.7.3 Low Supply Voltage Opamps 286

Common-Mode Feedback Circuits 288 Summary of Key Points 292 References 293 Problems 294

CHAPTER 7 BIASING, REFERENCES, AND REGULATORS 302

7.1 Analog Integrated Circuit Biasing 302 7.1.1 Bias Circuits 303

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7 .1.2 Reference Circuits 305 7.1.3 Regulator Circuits 306

Establishing Constant Transconductance 307 7 .2. I Basic Constant-Transconductance Circuit 307 7 .2.2 Improved Constant-Transconductance Circuits 309

Establishing Constant Voltages and Currents 310 7 .3.1 Bandgap Voltage Reference Basics 3 I 0 7.3.2 Circuits for Bandgap References 314 7.3 .3 Low-Voltage Bandgap Reference 319 7.3.4 Current Reference 320

Voltage Regulation 321 7.4.1 Regulator Specifications 322 7 .4.2 Feedback Analysis 322 7.4.3 Low Dropout Regulators 324

Summary ofKey Points 327 References 327 Problems 328

CHAPTER 8 BIPOLAR DEVICES AND CIRCUITS

8.1

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Bipolar-Junction Transistors 331 8. 1.1 Basic Operation 331 8.1.2 Analog Figures of Merit 341 Bipolar Device Model Summary 344 SPICE Mooeling 345 Bipolar and BICMOS Processing 346 8.4.1 Bipolar Processing 346 8.4.2 Modern SiGe BiCMOS HBT Processing 347 8.4.3 Mismatch in Bipolar Devices 348

Bipolar Current Mirrors and Gain Stages 349 8.5.1 Current Mirrors 349 8.5.2 Emitter Follower 350 8.5.3 Bipolar Differential Pair 353

Appendix 356 8.6.1 Bipolar Transistor Exponential Relationship 356 8.6.2 Base Charge Storage of an Active BJT 359 Summary ofKey Points 359 References 360 Problems 360

CHAPTER 9 NOISE AND LINEARITY ANALYSIS AND MODELLING

1Cl Time-Domain Analysis 363 9.1.1 Root Mean Square (rms) Value 364 9.1.2 SNR 365 9.1.3 Units ofdBm 365 9.1.4 Noise Summation 366

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9.2 Frequency-Domain Analysis 367 9.2.1 Noise Spectral Density 367 9.2.2 White Noise 369 9.2.3 1/f, or Flicker, Noise 370 9.2.4 Filtered Noise 371 9.2.5 Noise Bandwidth 373 9.2.6 Piecewise Integration ofNoise 375 9.2.7 1/fNoise Tangent Principle 377

9.3 Noise Models for Circuit Elements 377 ...ltiJ. /9.3.1 Resistors 378 1'\ K'i( 9.3.2 Diodes 378

9.3.3 Bipolar Transistors 380 9.3.4 MOSFETS 380 **'If- 9.3.5 Opamps 382 9.3.6 Capacitors and Inductors 382 9.3.7 Sampled Signal Noise 384 9.3.8 Input-Referred Noise 384

~1{( 9.4 Noise Analysis Examples 387 ~ 9.4.1 Opamp Example 387

9.4.2 Bipolar Common-Emitter Example 390 9.4.3 CMOS Differential Pair Example 392 9.4.4 Fiber-Optic Transimpedance Amplifier Example 395

9.5 Dynamic Range Performance 397 9.5.1 Total Harmonic Distortion (THO) 398 9.5.2 Third-Order Intercept Point (IP3) 400 9.5.3 Spurious-Free Dynamic Range (SFDR) 402 9.5.4 Signal-to-Noise and Distortion Ratio (SNDR) 404

9.6 Key Points 405 " 9.7 References 406

9.8 Problems 406

CHAPTER 10 COMPARATORS 413

10.1 Comparator Specifications 413 1 0.1.1 Input Offset and Noise 413 1 0.1.2 Hysteresis 414

10.2 Using an Opamp for a Comparator 415 1 0.2.1 Input-Offset Voltage Errors 417

10.3 Charge-Injection Errors 418 I 0.3.1 Making Charge-Injection Signal independent 421 10.3 .2 Minimizing Errors Due to Charge-Injection 421 l 0.3.3 Speed of Multi-Stage Comparators 424

10.4 Latched Comparators 426 1 0.4.1 Latch-Mode Time Constant 427 1 0.4.2 Latch Offset 430