Post on 22-Jul-2020
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S. Bernardi, S. Lebailly - Texas InstrumentsB. Blanc, G.Berry, J.Dormoy - Esterel Technologies
Villeneuve-Loubet - France
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HIGH LEVEL SYSTEM DESIGN p 2
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HIGH LEVEL SYSTEM DESIGN p 3
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HIGH LEVEL SYSTEM DESIGN p 4
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Esterel is a KLJK�OHYHO�ODQJXDJH dedicated to synchronous hw and embedded sw programming.Esterel Studio tool provides an HQYLURQPHQW� IRU� SURJUDP� FDSWXUH�� VLPXODWLRQ�� V\QWKHVLV� DQG� IRUPDO�YHULILFDWLRQ.
Esterel programs are built from combinationally broadcasted signals using concurrency, sequencing, pausing, preemption, and communication statements. All statements run on a unique base clock (tick), mapped to the hw clock for synchronous circuit designs.
module Example:input I, Rst, Susp;output X, Y;loopsuspendsustain X
||await 5 I;sustain Y
when Suspeach Rstend module
Esterel is used for control-dominated hw design by major electronic companies, but in some applications the single-clock constraint is too strong. The goal of this work is to present a practical method to extend Esterel to multiple clocks.
HIGH LEVEL SYSTEM DESIGN p 5
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IP Esterel Model
Domainclk1
Domainclk2
Domainclk3
tick
Respect the relationship between the clocks in Esterel simulation environment, according to the real frequencies.
The input domain clocks clk1, clk2 and clk3 are generated from the
global Esterel base clock.
Each domain is represented by an Esterel module constrained to work only when its clock signal is active.
Domains are directly connected to their external IOs.
Domains are connected with each other through synchronizers.
HIGH LEVEL SYSTEM DESIGN p 6
0XOWLFORFN LQ (VWHUHO��LPSOHPHQWDWLRQ�GHWDLOVmodule :constant Shift: integer;constant Period: integer;output Clock;
await Shift times tick;loop
emit Clockeach (Period/2) tick
end module
module ClockGenerator :constant Shift: integer;constant Period: integer;output Clock;
await Shift times tick;loop
emit Clockeach (Period/2) tick
end module
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• EXLOGLQJ�WKHP�LQWHUQDOO\�IURP�WKH�WLFN��WKURXJK�D�JHQHUDWRU�ZLWK�SKDVH�DQG�SHULRG�
+RZ�WR�XVH�FORFN�JHQHUDWRUV�WR�UXQ�GLIIHUHQW�FORFN�GRPDLQ�PRGXOHV2: VXVSHQG modules when clocks absent and
maintain exchanged signals in the environment1: LQVWDQWLDWH the clock generatorsrun ClockGenerator[
constant 4 / Period; constant 2 / Shift;signal clk1 / Clock]
||run ClockGenerator [
constant 6 / Period;constant 3 / Shift;signal clk2 / Clock]
suspendrun p1 [o1 / output1]
when immediate not clk1||
suspendrun p2 [i2 / input2]
when immediate not clk2||
sustain {i2 <= o1 and clk1,i2 <= pre(o1) and not clk1}
HIGH LEVEL SYSTEM DESIGN p 7
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Clock domain 1
Clock domain 2
Clock domain 3
I/O
I/O
resynchro resynchro
resynchro
I/O
tick
clk3 clk2clk1vhdl generation
EntityClockdomain 2
EntityClockdomain 3
vhdlgeneration
vhdl generation
EntityClockdomain 1
port (clk:rst:
…..)
Clock domain 1
Clock domain 2
Clock domain 3
I/O
I/O
resynchro resynchro
resynchro
I/O
tick
clk3 clk2clk1
Clock domain 1
Clock domain 2
Clock domain 3
I/O
I/O
resynchro resynchro
resynchro
I/O
ticktick
clk3clk3 clk2clk2clk1clk1vhdl generation
EntityClockdomain 2
EntityClockdomain 3
vhdlgeneration
vhdl generation
EntityClockdomain 1
port (clk:rst:
…..)
vhdl top level
clk
clk
clkclk2
clk1
clk3
rst
rst
rstA
rst
rstB
I/O I/O I/O
Clock Domainclk1
Clock Domainclk3
Clock Domainclk2
vhdl top level
clk
clk
clkclk2
clk1
clk3
rst
rst
rstA
rst
rstB
I/O I/O I/O
Clock Domainclk1
Clock Domainclk3
Clock Domainclk2
The modules of each clock domains are dumped into separate HDL files.
A top level VHDL entity is manually written, instantiating the clock domain components
and connecting ports, clocks and resets
vhdl top level
clk
clk
clk2
clk1
clk3
rst
clkrst
rstA
rst
rstB
I/O I/O I/O
Clock Domainclk1
Clock Domain clk3
Clock Domainclk2
clkrst
clkrst
vhdl top level
clk
clk
clk2
clk1
clk3
rst
clkrstclkrst
rstA
rst
rstB
I/O I/O I/O
Clock Domainclk1
Clock Domain clk3
Clock Domainclk2
clkrstclkrst
clkrstclkrst
Within each clock domain, modular compiling is performed from Esterel to VHDL
1
2
3
HIGH LEVEL SYSTEM DESIGN p 8
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Clock Domain A
signal to synchronize
clkB
signal resynchronized
Clock Domain B
module resynchro:input R;output D: reg;signal { R1 } : reg in
sustain next { R1 <= R, D <= R1 }end signalend module
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HIGH LEVEL SYSTEM DESIGN p 9
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HIGH LEVEL SYSTEM DESIGN p 10
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Results:
Two VHDL entities generated for each domain.
Synthesis run with Synopsys Design Compiler 2003.03
No area overhead if compared with manually written VHDL.
No timing/DFT issues.
Simulations run through a VHDL test bench show a correct behavior with all foreseen frequency relationships
HIGH LEVEL SYSTEM DESIGN p 11
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Video Interface 1
FIFOand
bufferingcontrol
Video Interface 2
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RXWSXW�SRUW
64 bits
Video Interface 1clock domain
Video Interface 2clock domain
Functional clock
domainConfiguration
registers
FrameProcessing and
resynchronization
FrameProcessing and
resynchronization
OutputProtocolcontroller
Video Interface 1
FIFOand
bufferingcontrol
Video Interface 2
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RXWSXW�SRUW
64 bits
Video Interface 1clock domain
Video Interface 2clock domain
Functional clock
domainConfiguration
registers
FrameProcessing and
resynchronization
FrameProcessing and
resynchronization
OutputProtocolcontroller
Three clock domains are involved.
The double stage synchronizer has been use to secure data writing from the video interfaces to the buffering system.
A VHDL top-level has been created connecting the clock domain components.
Synthesis was run with Synopsys Design Compiler 2003.03 and results compared with hand-written Verilog, showing:• no timing/DFT issues;• a total 5% gain in area occupation.
Simulations run under the Reference Test Bench show a correct behavior
HIGH LEVEL SYSTEM DESIGN p 12
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