14. November 2007 Theo Mustermann

Unsere Ziele Das Forschungszentrum Jülich im Fokus

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Strained Si Nanowire Tunnel FETs and

Inverters

Qing-Tai Zhao

Peter Grünberg Institut (PGI-9)

Forschungszentrum Jülich, 52425 Jülich, Germany

Peter Grünberg Institute (PGI-9) 2

Outline

• Introduction

• Scaled Strained Si NW TFETs and Inverters

• New structures and new materials for TFETs

• Summary

Peter Grünberg Institute (PGI-9) 3

STEEP SLOPE DEVICES: Tunnel FETs

Dynamic power dissipation

~ VDD2 . f

Static power dissipation

~ VDD . IT . exp (IT/S)

A. Ionescu, H. Riel

Nature 2011

For MOSFET with ideal SS,

60 mV of VDD decrease results in 10 x Ioff

Peter Grünberg Institute (PGI-9) 4

At equal standby power and switching

energy, TFET logic can operate with a ~8x

performance compared to MOSFET. U. E. Avci et al. (Intel), VLSI 2011

TFET vs MOSFET: Operation

Peter Grünberg Institute (PGI-9) 5

Band-to-Band Tunnel FET Challenges:

High on-currents

Steep slope for a large ID range

Ambipolar switching

Steep tunneling junctions

Trap assisted tunneling

Metal gate

TAT

TAT sets in at low VGS

BTBT

Vandooren et al. SSE 83,(2013)

Peter Grünberg Institute (PGI-9) 6

Eg , m*, band alignment in heterostructures

Si, strained Si, SiGe, … sGe, GeSn…..

Electrostatics: = dop + ch

dop : Tunnel-junctions: steep profiles, no defects

ch : Device layout : planar NW

Band to band tunneling

λ : Screening length of

electrical potential

Eg: Bandgap

m*: Effective mass

Reviews: J. Knoch et. al in „Nanoelectronics and IT“ ed. R. Waser, J. Wiley, (2012) p.341

A. Seabaugh & Q. Zhang, Proc. IEEE 2010 DOI:0.1109/JPROC.2010.2070470

Drain Drain

Source

Gate

Source

Gate

smaller Eg

)(3

24exp~

g

23

g

WKBEq

EmTIds

Peter Grünberg Institute (PGI-9) 7

Process to form p- and n-Tunnel FETs

Tilted ion implantation with TiN gate as shadow mask into the SILICIDE

sSi NW array

HfO2/TiN

Peter Grünberg Institute (PGI-9) 8

sSi NW array

HfO2/TiN

S/D silicidation

L. Knoll et al. ESSDERC 2012

Process to form p- and n-Tunnel FETs

Tilted ion implantation with TiN gate as shadow mask into the SILICIDE

Peter Grünberg Institute (PGI-9) 9

Process to form p- and n-Tunnel FETs

sSi NW array

HfO2/TiN

S/D silicidation

B+ implant at 135°

B+ implant

Tilted ion implantation with TiN gate as shadow mask into the SILICIDE

Peter Grünberg Institute (PGI-9) 10

Process to form p- and n-Tunnel FETs

sSi NW array

HfO2/TiN

S/D silicidation

B+ implant at 135°

As+ implant

As+ implant at 45°

Tilted ion implantation with TiN gate as shadow mask into the SILICIDE

Peter Grünberg Institute (PGI-9) 11

Process to form p- and n-Tunnel FETs

sSi NW array

HfO2/TiN

S/D silicidation

B+ implant at 135°

As+ implant at 45°

Out diffusion at 450°C

Tilted ion implantation with TiN gate as shadow mask into the SILICIDE

Peter Grünberg Institute (PGI-9) 12

0 5 10 15 2010

1

102

103

104

105

Coun

ts

Depth (nm)

Ni

As

1.4nm/dec

0 5 10 15 20 25 30 35 4010

0

101

102

103

104

105

Co

un

ts

depth (nm)

3.2nm/dec

500°C 1min

B+ implantationNiSi2

Steep junction formed by IIS

5keV As into NiSi2: 750°60s

Very steep junctions !

implant

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Doped silicide contact of sSOI NW TFETs

Advantages of IIS with NiSi2 • Steep junctions • Perfect gate alignment • Low S/D resistance • Less defects in Si (Less TAT)

Peter Grünberg Institute (PGI-9) 14

Complementary NW-array TFETs

L. Knoll et al. EDL34 (6) 813 (2013)

High Ion (VDS=0.5V):

10.3 µA/µm for the p-TFET

18.3 µA/µm for the n-TFET

Peter Grünberg Institute (PGI-9) 15

L. Knoll et al. EDL34 (6) 813 (2013)

SS (min)~30mV/dec

Ambipolar characteristics due to

symmetric doping.

Complementary NW-array TFETs

Peter Grünberg Institute (PGI-9) 16

Suppressed TAT by pulse measurements

More results will be presented in IEDM 2013

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First logic circuits:

Complementary NW-array TFET Inverter

L. Knoll et al. EDL34 (6) 813 (2013)

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First sSi-TFET-Inverters:

L. Knoll et al. EDL34 (6) 813 (2013)

Voltage transfer characteristics (VTC):

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First sSi-TFET-Inverters:

L. Knoll et al. EDL34 (6) 813 (2013)

Overshoot due to enhanced

Miller capacitance

S. Mookerjea et al. EDL 30 (2009)

-0.5

0.0

0.5

1.0

1.5

VIN

,VO

UT (

V)

0 25 50 75

VOUT

@VDD

=1V

Time (ns)

Inverter time response:

fall time ~2 ns;

Voltage transfer characteristics (VTC)

Peter Grünberg Institute (PGI-9) 20

10nm Si GAA NW-TFET

NW array

Lars Knoll Proc. ULIS conf. 2013

Optimized electrostatics by GAA

Higher current: 75µA/µm @VDS=1V

Smaller SS

suppressed ambipolarity due to

different doping at drain side

Peter Grünberg Institute (PGI-9) 21

Nanowires outperform planar devices !

T- dependence: planar vs NW Si TFETs

Steeper

Slopes

and less

TAT

with NWs

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Benchmarking: Si & Ge TFETs

11

11

VDD=1.0V

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10nm Si GAA NW-TFET

µA/µm

Nikonov et al. IEDM 2012

TARGET

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10nm Si GAA NW-TFET

µA/µm

Nikonov et al. IEDM 2012

TARGET

We need ~10 x more Ion

at Vdd = VG = 0.3 V !

High strain

New material: sGe, GeSn

Peter Grünberg Institute (PGI-9) 25

Implementation of local strain at source

Smaller Eg at source higher BTBT

Larger Eg at drain suppressed

ambipolarity

• Strain accumulation through

relaxed pads

• Si-NW tensile strained up to

4.5%

reduces 𝑬𝑮 to 0.5 eV

R.A. Minamisawa et al., Nature Communications, 2013

See Poster No. 9, by Lars Knoll et al.

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SiGeSn Tunnel FET

S. Wirths et al., Appl. Phys. Lett. 2013

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SiGeSn Tunnel FET

S. Wirths et al., Appl. Phys. Lett. 2013

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• Box-shaped doping profile

• ECV: B-doping ~ 1019 cm-3

• AFM: rms = 0.8 nm

SiGeSn Tunnel FET

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NW TFETs:

• Improved tunneling junction by IIS and DS

• Scaled NW diameter higher Ion (75µA/µm @ 1V)

less TAT, smaller SS

TFET inverters:

• High VTC gain

• Sharp Transition at VDD=0.2V

Future: highly strained Si NW structure

strained Ge …Si-Ge-Sn

…..may become competitive with III-V !

Conclusions

Peter Grünberg Institute (PGI-9) 30

Acknowledgements

Lars Knoll

Simon Richter

Stephan Wirths

Matthias Schmidt

Sebastian Bläser

Gia Vinh Luong

Anna Schäfer

Alexander Nichau

Andreas Tiedemann

Patric Bernardy

Dan Buca

Jürgen Schubert

Siegfried Mantl

sponsored by:

Peter Grünberg Institute 9

EPFL Adrian Ionescu (coord.)

IBM, RWTH Aachen, LETI, IUNET

Globalfoundries, Intel Mobile

Jülich

Helmholtz Nanofacility

K.Bourdelle