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Von Neumann Architecture Computer Organisation

Loren Al Hamwi

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• What are the important features of Von Neumann Architecture?

- Why is processor speed limited in the Von Neumann Architecture?

• How does the Fetch-Decode-Execute cycle work?

What is Von Neumann Architecture?

Digital Computer- 4 parts:

1.Processor design (Arithmetic & control units + along with internal memory)

2.Memory to store data and instructions3.I/O devices4.Secondary storage

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Processor

Main Memory

Arithmetic & Logic Unit

Control UnitInput Devices

Output Devices

Mass Storage

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Serial Nature

There is one bus used to transport data and instructions

Only One Instruction at a Time

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Think about how programs are written in sequences….. .Instructions are stored in CPU registers .Locations are directly modified as a result of instruction execution

Fetch

DecodeExecute

Why Von Neumann Architecture?

These sequences of instructions relate to the serial nature of Von Neumann processors.

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Registers:

1-Program Counter =>PC 2-Memory Address Register =>MAR 3-Memory Data Register =>MDR 4-Current Instruction Register =>CIR 5-Accumulator =>ACC

Other Important Components:

1-Arithmetic and Logic Unit =>ALU 2-Control Unit =>CU 3-Buses

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Processor

Arithmetic & Logic Unit

Control Unit

PC

MAR

MDR

CIR

ACC

Primary Memory

Fetch Decode Execute

Start Start Start

Stop

Stop

Stop

Copy address

from PC to MAR

Get data from

primary memory and copy to

MDRCopy from MDR to CIR

Increment PC

Split opcode

from data (address) in

MDRControl unit interprets opcode

(Data) Address copied

from CIR to MARGet data from

primary memory and copy to MDR

Instruction executed

+1

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Decode: Splitting an instruction

Opcode

Operand

Opcode

Operand 1

Operand 2

bit-15

bit-15

bit 0

bit 0

Instruction

Data or Address

Result stored in Accumulator

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Executing instructions:

. Calculations: -Contents of MDR sent to MDR

. Jump Instructions: -Contents of MDR sent to PC

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Thank You for Your Attention and Time